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- Modify the freebios tree so the pci config space api is mostly in sync between

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code that runs without ram and code that runs with ram.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@869 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
2003-06-12 19:23:51 +00:00
parent 540ae01cd3
commit 7a5416af95
9 changed files with 174 additions and 226 deletions
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15
src/southbridge/amd/amd8111/amd8111_lpc.c
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@@ -1,3 +1,6 @@
/*
* (C) 2003 Linux Networx
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -94,24 +97,24 @@ static void lpc_init(struct device *dev)
#if 0
/* IO APIC initialization */
pci_read_config_byte(dev, 0x4B, &byte);
byte = pci_read_config8(dev, 0x4B);
byte |= 1;
pci_write_config_byte(dev, 0x4B, byte);
pci_write_config8(dev, 0x4B, byte);
setup_ioapic();
#endif
/* posted memory write enable */
pci_read_config_byte(dev, 0x46, &byte);
pci_write_config_byte(dev, 0x46, byte | (1<<0));
byte = pci_read_config8(dev, 0x46);
pci_write_config8(dev, 0x46, byte | (1<<0));
/* power after power fail */
pci_read_config_byte(dev, 0x43, &byte);
byte = pci_read_config8(dev, 0x43);
if (pwr_on) {
byte &= ~(1<<6);
} else {
byte |= (1<<6);
}
pci_write_config_byte(dev, 0x43, byte);
pci_write_config8(dev, 0x43, byte);
}