cpu/intel/car/core2: Prepare for POSTCAR_STAGE support

Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is
also needed for future C_ENVIRONMENT_BOOTBLOCK.

When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it
is identical.

Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/cpu/intel/car/core2/cache_as_ram.S

@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+#define CPU_PHYSMASK_HI  (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+.code32
+_cache_as_ram_setup:
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) >> 1), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRR_DEF_TYPE_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRR_PHYS_BASE(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRR_PHYS_MASK(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	movl	$CPU_PHYSMASK_HI, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRR_DEF_TYPE_MSR, %ecx
+	rdmsr
+	orl	$MTRR_DEF_TYPE_EN, %eax
+	wrmsr
+
+	/* Enable L2 cache. */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* Clear the cache memory region. This will also fill up the cache. */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE >> 2), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$CR0_CacheDisable, %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRR_PHYS_BASE(1), %ecx
+	xorl	%edx, %edx
+	/*
+	 * IMPORTANT: The following calculation _must_ be done at runtime. See
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl	$copy_and_run, %eax
+	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRR_PHYS_MASK(1), %ecx
+	movl	$CPU_PHYSMASK_HI, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
+	wrmsr
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
+	movl	%eax, %cr0
+
+	/* Setup the stack. */
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	romstage_main
+
+	/* Should never see this postcode */
+	post_code(POST_DEAD_CODE)
+
+.Lhlt:
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
+_cache_as_ram_setup_end:

src/cpu/intel/socket_BGA956/Makefile.inc

@@ -8,6 +8,11 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+ifneq ($(CONFIG_POSTCAR_STAGE),y)
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+else
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+endif
+
 romstage-y += ../car/romstage.c

src/cpu/intel/socket_mFCPGA478/Makefile.inc

@@ -11,5 +11,11 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
+ifneq ($(CONFIG_POSTCAR_STAGE),y)
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+else
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+endif
+
 romstage-y += ../car/romstage.c

src/cpu/intel/socket_mPGA478MN/Makefile.inc

@@ -9,6 +9,11 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+ifneq ($(CONFIG_POSTCAR_STAGE),y)
 cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+else
+cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+postcar-y += ../car/p4-netburst/exit_car.S
+endif
+
 romstage-y += ../car/romstage.c