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mb/google/deltaur: Configure GPIO B11 as PMCALERT

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GPIO B11 pin should be configured as PMCALERT function. This is
required for the intergrated USB-C feature to work in the SOC

BUG=b:154778458, b:156288164
TEST= build and boot coreboot image on deltan. Test Type-C port
enumeration on Chrome OS

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Anil Kumar
2020-05-13 13:07:26 -07:00
committed by Tim Wawrzynczak
parent 2412924bc7
commit 7ac6a987d0
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/google/deltaur/variants/baseboard/gpio.c
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@@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = {
/* B10 : GPP_B10 ===> NC */ /* B10 : GPP_B10 ===> NC */
PAD_NC(GPP_B10, NONE), PAD_NC(GPP_B10, NONE),
/* B11 : GPP_B11 ==> TBT_I2C_INT# */ /* B11 : GPP_B11 ==> TBT_I2C_INT# */
PAD_CFG_GPI_APIC(GPP_B11, NONE, PLTRST, LEVEL, INVERT), PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* B12 : GPP_B12 ==> SIO_SLP_S0# */ /* B12 : GPP_B12 ==> SIO_SLP_S0# */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* B13 : PLTRST# ==> PCH_PLTRST# */ /* B13 : PLTRST# ==> PCH_PLTRST# */