intel/{i945,pineview},i82801gx: Move enable_smbus() call
Change-Id: I7a9e613f9a142e04030672f85ea80c56151be3c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Patrick Georgi
parent
a28ee1b186
commit
7adc370dc7
@@ -61,9 +61,6 @@ void mainboard_romstage_entry(void)
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s3resume = southbridge_detect_s3_resume();
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s3resume = southbridge_detect_s3_resume();
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/* Enable SPD ROMs and DDR-II DRAM */
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enable_smbus();
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mainboard_pre_raminit_config(s3resume);
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mainboard_pre_raminit_config(s3resume);
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if (CONFIG(DEBUG_RAM_SETUP))
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if (CONFIG(DEBUG_RAM_SETUP))
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@@ -51,8 +51,6 @@ void mainboard_romstage_entry(void)
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enable_lapic();
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enable_lapic();
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enable_smbus();
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/* Perform some early chipset initialization required
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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* before RAM initialization can work
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*/
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*/
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@@ -73,6 +73,9 @@ void i82801gx_early_init(void)
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{
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{
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uint8_t reg8;
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uint8_t reg8;
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uint32_t reg32;
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uint32_t reg32;
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enable_smbus();
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/* Setting up Southbridge. In the northbridge code. */
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/* Setting up Southbridge. In the northbridge code. */
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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printk(BIOS_DEBUG, "Setting up static southbridge registers...");
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i82801gx_setup_bars();
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i82801gx_setup_bars();
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