Revert r5902 to make code more readable again. At least three people like to

have this go away again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>                                                                          
Acked-by: Kevin O'Connor <kevin@koconnor.net>                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/intel/car/cache_as_ram.inc

@@ -21,7 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic_def.h>
@@ -29,7 +28,8 @@
 #define CacheSize		CONFIG_DCACHE_RAM_SIZE
 #define CacheBase		(0xd0000 - CacheSize)
 
-	save_bist_result()
+	/* Save the BIST result. */
+	movl	%eax, %ebp
 
 CacheAsRam:
 	/* Check whether the processor has HT capability. */
@@ -257,7 +257,10 @@ clear_fixed_var_mtrr_out:
 	wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-	enable_cache()
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
 
 	/* Read the range with lodsl. */
 	movl	$CacheBase, %esi
@@ -318,7 +321,8 @@ clear_fixed_var_mtrr_out:
 	movl	$(CacheBase + CacheSize - 4), %eax
 	movl	%eax, %esp
 lout:
-	restore_bist_result()
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
 
 	/* We need to set EBP? No need. */
 	movl	%esp, %ebp
@@ -327,7 +331,10 @@ lout:
 
 	/* We don't need CAR from now on. */
 
-	disable_cache()
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
 
 	/* Clear sth. */
 	movl	$MTRRfix4K_C8000_MSR, %ecx
@@ -349,7 +356,10 @@ lout:
 	movl	$0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
 	wrmsr
 
-	enable_cache();
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
 
 	/* Clear boot_complete flag. */
 	xorl	%ebp, %ebp