soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location

soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shuo Liu 2024-04-22 04:31:41 +08:00 committed by Felix Held
parent 71814b0e5b
commit 7b2b57b0b8
11 changed files with 6 additions and 6 deletions

View File

@ -22,7 +22,7 @@ DefinitionBlock(
{
Device (PCI0)
{
#include <soc/intel/xeon_sp/acpi/southcluster.asl>
#include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl>
#include <soc/intel/common/block/acpi/acpi/lpc.asl>
}

View File

@ -20,11 +20,11 @@ DefinitionBlock(
#include <cpu/intel/common/acpi/cpu.asl>
// CPX-SP ACPI tables
#include <soc/intel/xeon_sp/acpi/uncore.asl>
#include <soc/intel/xeon_sp/acpi/gen1/uncore.asl>
// LPC related entries
Scope (\_SB.PC00)
{
#include <soc/intel/xeon_sp/acpi/pch.asl>
#include <soc/intel/xeon_sp/acpi/gen1/pch.asl>
}
}

View File

@ -15,9 +15,9 @@ DefinitionBlock(
#include "acpi/platform.asl"
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <soc/intel/xeon_sp/acpi/uncore.asl>
#include <soc/intel/xeon_sp/acpi/gen1/uncore.asl>
Scope (\_SB.PC00)
{
#include <soc/intel/xeon_sp/acpi/pch.asl>
#include <soc/intel/xeon_sp/acpi/gen1/pch.asl>
}
}

View File

@ -3,7 +3,7 @@
/* This file should be included in the proper platform ACPI \_SB PCI scope */
/* GPIO */
#include <soc/intel/xeon_sp/acpi/gpio.asl>
#include <soc/intel/xeon_sp/acpi/gen1/gpio.asl>
/* LPC 0:1f.0 */
#include <soc/intel/common/block/acpi/acpi/lpc.asl>