sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drivers/intel/fsp2_0: Update MRC cache in ramstage

Browse Source 
Currently the MRC cache is updated in romstage, immediately after
returning from FSP-M. Since cbmem is not cached in romstage, the update
is slow (~6 ms on nissa). Specifically, the new MRC data returned by the
FSP is stored in the FSP reserved memory in cbmem, so hashing the new
data is slow.

Move the MRC cache update to ramstage, where cbmem is cached. On nissa,
this saves ~5 ms of boot time.

Before:
552:finished loading ChromeOS VPD (RW)                631,667 (16)
  3:after RAM initialization                          637,703 (6,036)
  4:end of romstage                                   650,307 (12,603)

After:
552:finished loading ChromeOS VPD (RW)                631,832 (15)
  3:after RAM initialization                          633,002 (1,169)
  4:end of romstage                                   645,582 (12,580)

In ramstage, save_mrc_data() takes ~138 us.

BUG=b:242667207
TEST=MRC caching still works as expected on nivviks - after clearing the
MRC cache, memory is retrained on the next boot, but cached data is used
on subsequent boots.

Change-Id: Ie6aa2dee83a3ab8913830746593935d36a034b8d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Reka Norman
2022-09-13 14:06:52 +10:00
committed by Felix Held
parent c4fbeacd01
commit 7b5a93153a
4 changed files with 58 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
View File

@@ -26,6 +26,7 @@
#define CBMEM_ID_FREESPACE 0x46524545
#define CBMEM_ID_FSP_RESERVED_MEMORY 0x46535052
#define CBMEM_ID_FSP_RUNTIME 0x52505346
#define CBMEM_ID_FSPM_VERSION 0x56505346
#define CBMEM_ID_GDT 0x4c474454
#define CBMEM_ID_HOB_POINTER 0x484f4221
#define CBMEM_ID_IGD_OPREGION 0x4f444749
@@ -108,6 +109,7 @@
{ CBMEM_ID_FREESPACE, "FREE SPACE " }, \
{ CBMEM_ID_FSP_RESERVED_MEMORY, "FSP MEMORY " }, \
{ CBMEM_ID_FSP_RUNTIME, "FSP RUNTIME" }, \
{ CBMEM_ID_FSPM_VERSION, "FSPM VERSION" }, \
{ CBMEM_ID_GDT, "GDT " }, \
{ CBMEM_ID_HOB_POINTER, "HOB " }, \
{ CBMEM_ID_IGD_OPREGION, "IGD OPREGION" }, \