cpu/intel: Indent with tabs
Fix the following error and warning detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no space before tabs TEST=Build and run on Galileo Gen2 Change-Id: I5bcd82561ef5856e99055d46528dcf3a283d2310 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@@ -45,7 +45,7 @@
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#define IA32_PLATFORM_DCA_CAP 0x1f8
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#define IA32_MISC_ENABLE 0x1a0
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#define MSR_TEMPERATURE_TARGET 0x1a2
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#define IA32_PERF_CTL 0x199
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#define IA32_PERF_CTL 0x199
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#define IA32_THERM_INTERRUPT 0x19b
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#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
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#define ENERGY_POLICY_PERFORMANCE 0
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@@ -53,7 +53,7 @@
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#define ENERGY_POLICY_POWERSAVE 15
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#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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#define MSR_LT_LOCK_MEMORY 0x2e7
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#define IA32_MC0_STATUS 0x401
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#define IA32_MC0_STATUS 0x401
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#define MSR_PIC_MSG_CONTROL 0x2e
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#define MSR_PLATFORM_INFO 0xce
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@@ -50,7 +50,7 @@
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(((1 << ((base)*5)) * (limit)) / 1000)
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#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
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C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
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(IRTL_1024_NS >> 10))
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(IRTL_1024_NS >> 10))
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/*
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* List of supported C-states in this processor. Only the ULT parts support C8,
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@@ -361,7 +361,7 @@ static void configure_pch_power_sharing(void)
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pch_power_ext = pcode_mailbox_read(MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT);
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printk(BIOS_INFO, "PCH Power: PCODE Levels 0x%08x 0x%08x\n",
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pch_power, pch_power_ext);
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pch_power, pch_power_ext);
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pmsync = RCBA32(PMSYNC_CONFIG);
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pmsync2 = RCBA32(PMSYNC_CONFIG2);
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@@ -532,19 +532,19 @@ static void configure_c_states(void)
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/* C-state Interrupt Response Latency Control 3 - package C8 */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS |
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C_STATE_LATENCY_CONTROL_3_LIMIT;
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C_STATE_LATENCY_CONTROL_3_LIMIT;
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wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);
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/* C-state Interrupt Response Latency Control 4 - package C9 */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS |
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C_STATE_LATENCY_CONTROL_4_LIMIT;
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C_STATE_LATENCY_CONTROL_4_LIMIT;
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wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);
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/* C-state Interrupt Response Latency Control 5 - package C10 */
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS |
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C_STATE_LATENCY_CONTROL_5_LIMIT;
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C_STATE_LATENCY_CONTROL_5_LIMIT;
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wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
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}
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}
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@@ -577,7 +577,7 @@ static void configure_misc(void)
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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@@ -147,8 +147,8 @@ void * asmlinkage romstage_main(unsigned long bist)
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const int num_guards = 4;
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const u32 stack_guard = 0xdeadbeef;
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u32 *stack_base = (void *)(CONFIG_DCACHE_RAM_BASE +
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CONFIG_DCACHE_RAM_SIZE -
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CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
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CONFIG_DCACHE_RAM_SIZE -
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CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE);
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printk(BIOS_DEBUG, "Setting up stack guards.\n");
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for (i = 0; i < num_guards; i++)
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@@ -221,7 +221,7 @@ static u32 northbridge_get_base_reg(struct device *dev, int reg)
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}
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static void fill_in_relocation_params(struct device *dev,
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struct smm_relocation_params *params)
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struct smm_relocation_params *params)
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{
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u32 tseg_size;
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u32 tsegmb;
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@@ -273,7 +273,7 @@ static void fill_in_relocation_params(struct device *dev,
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params->uncore_emrr_base.lo = emrr_base;
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params->uncore_emrr_base.hi = 0;
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params->uncore_emrr_mask.lo = (~(emrr_size - 1) & rmask) |
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MTRR_PHYS_MASK_VALID;
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MTRR_PHYS_MASK_VALID;
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params->uncore_emrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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@@ -297,7 +297,9 @@ static void setup_ied_area(struct smm_relocation_params *params)
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/* According to the BWG MP init section 2MiB of memory at IEDBASE +
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* 2MiB should be zeroed as well. However, I suspect what is intended
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* is to clear the memory covered by EMRR. TODO(adurbin): figure out if * this is really required. */
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* is to clear the memory covered by EMRR. TODO(adurbin): figure out if
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* this is really required.
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*/
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//memset(ied_base + (2 << 20), 0, (2 << 20));
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}
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