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vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7

Browse Source 
The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
This commit is contained in:
WANG Siyuan
2013-07-31 16:55:26 +08:00
committed by Bruce Griffith
parent f8bf5a10c5
commit 7b6d412dbc
51 changed files with 7109 additions and 12111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/vendorcode/amd/agesa/f16kb/AGESA.h
View File

@ -2882,6 +2882,7 @@ typedef struct {
IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control
IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control
IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control
IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround
} FCH_PLATFORM_POLICY;

15
src/vendorcode/amd/agesa/f16kb/Include/KeralaInstall.h → src/vendorcode/amd/agesa/f16kb/Include/KabiniFt3Install.h
View File

@ -2,9 +2,9 @@
/**
* @file
*
* Install of build options for a Kerala platform solution
* Install of build options for a Kabini platform solution
*
* This file generates the defaults tables for the "Kerala" platform solution
* This file generates the defaults tables for the "Kabini" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
@ -68,16 +68,16 @@
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "KabiniPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I'}
// This is the delivery package title, "KabiniPI "
// This string MUST be exactly 16 characters long
#define AGESA_PACKAGE_STRING {'K', 'a', 'b', 'i', 'n', 'i', 'P', 'I', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '1', '.', '0', ' ', ' ', ' ', ' '}
#define AGESA_VERSION_STRING {'V', '1', '.', '0', '.', '0', '.', '7', ' ', ' ', ' ', ' '}
// The Kerala solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets.
// The Kabini FT3 solution is defined to be family 0x16 models 0x00 - 0x0F in the FT3 sockets.
#define INSTALL_FT3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
@ -138,6 +138,7 @@
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
#define OPTION_MICROSERVER TRUE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

24
src/vendorcode/amd/agesa/f16kb/Include/OptionFamily16hInstall.h
View File

@ -127,6 +127,7 @@
extern F_PERFORM_EARLY_INIT_ON_CORE F16SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE F16KbLoadMicrocodePatchAtEarly;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F16KbEarlyInitBeforeApLaunchOnCoreTable[] =
{
@ -143,7 +144,7 @@
{SetRegistersFromTablesAfterApLaunch, PERFORM_EARLY_ANY_CONDITION},
{F16SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
#if OPTION_EARLY_SAMPLES == FALSE
{LoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
{F16KbLoadMicrocodePatchAtEarly, PERFORM_EARLY_ANY_CONDITION},
#endif
{NULL, 0}
};
@ -208,25 +209,24 @@
#endif
#if (AGESA_ENTRY_INIT_RECOVERY == TRUE) || (AGESA_ENTRY_INIT_EARLY == TRUE)
#define F16_KB_UCODE_002A
#define F16_KB_UCODE_0106
#define F16_KB_UCODE_7000
#define F16_KB_UCODE_7001
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST UINT8 ROMDATA CpuF16KbId7000MicrocodePatch[];
#undef F16_KB_UCODE_7000
#define F16_KB_UCODE_7000 CpuF16KbId7000MicrocodePatch,
#endif
extern CONST UINT8 ROMDATA arr1[];
#undef F16_KB_UCODE_002A
#define F16_KB_UCODE_002A arr1,
extern CONST UINT8 ROMDATA arr2[];
#undef F16_KB_UCODE_0106
#define F16_KB_UCODE_0106 arr2,
extern CONST UINT8 ROMDATA CpuF16KbId7001MicrocodePatch[];
#undef F16_KB_UCODE_7001
#define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch,
#endif
CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] =
{
F16_KB_UCODE_0106
F16_KB_UCODE_002A
F16_KB_UCODE_7001
F16_KB_UCODE_7000
NULL
};

10
src/vendorcode/amd/agesa/f16kb/Include/OptionFchInstall.h
View File

@ -241,6 +241,7 @@
#define FCH_NO_GPP_SUPPORT TRUE
#define FCH_NO_PCIB_SUPPORT TRUE
#define FCH_NO_PCIE_SUPPORT TRUE
#define BLDOPT_RTC_WORKAROUND TRUE
#else
#error FCH_SUPPORT: No chip type selected.
#endif
@ -929,6 +930,7 @@
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitMidUsbEhci,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
@ -1011,6 +1013,14 @@
#endif
#define DFLT_RTC_WORKAROUND FALSE
#ifdef BLDOPT_RTC_WORKAROUND
#undef CFG_FCH_RTC_WORKAROUND
#define CFG_FCH_RTC_WORKAROUND BLDOPT_RTC_WORKAROUND
#else
#undef CFG_FCH_RTC_WORKAROUND
#define CFG_FCH_RTC_WORKAROUND DFLT_RTC_WORKAROUND
#endif
CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
FP_FCH_INIT_RESET,

48
src/vendorcode/amd/agesa/f16kb/Include/OptionMemoryInstall.h
View File

@ -1263,16 +1263,34 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_KB_ODT_TRI_FT3 &KBSODdr3ODTTriEntFT3,
extern PSC_TBL_ENTRY KBSODdr3CSTriEntFT3;
#define PSC_TBL_KB_CS_TRI_FT3 &KBSODdr3CSTriEntFT3,
#undef PSC_TBL_KB_UDIMM3_S2D_FT3
#ifndef extern_S2DTblEntUFT3
#define extern_S2DTblEntUFT3
extern PSC_TBL_ENTRY S2DTblEntUFT3;
#endif
#define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3,
#endif
#if OPTION_UDIMMS
extern PSC_TBL_ENTRY KBMaxFreqTblEntU;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ &KBMaxFreqTblEntU,
extern PSC_TBL_ENTRY KBDramTermTblEntU;
#define PSC_TBL_KB_UDIMM3_DRAM_TERM &KBDramTermTblEntU,
extern PSC_TBL_ENTRY KBSAOTblEntU3;
#define PSC_TBL_KB_UDIMM3_SAO &KBSAOTblEntU3,
#if (OPTION_MICROSERVER == TRUE)
extern PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntMicroSrvU6L,
#else
extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L,
#endif
extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L,
#if OPTION_FT3_SOCKET_SUPPORT
extern PSC_TBL_ENTRY KBDramTermTblEntUFT3;
#define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3 &KBDramTermTblEntUFT3,
extern PSC_TBL_ENTRY KBSAOTblEntU3FT3;
#define PSC_TBL_KB_UDIMM3_SAO_FT3 &KBSAOTblEntU3FT3,
#endif
#undef PSC_TBL_KB_UDIMM3_S2D_FT3
extern PSC_TBL_ENTRY S2DTblEntUFT3;
#ifndef extern_S2DTblEntUFT3
#define extern_S2DTblEntUFT3
extern PSC_TBL_ENTRY S2DTblEntUFT3;
#endif
#define PSC_TBL_KB_UDIMM3_S2D_FT3 &S2DTblEntUFT3,
#endif
#if OPTION_SODIMMS
@ -1299,10 +1317,6 @@ BOOLEAN MemFS3DefConstructorRet (
#define PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L &KBMaxFreqTblEntSoDwnPlusSODIMM6L,
extern PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn;
#define PSC_TBL_KB_SODWN_MAX_FREQ &KBMaxFreqTblEntSoDwn,
extern PSC_TBL_ENTRY KBMaxFreqTblEntU6L;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_6L &KBMaxFreqTblEntU6L,
extern PSC_TBL_ENTRY KBMaxFreqTblEntU4L;
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L &KBMaxFreqTblEntU4L,
#undef PSC_TBL_KB_SODIMM3_S2D_FT3
#define PSC_TBL_KB_SODIMM3_S2D_FT3
#endif
@ -1334,8 +1348,8 @@ BOOLEAN MemFS3DefConstructorRet (
#ifndef PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
#define PSC_TBL_KB_UDIMM3_MAX_FREQ_4L
#endif
#ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM
#define PSC_TBL_KB_UDIMM3_DRAM_TERM
#ifndef PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
#define PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
#endif
#ifndef PSC_TBL_KB_SODIMM3_DRAM_TERM
#define PSC_TBL_KB_SODIMM3_DRAM_TERM
@ -1355,8 +1369,8 @@ BOOLEAN MemFS3DefConstructorRet (
#ifndef PSC_TBL_KB_SODWN_SAO
#define PSC_TBL_KB_SODWN_SAO
#endif
#ifndef PSC_TBL_KB_UDIMM3_SAO
#define PSC_TBL_KB_UDIMM3_SAO
#ifndef PSC_TBL_KB_UDIMM3_SAO_FT3
#define PSC_TBL_KB_UDIMM3_SAO_FT3
#endif
#ifndef PSC_TBL_KB_CLK_DIS_FT3
#define PSC_TBL_KB_CLK_DIS_FT3
@ -1384,7 +1398,7 @@ BOOLEAN MemFS3DefConstructorRet (
};
PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = {
PSC_TBL_KB_UDIMM3_DRAM_TERM
PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
PSC_TBL_KB_SODIMM3_DRAM_TERM
PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
PSC_TBL_KB_SODWN_DRAM_TERM
@ -1401,7 +1415,7 @@ BOOLEAN MemFS3DefConstructorRet (
PSC_TBL_KB_SODIMM3_SAO
PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
PSC_TBL_KB_SODWN_SAO
PSC_TBL_KB_UDIMM3_SAO
PSC_TBL_KB_UDIMM3_SAO_FT3
PSC_TBL_END
};

6
src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h
View File

@ -360,6 +360,9 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
#define OPTION_MEM_RESTORE TRUE
#undef OPTION_DIMM_EXCLUDE
#define OPTION_DIMM_EXCLUDE TRUE
#ifndef OPTION_MICROSERVER
#define OPTION_MICROSERVER FALSE
#endif
#endif
#endif
@ -1811,7 +1814,8 @@ FCH_PLATFORM_POLICY FchUserOptions = {
CFG_FCH_SD_CLOCK_CONTROL, // CfgFchSdClockControl
CFG_FCH_SCI_MAP_LIST, // *CfgFchSciMapControl
CFG_FCH_SATA_PHY_LIST, // *CfgFchSataPhyControl
CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl
CFG_FCH_GPIO_CONTROL_LIST, // *CfgFchGpioControl
CFG_FCH_RTC_WORKAROUND // CfgFchRtcWorkaround
};
BUILD_OPT_CFG UserOptions = {

2
src/vendorcode/amd/agesa/f16kb/Legacy/PlatformMemoryConfiguration.inc
View File

@ -444,7 +444,7 @@ MEMORY_POWER_POLICY_OVERRIDE MACRO PowerPolicy:REQ
DB PowerPolicy
ENDM
MOTHER_RBOARD_LAYERS MACRO Layers:REQ
MOTHER_BOARD_LAYERS MACRO Layers:REQ
DB PSO_MOTHER_BOARD_LAYERS
DB 1
DB Layers

1
src/vendorcode/amd/agesa/f16kb/Legacy/agesa.inc
View File

@ -2453,6 +2453,7 @@ FCH_PLATFORM_POLICY STRUCT
CfgFchSciMapControl POINTER ? ; FCH SCI Mapping Control
CfgFchSataPhyControl POINTER ? ; FCH SATA PHY Control
CfgFchGpioControl POINTER ? ; FCH GPIO Control
CfgFchRtcWorkaround BOOLEAN ? ; FCH RTC Workaround
FCH_PLATFORM_POLICY ENDS

37
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c
View File

@ -139,13 +139,13 @@ F16KbPmCoreAfterReset (
LibAmdPciRead (AccessWidth32, PciAddress, &HwPsMaxVal, StdHeader);
HwPsMaxVal = ((CLK_PWR_TIMING_CTRL2_REGISTER *) &HwPsMaxVal)->HwPstateMaxVal;
// Launch each local core to perform steps 1 through 3.
// Launch each local core to perform steps 1 through 4.
TaskPtr.FuncAddress.PfApTask = F16KbPmCoreAfterResetPhase1OnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Launch each local core to perform steps 4 through 6.
// Launch each local core to perform steps 5 through 7.
TaskPtr.FuncAddress.PfApTaskI = F16KbPmCoreAfterResetPhase2OnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &HwPsMaxVal;
@ -176,25 +176,36 @@ F16KbPmCoreAfterResetPhase1OnCore (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 CofvidSts;
UINT64 LocalMsrRegister;
UINT64 PstateCtrl;
BOOLEAN SkipStep3;
UINT64 CofvidSts;
UINT64 LocalMsrRegister;
UINT64 PstateCtrl;
IDS_HDT_CONSOLE (CPU_TRACE, " F16KbPmCoreAfterResetPhase1OnCore\n");
// 1. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
// 1. If MSRC001_0071[CurPstate] = MSRC001_0071[CurPstateLimit], then skip step 3 for that core
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
if (((COFVID_STS_MSR *) &CofvidSts)->CurPstate == ((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit) {
SkipStep3 = TRUE;
} else {
SkipStep3 = FALSE;
}
// 2. Write 0 to MSRC001_0062[PstateCmd] on all cores in the processor.
PstateCtrl = 0;
LibAmdMsrWrite (MSR_PSTATE_CTL, &PstateCtrl, StdHeader);
// 2. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
// 3. Wait for MSRC001_0071[CurCpuFid, CurCpuDid] = [CpuFid, CpuDid] from
// MSRC001_00[6B:64] indexed by MSRC001_0071[CurPstateLimit].
do {
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
} while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
(((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
if (!SkipStep3) {
do {
LibAmdMsrRead (MSR_COFVID_STS, &CofvidSts, StdHeader);
LibAmdMsrRead ((UINT32) (MSR_PSTATE_0 + (UINT32) (((COFVID_STS_MSR *) &CofvidSts)->CurPstateLimit)), &LocalMsrRegister, StdHeader);
} while ((((COFVID_STS_MSR *) &CofvidSts)->CurCpuFid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuFid) ||
(((COFVID_STS_MSR *) &CofvidSts)->CurCpuDid != ((PSTATE_MSR *) &LocalMsrRegister)->CpuDid));
}
// 3. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
// 4. Write MSRC001_0061[PstateMaxVal] to MSRC001_0062[PstateCmd] on all
// cores in the processor.
LibAmdMsrRead (MSR_PSTATE_CURRENT_LIMIT, &LocalMsrRegister, StdHeader);
((PSTATE_CTRL_MSR *) &PstateCtrl)->PstateCmd = ((PSTATE_CURLIM_MSR *) &LocalMsrRegister)->PstateMaxVal;

2
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbDmi.c
View File

@ -344,7 +344,7 @@ DmiF16KbGetExtClock (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (EXTERNAL_CLOCK_DFLT);
return (EXTERNAL_CLOCK_100MHZ);
}
/* -----------------------------------------------------------------------------*/

4267
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch07000106_Enc.c → src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
View File

File diff suppressed because it is too large Load Diff

32
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
View File

@ -52,6 +52,7 @@
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "cpuEarlyInit.h"
#include "cpuFeatures.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_CPU_FAMILY_0X16_KB_F16KBINITEARLYTABLE_FILECODE
@ -88,6 +89,13 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable (
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
F16KbLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
@ -141,3 +149,27 @@ GetF16KbEarlyInitAfterApLaunchOnCoreTable (
*Table = F16KbEarlyInitAfterApLaunchOnCoreTable;
}
/*---------------------------------------------------------------------------------------*/
/**
* Update microcode patch in current processor for Family16h KB.
*
* This function acts as a wrapper for calling the LoadMicrocodePatch
* routine at AmdInitEarly.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[in] EarlyParams Service parameters.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F16KbLoadMicrocodePatchAtEarly (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
if (!IsFeatureEnabled (C6Cstate, &EarlyParams->PlatformConfig, StdHeader)) {
AGESA_TESTPOINT (TpProcCpuLoadUcode, StdHeader);
LoadMicrocodePatch (StdHeader);
}
}

3539
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbMicrocodePatch0700002A_Enc.c
View File

File diff suppressed because it is too large Load Diff

19
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbPciTables.c
View File

@ -710,23 +710,6 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersAfterApLaunch[] =
0x08000000, // RegMask
}}
},
// D18F3x200 - Performance Mode Control Register
// bits[3] EnMcqPrbPickThrottle = 0x1
// bits[2] EnDctOddToNcLnkDatXfr = 0x1
// bits[1] EnDctEvnToNcLnkDatXfr = 0x1
{
PciRegister,
{
AMD_FAMILY_16, // CpuFamily
AMD_F16_KB_ALL // CpuRevision
},
{AMD_PF_ALL}, // PlatformFeatures
{{
MAKE_SBDFO (0, 0, 24, FUNC_3, 0x200), // Address
0x0000000E, // RegData
0x0000000E, // RegMask
}}
},
// D18F4x118 - C-state Control 1
// bits[23:21] ClkDivisorCstAct1 = 0x0
// bits[19:18] CacheFlushTmrSelCstAct1 = 0x2
@ -828,7 +811,7 @@ STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F16KbPciRegistersAfterApLaunch[] =
}}
},
// D18F5x8C
// bits[15] = 0x1
// bits[15] EnSrqAllocGt31 = 0x1
{
PciRegister,
{

367
src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt.asm
View File

@ -1,367 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.XLIST
INCLUDE agesa.inc
INCLUDE cpcarmac.inc
.LIST
.586P
;===============================================
;===============================================
;==
;== M E M O R Y A B S E N T S E G M E N T
;==
;===============================================
;===============================================
.MODEL flat
.CODE
;======================================================================
; ExecuteFinalHltInstruction: Disables the stack and performs
; a hlt instruction on an AP.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteFinalHltInstruction
ExecuteFinalHltInstruction PROC NEAR C USES ESI EDI HaltFlags:DWORD, ApMtrrSettingList:PTR, StandardHeader:PTR
mov esi, StandardHeader ; The code must reference all parameters to avoid a build warning
mov esi, HaltFlags
mov edi, ApMtrrSettingList
; Do these special steps in case if the core is part of a compute unit
; Note: The following bits are family specific flags, that gets set during build time,
; and indicates things like "family cache control methodology", etc.
; esi bit0 = 0 -> not a Primary core
; esi bit0 = 1 -> Primary core
; esi bit1 = 0 -> Cache disable
; esi bit1 = 1 -> Cache enable
.if (esi & 2h)
AMD_CPUID CPUID_MODEL
shr eax, 20 ; AL = cpu extended family
cmp al, 05h ; Is this family 15h?
jne not_fam15_skip_combineCr0Cd ; Branch if not family15h
; Set CombineCr0Cd bit
mov ecx, CU_CFG3
_RDMSR
bts edx, (COMBINE_CR0_CD - 32)
_WRMSR
not_fam15_skip_combineCr0Cd:
; Clear the CR0.CD bit
mov eax, CR0 ; Make sure cache is enabled for all APs
btr eax, CR0_CD
btr eax, CR0_NW
mov CR0, eax ; Write back to CR0
.else
mov eax, CR0 ; Make sure cache is disabled for all APs
bts eax, CR0_CD ; Disable cache
bts eax, CR0_NW
mov CR0, eax ; Write back to CR0
.endif
.if (esi & 1h)
; This core is a primary core and needs to do all the MTRRs, including shared MTRRs.
mov esi, edi ; Get ApMtrrSettingList
; Configure the MTRRs on the AP so
; when it runs remote code it will execute
; out of RAM instead of ROM.
; Disable MTRRs and turn on modification enable bit
mov ecx, MTRR_SYS_CFG
_RDMSR
btr eax, MTRR_VAR_DRAM_EN ; Disable
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable
btr eax, MTRR_FIX_DRAM_EN ; Disable
_WRMSR
; Setup default values for Fixed-Sized MTRRs
; Set 7FFFh-00000h as WB
mov ecx, AMD_AP_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR
; Set 9FFFFh-80000h also as WB
mov ecx, AMD_AP_MTRR_FIX16k_80000
_WRMSR
; Set BFFFFh-A0000h as Uncacheable Memory-mapped IO
mov ecx, AMD_AP_MTRR_FIX16k_A0000
xor eax, eax
xor edx, edx
_WRMSR
; Set DFFFFh-C0000h as Uncacheable Memory-mapped IO
xor eax, eax
xor edx, edx
mov ecx, AMD_AP_MTRR_FIX4k_C0000
CDLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_D8000
jbe CDLoop
; Set FFFFFh-E0000h as Uncacheable Memory
mov eax, 18181818h
mov edx, eax
mov ecx, AMD_AP_MTRR_FIX4k_E0000
EFLoop:
_WRMSR
inc ecx
cmp ecx, AMD_AP_MTRR_FIX4k_F8000
jbe EFLoop
; If IBV provided settings for Fixed-Sized MTRRs,
; overwrite the default settings.
.if ((esi != 0) && (esi != 0FFFFFFFFh))
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
; While we are not at the end of the list
.while (ecx != CPU_LIST_TERMINAL)
; Ensure that the MSR address is valid for Fixed-Sized MTRRs
.if ( ((ecx >= AMD_AP_MTRR_FIX4k_C0000) && (ecx <= AMD_AP_MTRR_FIX4k_F8000)) || \
(ecx == AMD_AP_MTRR_FIX64k_00000) || (ecx == AMD_AP_MTRR_FIX16k_80000 ) || (ecx == AMD_AP_MTRR_FIX16k_A0000))
mov eax, dword ptr (AP_MTRR_SETTINGS ptr [esi]).MsrData
mov edx, dword ptr (AP_MTRR_SETTINGS ptr [esi+4]).MsrData
_WRMSR
.endif
add esi, sizeof (AP_MTRR_SETTINGS)
mov ecx, (AP_MTRR_SETTINGS ptr [esi]).MsrAddr
.endw
.endif
; Enable fixed-range and variable-range MTRRs
mov ecx, AMD_MTRR_DEFTYPE
_RDMSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Enable Top-of-Memory setting
; Enable use of RdMem/WrMem bits attributes
mov ecx, MTRR_SYS_CFG
_RDMSR
bts eax, MTRR_VAR_DRAM_EN ; Enable
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable
bts eax, MTRR_FIX_DRAM_EN ; Enable
_WRMSR
mov esi, (1 SHL FLAG_IS_PRIMARY)
.else ; end if primary core
xor esi, esi
.endif
; Make sure not to touch any Shared MSR from this point on
AMD_DISABLE_STACK_FAMILY_HOOK
bt esi, FLAG_IS_PRIMARY
.if (carry?)
; restore variable MTRR6 and MTRR7 to default states
mov ecx, AMD_MTRR_VARIABLE_MASK7 ; clear MTRRPhysBase6 MTRRPhysMask6
xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7
xor edx, edx
.while (cx >= AMD_MTRR_VARIABLE_BASE6)
_WRMSR
dec cx
.endw
.endif
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ret
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
PUBLIC ExecuteHltInstruction
ExecuteHltInstruction PROC NEAR C
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC NmiHandler
NmiHandler PROC NEAR C
iretd
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC GetCsSelector
GetCsSelector PROC NEAR C, CsSelector:PTR
push ax
push ebx
call FarCallGetCs
mov ebx, CsSelector
mov [ebx], ax
pop ebx
pop ax
ret
GetCsSelector ENDP
;======================================================================
; FarCallGetCs:
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
FarCallGetCs PROC FAR PRIVATE
mov ax, ss:[esp + 4]
retf
FarCallGetCs ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC SetIdtr
SetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
lidt fword ptr ss:[ebx]
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
PUBLIC GetIdtr
GetIdtr PROC NEAR C USES EBX, IdtPtr:PTR
mov ebx, IdtPtr
sidt fword ptr ss:[ebx]
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
PUBLIC ExecuteWbinvdInstruction
ExecuteWbinvdInstruction PROC NEAR C
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

173
src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahalt64.asm
View File

@ -1,173 +0,0 @@
;/**
; * @file
; *
; * Agesa pre-memory miscellaneous support, including ap halt loop.
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: CPU
; * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
; */
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
text SEGMENT
;======================================================================
; ExecuteFinalHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteFinalHltInstruction PROC PUBLIC
@@:
cli
hlt
jmp @B ;ExecuteHltInstruction
ExecuteFinalHltInstruction ENDP
;======================================================================
; ExecuteHltInstruction: Performs a hlt instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; eax, ebx, ecx, edx, esp
;
;======================================================================
ExecuteHltInstruction PROC PUBLIC
cli
hlt
ret
ExecuteHltInstruction ENDP
;======================================================================
; NmiHandler: Simply performs an IRET.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
NmiHandler PROC PUBLIC
iretq
NmiHandler ENDP
;======================================================================
; GetCsSelector: Returns the current protected mode CS selector.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
GetCsSelector PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetCsSelector ENDP
;======================================================================
; SetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
SetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
SetIdtr ENDP
;======================================================================
; GetIdtr:
;
; In:
; @param[in] IdtPtr Points to IDT table
;
; Out:
; None
;
; Destroyed:
; none
;
;======================================================================
GetIdtr PROC PUBLIC
; This stub function is here to avoid compilation errors.
; At this time, there is no need to provide a 64 bit function.
ret
GetIdtr ENDP
;======================================================================
; ExecuteWbinvdInstruction: Performs a wbinvd instruction.
;
; In:
; None
;
; Out:
; None
;
; Destroyed:
; None
;
;======================================================================
ExecuteWbinvdInstruction PROC PUBLIC
wbinvd ; Write back the cache tag RAMs
ret
ExecuteWbinvdInstruction ENDP
END

13
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchCommonCfg.h
View File

@ -370,11 +370,15 @@ typedef struct _SATA_ST {
/// @li <b>0</b> - disable
/// @li <b>1</b> - enable
///
BOOLEAN IdeEnable; ///< IdeEnable - Ide Controller Mode
BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE
/// @par
/// Sata IDE Controller set to Combined Mode
/// @li <b>0</b> - disable
/// @li <b>1</b> - enable
/// Sata IDE Controller Combined Mode
/// Enable - SATA controller has control over Port0 through Port3,
/// IDE controller has control over Port4 and Port7.
/// Disable - SATA controller has full control of all 8 Ports
/// when operating in non-IDE mode.
/// @li <b>0</b> - enable
/// @li <b>1</b> - disable
///
UINT8 SataClkMode; /// SataClkMode - Reserved
} SATA_ST;
@ -843,6 +847,7 @@ typedef struct {
TIMER_SMI LongTimer; ///< Long Timer SMI
TIMER_SMI ShortTimer; ///< Short Timer SMI
UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
} FCH_MISC;

3
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Common/FchDef.h
View File

@ -245,6 +245,7 @@ VOID ImcWakeup (IN VOID *FchDataPtr);
VOID ImcIdle (IN VOID *FchDataPtr);
BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
VOID SoftwareDisableImc (IN VOID *FchDataPtr);
///
@ -355,7 +356,7 @@ VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
///
/// Fch Sd Routines

7
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Fch.h
View File

@ -1617,8 +1617,13 @@ FCH_MISC_REGF0 EQU 0F0h
#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02
#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01
#define RTC_WORKAROUND_SECOND 0x00
#define RTC_VALID_SECOND_VALUE 0x59
#define RTC_SECOND_RESET_VALUE 0x30
#define RTC_SECOND_LOWER_NIBBLE 0x0F
#define RTC_VALID_SECOND_VALUE_LN 0x09
#ifndef FCH_DEADLOOP
#define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
#endif

13
src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c
View File

@ -77,21 +77,19 @@ ACPI_REG_WRITE FchYangtzeInitEnvHwAcpiMmioTable[] =
//
// HPET workaround
//
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, BIT7},
{PMIO_BASE >> 8, FCH_PMIOA_REG54 + 2, 0x7F, 0x00},
{PMIO_BASE >> 8, FCH_PMIOA_REGC4, (UINT8)~BIT2, BIT2},
{PMIO_BASE >> 8, FCH_PMIOA_REGC0, 0, 0x3D},
{PMIO_BASE >> 8, FCH_PMIOA_REGC0 + 1, 0x0, 0x04},
{PMIO_BASE >> 8, FCH_PMIOA_REGC2, 0x20, 0x58},
{PMIO_BASE >> 8, FCH_PMIOA_REGC2 + 1, 0, 0x40},
{PMIO_BASE >> 8, FCH_PMIOA_REGC2, (UINT8)~(BIT4), BIT4},
{PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x07},
{PMIO_BASE >> 8, FCH_PMIOA_REGCC, 0xF8, 0x03},
{PMIO_BASE >> 8, FCH_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},
{PMIO_BASE >> 8, 0x74 + 3, (UINT8)~BIT5, 0},
{PMIO_BASE >> 8, FCH_PMIOA_REGBA, (UINT8)~BIT3, BIT3},
{PMIO_BASE >> 8, FCH_PMIOA_REGBA + 1, (UINT8)~BIT6, BIT6},
{PMIO_BASE >> 8, FCH_PMIOA_REGBC, (UINT8)~BIT1, BIT1},
{PMIO_BASE >> 8, FCH_PMIOA_REGED, (UINT8)~(BIT0 + BIT1), 0},
{PMIO_BASE >> 8, 0xDC, 0x7C, BIT1},
{SMI_BASE >> 8, FCH_SMI_Gevent1, 0, 1},
@ -190,6 +188,11 @@ ProgramFchEnvHwAcpiPciReg (
if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
}
if ( LocalCfgPtr->Misc.NoneSioKbcSupport ) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2 + BIT1);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGED, AccessWidth8, ~(UINT32) ( BIT2 + BIT1), BIT2);
}
ProgramPcieNativeMode (FchDataPtr);
}

1
src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c
View File

@ -116,6 +116,7 @@ ProgramFchHwAcpiResetP (
LocalCfgPtr = (FCH_RESET_DATA_BLOCK *) FchDataPtr;
StdHeader = &((AMD_RESET_PARAMS *)FchDataPtr)->StdHeader;
RwPmio (FCH_PMIOA_REGC8, AccessWidth8, 0xEF, 0x0, StdHeader);
RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, 0, StdHeader);
RwPmio (FCH_PMIOA_REGD3, AccessWidth8, (UINT32)~BIT4, BIT4, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);

35
src/vendorcode/amd/agesa/f16kb/Proc/Fch/HwAcpi/HwAcpiReset.c
View File

@ -135,7 +135,18 @@ FchInitResetHwAcpi (
if (UserOptions.FchBldCfg->CfgFchSataPhyControl != NULL) {
ProgramFchSataPhyTbl ((UserOptions.FchBldCfg->CfgFchSataPhyControl), LocalCfgPtr);
}
//
// RTC Workaround for Daylight saving time enable bit
//
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, BIT0 ); // Enable DltSavEnable
Value = 0x0B;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= 0xFE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5E, AccessWidth8, 0, 0);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5F, AccessWidth8, 0xFE, 0 ); // Disable DltSavEnable
//
// Prevent RTC error
//
@ -148,6 +159,7 @@ FchInitResetHwAcpi (
Value = 0x08;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( !LocalCfgPtr->EcKbd ) {
//
// Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input
@ -156,6 +168,23 @@ FchInitResetHwAcpi (
}
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
if ( UserOptions.FchBldCfg->CfgFchRtcWorkAround ) {
Value = RTC_WORKAROUND_SECOND;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG70, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
if ( Value > RTC_VALID_SECOND_VALUE ) {
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value &= RTC_SECOND_LOWER_NIBBLE;
if ( Value > RTC_VALID_SECOND_VALUE_LN ) {
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
Value = RTC_SECOND_RESET_VALUE;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REG71, &Value, StdHeader);
}
}
Value = 0x09;
LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGC00, &Value, StdHeader);
LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGC01, &Value, StdHeader);
@ -189,14 +218,14 @@ FchInitResetHwAcpi (
//
// PciExpWakeStatus workaround
//
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
AsfPort++;
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG04, AccessWidth32, &GeventEnableBits);
ReadMem (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG00, AccessWidth32, &GeventValue);
if ( (GeventValue & GeventEnableBits) != 0 ) {
Value = 0x40;
LibAmdIoWrite (AccessWidth8, AsfPort, &Value, StdHeader);
}
ReadMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60, AccessWidth16, &AsfPort);
AsfPort++;
LibAmdIoRead (AccessWidth8, AsfPort, &Value, StdHeader);
if ((Value & (BIT2 + BIT0)) != 0) {
Value = 0x40;

37
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Imc/ImcLib.c
View File

@ -176,6 +176,43 @@ ImcSleep (
WaitForEcLDN9MailboxCmdAck (StdHeader);
}
/**
* SoftwareDisableImc - Software disable IMC strap
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
VOID
SoftwareDisableImc (
IN VOID *FchDataPtr
)
{
UINT8 ValueByte;
UINT8 PortStatusByte;
UINT32 AbValue;
UINT32 ABStrapOverrideReg;
AMD_CONFIG_PARAMS *StdHeader;
StdHeader = ((FCH_DATA_BLOCK *) FchDataPtr)->StdHeader;
GetChipSysMode (&PortStatusByte, StdHeader);
RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGC8 + 3, AccessWidth8, 0x7F, BIT7, StdHeader);
ReadPmio (0xBF, AccessWidth8, &ValueByte, StdHeader);
ReadMem ((ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), AccessWidth32, &AbValue);
ABStrapOverrideReg = AbValue;
ABStrapOverrideReg &= ~BIT2; // bit2=0 EcEnableStrap
WriteMem ((ACPI_MMIO_BASE + MISC_BASE + 0x84), AccessWidth32, &ABStrapOverrideReg);
ReadPmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte |= BIT1;
WritePmio (FCH_PMIOA_REGD7, AccessWidth8, &ValueByte, StdHeader);
ValueByte = 06;
LibAmdIoWrite (AccessWidth8, 0xcf9, &ValueByte, StdHeader);
FchStall (0xffffffff, StdHeader);
}
/**
* ImcEnableSurebootTimer - IMC Enable Sureboot Timer.

6
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c
View File

@ -210,12 +210,12 @@ FchProgramSataPhy (
SquelchValue[0] = (0x07 << 9);
SquelchValue[1] = (0x07 << 9);
for (PortNum = 0; PortNum < 2; PortNum ++) {
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x130 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x30 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 13)), (UINT32) (0x0 << 13), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x120 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x20 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x110 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, ( 0x10 + PortNum), StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C, AccessWidth32, (UINT32) (~(0x7 << 9)), SquelchValue[PortNum], StdHeader);
RwPci ((SATA_BUS_DEV_FUN << 16) + 0x080, AccessWidth16, 0x00, 0x010, StdHeader);
}

23
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c
View File

@ -165,13 +165,22 @@ FchInitMidProgramSataRegs (
FchSataMsiCapability = 0;
}
//
// Disable SATA FLR Capability
//
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0, StdHeader);
//
// Enabled SATA MSI capability
// SATA MSI and D3 Power State Capability MMC 0x2
//
if ( !FchSataMsiCapability ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x70 + 1), AccessWidth8, 0, 0, StdHeader);
if ( FchSataMsiCapability ) {
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x50, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x06, StdHeader);
} else {
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x060 + 1), AccessWidth8, 0, 0x70, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x070 + 1), AccessWidth8, 0, 0x00, StdHeader);
RwPci (((SATA_BUS_DEV_FUN << 16) + 0x050 + 2), AccessWidth8, 0xF1, 0x00, StdHeader);
}
//
// Sata Target Support 8 devices function
//
@ -286,8 +295,8 @@ FchInitLateProgramSataRegs (
RwMem ((Bar5 + 0x110 + (PortNumByte * 0x80)), AccessWidth32, 0xFFFFFFFF, 0x00);
}
if ( LocalCfgPtr->Sata.SataDevSlpPort0 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x0E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x02);
RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFEEF, BIT4 + BIT8);
} else {
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG55, AccessWidth8, 0, 0x00);
@ -297,8 +306,8 @@ FchInitLateProgramSataRegs (
}
}
if ( LocalCfgPtr->Sata.SataDevSlpPort1 ) {
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x3E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x01);
RwMem (ACPI_MMIO_BASE + GPIO_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x0E);
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x02);
RwMem ((Bar5 + 0x0F4), AccessWidth32, 0xFFFFFDEF, BIT4 + BIT9);
} else {
RwMem (ACPI_MMIO_BASE + IOMUX_BASE + FCH_GPIO_REG59, AccessWidth8, 0, 0x00);

12
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c
View File

@ -71,6 +71,7 @@ FchInitEnvSdProgram (
// SD Configuration
//
if ( LocalCfgPtr->Sd.SdConfig != SdDisable) {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x40);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, BIT0);
Sd30Control = 0;
SdData32 = 0x30FE00B2;
@ -83,8 +84,7 @@ FchInitEnvSdProgram (
} else if ( LocalCfgPtr->Sd.SdConfig == SdPio) {
SdData32 &= ~(BIT20 + BIT22 + BIT19); ///PIO
}
SdData32 |= (LocalCfgPtr->Sd.SdSpeed << 21) + (LocalCfgPtr->Sd.SdBitWidth << 28);
SdData32 |= BIT24;
SdData32 |= BIT24 + BIT21;
if ( LocalCfgPtr->Sd.SdHostControllerVersion == 1) {
SdData32 |= 0x3200;
if ( (ApuStepping & 0x0F) == 0) {
@ -109,12 +109,13 @@ FchInitEnvSdProgram (
Sd30Control |= (BIT16 + BIT17);
}
Sd30Control &= ~(BIT0 + BIT1);
Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities;
// Sd30Control |= LocalCfgPtr->Sd.SdrCapabilities;
Sd30Control |= LocalCfgPtr->Sd.SdReTuningMode << 14;
if ( LocalCfgPtr->Sd.SdHostControllerVersion == 2) {
Sd30Control &= 0xFFFF00FF;
Sd30Control |= ( BIT4 + BIT5 + BIT6 + BIT8 + BIT10 + BIT13 );
Sd30Control |= ( BIT0 + BIT1 + BIT8 + BIT10 + BIT13 );
}
Sd30Control |= ( BIT4 + BIT5 + BIT6 );
RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGD0 + 1, AccessWidth8, 0xFD, BIT1, StdHeader);
RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGA8, AccessWidth32, 0x3FFC, Sd30Control, StdHeader);
RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGB0 + 3, AccessWidth8, 0, LocalCfgPtr->Sd.SdHostControllerVersion, StdHeader);
@ -124,6 +125,7 @@ FchInitEnvSdProgram (
RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGF8, AccessWidth32, 0, 0x00010002, StdHeader);
RwPci ((SD_BUS_DEV_FUN << 16) + SD_PCI_REGFC, AccessWidth32, 0, 0x00014000, StdHeader);
} else {
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD3, AccessWidth8, 0xBF, 0x00);
RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGE8, AccessWidth8, 0xFE, 0x00);
}
}

36
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c
View File

@ -471,7 +471,7 @@ FchInitResetSpi (
SpiModeByte = LocalCfgPtr->Mode;
if (LocalCfgPtr->Mode) {
if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144)) {
if ((SpiModeByte == FCH_SPI_MODE_QUAL_114) || (SpiModeByte == FCH_SPI_MODE_QUAL_144) || (SpiModeByte == FCH_SPI_MODE_QUAL_112) || (SpiModeByte == FCH_SPI_MODE_QUAL_122) || (SpiModeByte == FCH_SPI_MODE_FAST)) {
if (FchPlatformSpiQe (FchDataPtr)) {
FchSetQualMode (SpiModeByte, StdHeader);
}
@ -671,6 +671,7 @@ FchConfigureSpiDeviceDummyCycle (
{
UINT16 Mode16;
UINT16 Value16;
UINT8 Value8;
UINT16 DummyValue16;
UINT16 CurrentDummyValue16;
UINT16 CurrentMode16;
@ -681,7 +682,8 @@ FchConfigureSpiDeviceDummyCycle (
DummyValue16 = 8;
switch (DeviceID) {
case 0x17BA20:
case 0x17BA20://N25Q064
case 0x16BA20://N25Q032
FchSpiTransfer (
0, //IN UINT8 PrefixCode,
@ -740,8 +742,34 @@ FchConfigureSpiDeviceDummyCycle (
TRUE,//IN BOOLEAN DataFlag,
TRUE //IN BOOLEAN FinishedFlag
);
FchStall (1000, StdHeader);
WriteIo8 ((UINT16) (0xCF9), 0x0E);
FchSpiTransfer (
0, //IN UINT8 PrefixCode,
0x85,//IN UINT8 Opcode,
(UINT8 *)(&Value8),//IN OUT UINT8 *DataPtr,
NULL,//IN UINT8 *AddressPtr,
0,//IN UINT8 Length,
FALSE,//IN BOOLEAN WriteFlag,
FALSE,//IN BOOLEAN AddressFlag,
TRUE,//IN BOOLEAN DataFlag,
FALSE //IN BOOLEAN FinishedFlag
);
Value8 &= ~ (0xf << 4);
Value8 |= (UINT8) (DummyValue16 << 4);
FchSpiTransfer (
0x06, //IN UINT8 PrefixCode,
0x81,//IN UINT8 Opcode,
(UINT8 *)(&Value8),//IN OUT UINT8 *DataPtr,
NULL,//IN UINT8 *AddressPtr,
0,//IN UINT8 Length,
TRUE,//IN BOOLEAN WriteFlag,
FALSE,//IN BOOLEAN AddressFlag,
TRUE,//IN BOOLEAN DataFlag,
TRUE //IN BOOLEAN FinishedFlag
);
// FchStall (1000, StdHeader);
// WriteIo8 ((UINT16) (0xCF9), 0x0E);
}
return TRUE;
default:

17
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c
View File

@ -66,6 +66,8 @@ FchEhciInitAfterPciInit (
AMD_CONFIG_PARAMS *StdHeader;
UINT32 PortNum;
UINT32 DrivingStrength;
UINT8 RetEfuseValue;
UINT32 UsbFuseCommonCalibrationValue;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
@ -122,8 +124,13 @@ FchEhciInitAfterPciInit (
RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x02));
FchStall (400, StdHeader);
RwMem (BarAddress + FCH_EHCI_BAR_REGD4, AccessWidth32, ~((UINT32) (0x02)), (UINT32) (0x0));
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00010000), BIT16);
RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr );
if ( RetEfuseValue == 0 ) {
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x00030000), BIT16);
} else {
UsbFuseCommonCalibrationValue = RetEfuseValue << 11;
RwMem (BarAddress + FCH_EHCI_BAR_REGC0, AccessWidth32, (UINT32) (~ 0x0003FF00), UsbFuseCommonCalibrationValue);
}
RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x01 << 6)), (UINT32) (0x01 << 6), StdHeader);
RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 8)), (UINT32) (0x01 << 8), StdHeader);
RwPci ((UINT32) Value + 0x50, AccessWidth32, ~ ((UINT32) (0x0F << 12)), (UINT32) (0x01 << 12), StdHeader);
@ -170,12 +177,6 @@ FchEhciInitAfterPciInit (
RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), 0);
RwMem (BarAddress + FCH_EHCI_BAR_REGB4, AccessWidth32, ~((UINT32) (1 << 12)), (UINT32) (0x1 << 12));
}
} else {
BarAddress = FCH_FAKE_USB_BAR_ADDRESS;
WritePci ((UINT32) Value + FCH_EHCI_REG10, AccessWidth32, &BarAddress, StdHeader);
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, BIT1, StdHeader);
RwMem (BarAddress + FCH_EHCI_BAR_REGBC, AccessWidth32, (UINT32)~( BIT12 + BIT14), BIT12 + BIT14);
RwPci ((UINT32) Value + FCH_EHCI_REG04, AccessWidth8, 0, 0, StdHeader);
}
ReadPmio (FCH_PMIOA_REGF0, AccessWidth8, &UsbS3WakeResumeOnlyDisable, StdHeader);

42
src/vendorcode/amd/agesa/f16kb/Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c
View File

@ -47,7 +47,35 @@
// Declaration of local functions
//
#define PRODUCT_INFO_REG1 0x1FC // Product Information Register 1
#define AMD_CPU_DEV_FUN ((0x18 << 3) + 3)
/**
* FchUsbCommonPhyCalibration - Config USB Common PHY
* Calibration
*
*
*
* @param[in] FchDataPtr Fch configuration structure pointer.
*
*/
UINT8
FchUsbCommonPhyCalibration (
IN FCH_DATA_BLOCK *FchDataPtr
)
{
UINT8 RetEfuseValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
ReadPci ((AMD_CPU_DEV_FUN << 16) + PRODUCT_INFO_REG1, AccessWidth8, &RetEfuseValue, StdHeader);
RetEfuseValue = ((RetEfuseValue & 0x1E) >> 1);
return RetEfuseValue;
}
/**
* FchXhciUsbPhyCalibrated - Config XHCI Phy
*
@ -133,11 +161,15 @@ FchXhciInitIndirectReg (
UINT32 RegValue;
FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader;
UINT8 RetEfuseValue;
UINT32 UsbFuseCommonCalibrationValue;
LocalCfgPtr = (FCH_DATA_BLOCK *)FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader;
DrivingStrength = 0;
FchXhciUsbPhyCalibrated (LocalCfgPtr);
RwXhci0IndReg ( FCH_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021, StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021, StdHeader);
@ -150,10 +182,16 @@ FchXhciInitIndirectReg (
}
RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x07)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG50, ~ ((UINT32) (0x0f)), ((UINT32) (0x06)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 4)), ((UINT32) (0x02 << 4)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8)), StdHeader);
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, 0, StdHeader); // For BTS
RetEfuseValue = FchUsbCommonPhyCalibration ( FchDataPtr );
if ( RetEfuseValue == 0) {
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FD00FF, (UINT32) BIT16 , StdHeader);
} else {
UsbFuseCommonCalibrationValue = RetEfuseValue << 11;
RwXhci0IndReg ( FCH_XHCI_IND60_REG08, 0x80FC00FF, UsbFuseCommonCalibrationValue , StdHeader);
}
for (Port = 0; Port < 2; Port ++) {
DrivingStrength = 0x1E4;

24
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h
View File

@ -3269,9 +3269,21 @@ typedef union {
#define DxFxxE4_xA0_LcL1ImmediateAck_OFFSET 23
#define DxFxxE4_xA0_LcL1ImmediateAck_WIDTH 1
#define DxFxxE4_xA0_LcL1ImmediateAck_MASK 0x800000
#define DxFxxE4_xA0_Reserved_31_24_OFFSET 24
#define DxFxxE4_xA0_Reserved_31_24_WIDTH 8
#define DxFxxE4_xA0_Reserved_31_24_MASK 0xFF000000
#define DxFxxE4_xA0_Reserved_24_24_OFFSET 24
#define DxFxxE4_xA0_Reserved_24_24_WIDTH 1
#define DxFxxE4_xA0_Reserved_24_24_MASK 0x01000000
#define DxFxxE4_xA0_Reserved_26_25_OFFSET 25
#define DxFxxE4_xA0_Reserved_26_25_WIDTH 2
#define DxFxxE4_xA0_Reserved_26_25_MASK 0x06000000
#define DxFxxE4_xA0_Reserved_27_27_OFFSET 27
#define DxFxxE4_xA0_Reserved_27_27_WIDTH 1
#define DxFxxE4_xA0_Reserved_27_27_MASK 0x08000000
#define DxFxxE4_xA0_Reserved_28_28_OFFSET 28
#define DxFxxE4_xA0_Reserved_28_28_WIDTH 1
#define DxFxxE4_xA0_Reserved_28_28_MASK 0x10000000
#define DxFxxE4_xA0_Reserved_31_29_OFFSET 29
#define DxFxxE4_xA0_Reserved_31_29_WIDTH 3
#define DxFxxE4_xA0_Reserved_31_29_MASK 0xE0000000
/// DxFxxE4_xA0
typedef union {
@ -3282,7 +3294,11 @@ typedef union {
UINT32 LcL1Inactivity:4; ///<
UINT32 Reserved_22_16:7; ///<
UINT32 LcL1ImmediateAck:1; ///<
UINT32 Reserved_31_24:8; ///<
UINT32 Reserved_24_24:1; ///<
UINT32 Reserved_26_25:2; ///<
UINT32 Reserved_27_27:1; ///<
UINT32 Reserved_28_28:1; ///<
UINT32 Reserved_31_29:3; ///<
} Field;

5040
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
View File

File diff suppressed because it is too large Load Diff

5
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c
View File

@ -461,10 +461,7 @@ GfxIntInfoTableInitKB (
SystemInfoTableV3.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940;
SystemInfoTableV3.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000;
SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo =
GPUCAPINFO_TMDS_HDMI_USE_SINGLE_PLL_MODE |
GPUCAPINFO_DP_USE_SINGLE_PLL_MODE |
GPUCAPINFO_DFS_BYPASS_DISABLE;
SystemInfoTableV3.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_DFS_BYPASS_DISABLE;
// GPUCAPINFO_DFS_BYPASS_ENABLE should be enabled by default for MOBILE systems
if ((Gfx->AmdPlatformType & AMD_PLATFORM_MOBILE) != 0) {

2
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c
View File

@ -133,7 +133,7 @@ GfxMidInterfaceKB (
Status = GfxGmcInitKB (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
//Status = GfxSamuInit (Gfx);
Status = GfxSamuInit (Gfx);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
Status = GfxInitSsid (Gfx);

5
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c
View File

@ -434,10 +434,13 @@ GNB_TABLE ROMDATA GfxGmcInitTableKB [] = {
GNB_ENTRY_WR (0x12, 0x3750, 0x18201015),
GNB_ENTRY_WR (0x12, 0x3754, 0x18201015),
GNB_ENTRY_WR (0x12, 0x253C, 0x000000B4),
GNB_ENTRY_WR (0x12, 0x2550, 0x000000A3),
GNB_ENTRY_WR (0x12, 0x2550, 0x000000B3),
GNB_ENTRY_WR (0x12, 0x2558, 0x00002077),
GNB_ENTRY_WR (0x12, 0x2558, 0x000020B7),
GNB_ENTRY_WR (0x12, 0x2558, 0x00002A3D),
GNB_ENTRY_WR (0x12, 0x2558, 0x00002010),
GNB_ENTRY_WR (0x12, 0x2558, 0x00002A20),
GNB_ENTRY_WR (0x12, 0x2544, 0x00040108),
GNB_ENTRY_WR (0x12, 0x287C, 0x0c000911),

4382
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
View File

File diff suppressed because it is too large Load Diff

2
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c
View File

@ -475,7 +475,7 @@ GNB_TABLE ROMDATA GnbMidInitTableKB [] = {
0x7 |
0x8 |
0xfff0,
( 5 << 0) |
( 4 << 0) |
( 0 << 3) |
( 0xF << 4)
),

6
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c
View File

@ -244,7 +244,7 @@ PciePhyIsolationKB (
);
PhyRxIsoDis = GnbBuildOptions.CfgPciePhyIsolationEnable ? 0 : 3;
ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE_ALLOC_ACTIVE, 0, Wrapper);
ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_PHY_NATIVE, 0, Wrapper);
if ((ActiveLaneBitmap & 0xF0) != 0) {
PhyRxIsoDis = 3;
}
@ -256,7 +256,7 @@ PciePhyIsolationKB (
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
Pcie
);
D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = 3;
D0F0xE4_WRAP_8013.Field.PhyRxIsoDis = PhyRxIsoDis;
PcieRegisterWrite (
Wrapper,
WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_8013_ADDRESS),
@ -264,7 +264,7 @@ PciePhyIsolationKB (
FALSE,
Pcie
);
IDS_HDT_CONSOLE (GNB_TRACE, " ActiveLaneBitmap = 0x%x, PhyRxIsoDis = %d\n", ActiveLaneBitmap, PhyRxIsoDis);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePhyIsolationKB Exit\n");
}

86
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c
View File

@ -110,21 +110,77 @@ PcieMidPortInitCallbackKB (
PciePortProgramRegisterTable (PortInitMidTableKB.Table, PortInitMidTableKB.Length, Engine, TRUE, Pcie);
if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) {
PcieEnableSlotPowerLimitV5 (Engine, Pcie);
// If StartLane == 4/7 and EndLane == 7/4, this is GFX port
if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) ||
((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) {
// Only count active Gpp ports
*(UINT8 *)Buffer += 1;
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Callback to init ASPM on all active ports
*
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in, out] Buffer PortCount
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
PcieMidAspmInitCallbackKB (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidAspmInitCallbackKB Enter\n");
IDS_HDT_CONSOLE (GNB_TRACE, " PortCount = %02x\n", *(UINT8 *)Buffer);
// If StartLane == 4/7 and EndLane == 7/4, this is GFX port
if (!(((Engine->EngineData.StartLane == 4) && (Engine->EngineData.EndLane == 7)) ||
((Engine->EngineData.StartLane == 7) && (Engine->EngineData.EndLane == 4)))) {
// For GPP ports only set STRAP_MED_yTSx_COUNT=2
PciePortRegisterRMW (
Engine,
0xC0,
0x30,
0x2 << 4,
TRUE,
Pcie
);
// For GPP ports only set STRAP_MED_yTSx_COUNT=2, but only if active ports is > 2
switch (*(UINT8 *)Buffer) {
case 0:
case 1:
break;
case 2:
PciePortRegisterRMW (
Engine,
DxFxxE4_xA0_ADDRESS,
DxFxxE4_xA0_Reserved_26_25_MASK |
DxFxxE4_xA0_Reserved_28_28_MASK,
(0 << DxFxxE4_xA0_Reserved_26_25_OFFSET) |
(1 << DxFxxE4_xA0_Reserved_28_28_OFFSET),
TRUE,
Pcie
);
break;
default:
PciePortRegisterRMW (
Engine,
0xC0,
0x30,
0x2 << 4,
TRUE,
Pcie
);
break;
}
}
PcieEnableAspm (Engine, Pcie);
IDS_HDT_CONSOLE (GNB_TRACE, "PcieMidAspmInitCallbackKB Exit\n");
}
/*----------------------------------------------------------------------------------------*/
@ -147,12 +203,22 @@ PcieMidPortInitKB (
{
AGESA_STATUS Status;
PCIE_LINK_SPEED_CAP GlobalSpeedCap;
UINT8 PortCount;
Status = AGESA_SUCCESS;
PortCount = 0;
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidPortInitCallbackKB,
NULL,
&PortCount,
Pcie
);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE,
PcieMidAspmInitCallbackKB,
&PortCount,
Pcie
);

4
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c
View File

@ -392,8 +392,8 @@ MemFDMISupport3 (
FormFactor = (UINT8) SpdDataStructure->Data[3];
if (((FormFactor & 0x0F) == 0x01) || ((FormFactor & 0x0F) == 0x02) || ((FormFactor & 0x0F) == 0x0B)) {
DmiPhysicalDimmInfoTable->FormFactor = 0x09; // RDIMM or UDIMM or LRDIMM
} else if ((FormFactor & 0x0F) == 0x03) {
DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM
} else if (((FormFactor & 0x0F) == 0x03) || ((FormFactor & 0x0F) == 0x08) || ((FormFactor & 0x0F) == 0x09) || ((FormFactor & 0x0F) == 0x0A)) {
DmiPhysicalDimmInfoTable->FormFactor = 0x0D; // SO-DIMM, SO-UDIMM, SO-RDIMM and SO-CDIMM
} else {
DmiPhysicalDimmInfoTable->FormFactor = 0x02; // UNKNOWN
}

9
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/mmMemRestore.c
View File

@ -59,6 +59,7 @@
#include "S3.h"
#include "mfs3.h"
#include "heapManager.h"
#include "cpuFeatures.h"
#include "cpuRegisters.h"
#include "cpuPostInit.h"
#include "cpuApicUtilities.h"
@ -491,6 +492,14 @@ MemMContextRestore (
MemFeatMain.MemClr (MemMainPtr);
}
}
// Set LockDramCfg, which must be done after Memory Clear
for (Node = 0; Node < MemMainPtr->DieCount; Node ++) {
if (IsFeatureEnabled (C6Cstate, MemMainPtr->MemPtr->PlatFormConfig, &(MemMainPtr->MemPtr->StdHeader))) {
IDS_SKIP_HOOK (IDS_LOCK_DRAM_CFG, &NBArray[Node], &MemMainPtr->MemPtr->StdHeader) {
NBArray[Node].SetBitField (&NBArray[Node], BFLockDramCfg, 1);
}
}
}
} else {
RefPtr->MemRestoreCtl = FALSE;
}

1
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnkb.c
View File

@ -451,6 +451,7 @@ MemNInitNBDataKB (
NBPtr->FamilySpecificHook[DisableMemHoleMapping] = MemNDisableMemHoleMappingKB;
NBPtr->FamilySpecificHook[RestoreMemHoleMapping] = MemNRestoreMemHoleMappingKB;
NBPtr->FamilySpecificHook[PhyInitVref] = MemNPhyInitVrefKB;
NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] = MemNIntermediateMemclkFreqValUnb;
IEM_INSERT_CODE (IEM_NBBLOCK_INIT, IemInitNBDataOverrideKB, (NBPtr));
}

8
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnphykb.c
View File

@ -938,6 +938,8 @@ MemNPhyPowerSavingMPstateKB (
UINT8 WrDqDqsEarly;
UINT8 i;
UINT8 j;
UINT16 MemClkSpeed;
MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
// 3. Program D18F2x9C_x0D0F_0[F,8:0]30_dct[0][PwrDn] to disable the ECC lane if
// D18F2x90_dct[0][DimmEccEn]==0.
@ -966,11 +968,11 @@ MemNPhyPowerSavingMPstateKB (
}
// 11. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
// (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
// 12. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
// If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
// else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
if (MemClkSpeed <= DDR1600_FREQUENCY) {
MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
} else {
@ -994,7 +996,7 @@ MemNPhyPowerSavingMPstateKB (
DllPower[i] = 0x8080;
}
// 13. If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
// Let MaxRxStggrDly = ((Tcl-1)*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 6.
MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
Tcl = (UINT8) MemNGetBitFieldNb (NBPtr, BFTcl);

106
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mns3kb.c
View File

@ -185,6 +185,14 @@ MemS3ResumeConstructNBBlockKB (
IN UINT8 NodeID
);
VOID
MemNS3SetMemClkFreqValKB (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR Address,
IN OUT VOID *Value,
IN OUT VOID *ConfigPtr
);
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
@ -201,7 +209,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncKB[] = {
{MemNS3SaveNBRegisterUnb, MemNS3RestoreNBRegisterUnb},
{MemNS3GetBitFieldNb, MemNS3SetPreDriverCalUnb},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetPhyStatusRegKB},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValUnb},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3SetMemClkFreqValKB},
{MemNS3ChangeMemPStateContextNb, MemNS3ChangeMemPStateContextNb},
{MemNS3GetBitFieldNb, MemNS3SetPhyFenceKB},
{ (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ReleaseNBPSUnb},
@ -218,8 +226,8 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
{{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703},
{{0, 0, 0}, FUNC_1, 0x44, 0xFFFF0707},
{{0, 0, 0}, FUNC_1, 0xF0, 0xFF00FF83},
{{0, 0, 0}, FUNC_1, 0x120, 0x00001FFF},
{{0, 0, 0}, FUNC_1, 0x124, 0x00001FFF},
{{0, 0, 0}, FUNC_1, 0x120, 0x001FFFFF},
{{0, 0, 0}, FUNC_1, 0x124, 0x001FFFFF},
{{0, 0, 0}, FUNC_1, 0x200, 0x00FFF87B},
{{0, 0, 0}, FUNC_1, 0x204, 0x00FFF800},
{{0, 0, 0}, FUNC_2, 0x114, 0x00000200},
@ -229,11 +237,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorKB[] = {
{{0, 0, 0}, FUNC_2, 0x1B0, 0xFFD3FF3F},
{{0, 0, 0}, FUNC_2, 0x1B4, 0xFC7FFFFF},
{{0, 0, 0}, FUNC_2, 0x1BC, 0xFFFFFFFF},
{{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900},
{{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1},
{{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF},
{{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0},
{{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF}
{{0, 0, 0}, FUNC_2, 0xA4, 0x00F07900}
};
CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefKB = {
@ -421,12 +425,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MASK, ANY_DIMM_MASK},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MASK, 0x04},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MASK, 0x10},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MASK, 0x40},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MASK, 0x04},
@ -437,12 +445,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MASK, 0x01},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MASK, 0x04},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MASK, 0x10},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MASK, 0x40},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MASK, 0x04},
@ -453,12 +465,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MASK, 0x04},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MASK, 0x10},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MASK, 0x40},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MASK, 0x04},
@ -493,12 +509,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 2, 1}, DCT0, BFRxDqInsDly, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x10), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x11), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x12), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x13), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x14), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x15), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x16), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x17), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x18), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x19), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 2, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x1B), 0x000003FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x20), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x21), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x23), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x04},
@ -509,12 +529,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x2A), 0x03FF03FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x01), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x02), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x03), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x101), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x102), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x103), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x201), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x202), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x203), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x301), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x302), 0xFFFFFFFF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x303), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x05), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x06), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x105), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x04},
@ -525,12 +549,16 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x306), 0x3E3E3E3E, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x30), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x31), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x32), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x33), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x34), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x35), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x04},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x36), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x37), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x38), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x10},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x39), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3A), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 1, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x3B), 0x000000FF, DCT0_MEMPSTATE_MASK, 0x40},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x40), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x41), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x01},
{{0, 0, 1}, FUNC_2, SET_S3_SPECIAL_OFFSET (DCT_PHY_FLAG, 0, 0x43), 0x00FF00FF, DCT0_MEMPSTATE_MASK, 0x04},
@ -562,6 +590,10 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{1, 1, 1}, DCT0, BFVrefSel, 0x00000007, DCT0_MASK, ANY_DIMM_MASK},
{{1, 2, 1}, DCT0, BFVrefDAC, 0x000001F8, DCT0_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_5, 0x240, 0xFFFFFFC1, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_5, 0x244, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_5, 0x248, 0xFFFFFFC0, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_5, 0x24C, 0x0000FFFF, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x1B4, 0x08000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_3, 0x180, 0x02000000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_3, 0x58, 0x0000001F, ANY_DIMM_MASK, ANY_DIMM_MASK},
@ -569,7 +601,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorKB[] = {
{{0, 0, 0}, FUNC_3, 0x44, 0x00400004, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x118, 0x00040000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK},
{{0, 0, 0}, FUNC_2, 0x118, 0x00080000, ANY_DIMM_MASK, ANY_DIMM_MASK, S3_RESUME_MODE},
{{13, 3, 1}, DO_NOT_CARE, 0, DO_NOT_CARE, ANY_DIMM_MASK, ANY_DIMM_MASK}
};
@ -1256,3 +1288,59 @@ MemNS3SetPhyFenceKB (
MemNSetBitFieldNb (NBPtr, BFFence2, Fence2Reg);
}
}
/* -----------------------------------------------------------------------------*/
/**
*
*
* This function sets MemClkFreqVal bit, adding an intermediate frequency hop
* to 333Mhz before changing to the target DDR rate. This sequence is
* intended to mimic the initial boot frequency ramp.
*
* @param[in] AccessWidth - Access width of the register.
* @param[in] Address - address in PCI_ADDR format.
* @param[in, out] *Value - Pointer to the value to be written.
* @param[in, out] *ConfigPtr - Pointer to Config handle.
* @return none
*/
VOID
MemNS3SetMemClkFreqValKB (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR Address,
IN OUT VOID *Value,
IN OUT VOID *ConfigPtr
)
{
UINT32 TempValue;
UINT32 TempMemClk;
// 1. Save the current MemClkFreq
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
TempMemClk = TempValue;
// 2. Program MemClkFreq = 200MHz, MemClkFreqVal = 1;
TempValue &= 0xFFFFFF00;
TempValue |= 0x82;
MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
// 3. Wait for FreqChgInPrg == 0
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
while ((TempValue & 0x200000) != 0) {
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
}
// 4. Program MemClkFreqVal = 0, Restore MemClkFreq
TempValue &= 0xFFFFFFEF;
MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempMemClk, ConfigPtr);
// 5. Program MemClkFreqVal = 1
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
TempValue |= 0x80;
MemNS3RestoreNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
// 6. Wait for FreqChgInPrg = 0
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
while ((TempValue & 0x200000) != 0) {
MemNS3SaveNBRegisterUnb (AccessWidth, Address, &TempValue, ConfigPtr);
}
}

1
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mndct.c
View File

@ -367,6 +367,7 @@ MemNStartupDCTUnb (
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
MemNSwitchDCTNb (NBPtr, Dct);
if ((NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
NBPtr->FamilySpecificHook[IntermediateMemclkFreqVal] (NBPtr, NULL);
MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
}

40
src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/mnphy.c
View File

@ -1152,6 +1152,8 @@ MemNPhyPowerSavingMPstateUnb (
UINT8 MaxTxStggrDly;
UINT8 Tcwl;
UINT8 i;
UINT16 MemClkSpeed;
MemClkSpeed = ( (NBPtr->MemPstate == MEMORY_PSTATE0) ? NBPtr->DCTPtr->Timings.Speed : MemNGetMemClkFreqUnb (NBPtr, (UINT8) MemNGetBitFieldNb (NBPtr, BFM1MemClkFreq)) );
IDS_HDT_CONSOLE (MEM_FLOW, "Start Phy power saving setting for memory Pstate %d\n", NBPtr->MemPstate);
// 4. Program D18F2x9C_x0D0F_0[F,8:0]13_dct[1:0][DllDisEarlyU] = 1b.
@ -1172,11 +1174,11 @@ MemNPhyPowerSavingMPstateUnb (
}
// 10. Program D18F2x9C_x0D0F_0[F,7:0][50,10]_dct[1:0][EnRxPadStandby] = IF
// (D18F2x94_dct[1:0][MemClkFreq] <= 800 MHz) THEN 1 ELSE 0 ENDIF.
MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
MemNSetBitFieldNb (NBPtr, BFEnRxPadStandby, (MemClkSpeed <= DDR1600_FREQUENCY) ? 0x1000 : 0);
// 11. Program D18F2x9C_x0000_000D_dct[1:0]_mp[1:0] as follows:
// If (DDR rate < = 1600) TxMaxDurDllNoLock = RxMaxDurDllNoLock = 8h
// else TxMaxDurDllNoLock = RxMaxDurDllNoLock = 7h.
if (NBPtr->DCTPtr->Timings.Speed <= DDR1600_FREQUENCY) {
if (MemClkSpeed <= DDR1600_FREQUENCY) {
MemNSetBitFieldNb (NBPtr, BFTxMaxDurDllNoLock, 8);
MemNSetBitFieldNb (NBPtr, BFRxMaxDurDllNoLock, 8);
} else {
@ -1199,7 +1201,7 @@ MemNPhyPowerSavingMPstateUnb (
DllPower[i] = 0x8080;
}
// If (DDR rate > = 1866) DllWakeTime = 1, Else DllWakeTime = 0.
DllWakeTime = (NBPtr->DCTPtr->Timings.Speed >= DDR1866_FREQUENCY) ? 1 : 0;
DllWakeTime = (MemClkSpeed >= DDR1866_FREQUENCY) ? 1 : 0;
// Let MaxRxStggrDly = (Tcl*2) + MIN(DqsRcvEnGrossDelay for all byte lanes (see D18F2x9C_x0000_00[2A:10]_dct[1:0]_mp[1:0])) - 4.
MinRcvEnGrossDly = NBPtr->TechPtr->GetMinMaxGrossDly (NBPtr->TechPtr, AccessRcvEnDly, FALSE);
ASSERT ((NBPtr->DCTPtr->Timings.CasL * 2 + MinRcvEnGrossDly) >= 4);
@ -1343,3 +1345,35 @@ MemN2DRdDQSEyeRimSearchUnb (
{
return MemT2DRdDQSEyeRimSearch (NBPtr->TechPtr);
}
/*-----------------------------------------------------------------------------
*
*
* Hook for some families which need an intermediate Mem Clk Frequency Valid
* before changing to the initial startup training frequency.
*
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
* @param[in,out] *OptParam - Optional parameter
*
* @return TRUE - always
* ----------------------------------------------------------------------------
*/
BOOLEAN
MemNIntermediateMemclkFreqValUnb (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT VOID *OptParam
)
{
// 1. Program MemClkFreq = 200MHz
MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, DDR400_FREQUENCY));
// 2. MemClkFreqVal = 1;
MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 1);
// 3. Wait for FreqChgInPrg == 0
MemNPollBitFieldNb (NBPtr, BFFreqChgInProg, 0, PCI_ACCESS_TIMEOUT, FALSE);
// 4. Program MemClkFreqVal = 0
MemNSetBitFieldNb (NBPtr, BFMemClkFreqVal, 0);
// 5. Retore MemClkFreq to startup value.
MemNSetBitFieldNb (NBPtr, BFMemClkFreq, MemNGetMemClkFreqIdUnb (NBPtr, NBPtr->DCTPtr->Timings.Speed));
return TRUE;
}

77
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/FT3/mpSkbft3.c
View File

@ -66,7 +66,6 @@ RDATA_GROUP (G2_PEI)
*----------------------------------------------------------------------------
*/
#define SOCKET_FT3_KB 0
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
@ -84,12 +83,80 @@ RDATA_GROUP (G2_PEI)
*
*-----------------------------------------------------------------------------
*/
// Slow mode, POdtOff, Address timing and Output drive compensation for FT3
// Format :
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff
//
STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAOFT3[] = {
{_1DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0},
{_1DIMM, DDR1066, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_1DIMM, DDR1066, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0},
{_1DIMM, DDR1333, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_1DIMM, DDR1333, V1_5 + V1_35, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR667 + DDR800, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
{_2DIMM, DDR667, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
{_2DIMM, DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
{_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_2DIMM, DDR1066, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
{_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_2DIMM, DDR1333, V1_5 + V1_35, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntU3FT3 = {
{PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBUDdr3SAOFT3) / sizeof (PSCFG_SAO_ENTRY),
(VOID *)&KBUDdr3SAOFT3
};
// Dram Term and Dynamic Dram Term for FT3
// Format :
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
//
// RttNom:
// 0 On die termination disabled
// 1 60ohms
// 2 120ohms
// 3 40ohms
// 4 20ohms
// 5 30ohms
// RttWr:
// 0 Dynamic termination for writes disabled.
// 1 60ohms
// 2 120ohms
STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMMFT3[] = {
{_1DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_1DIMM, DDR1333 + DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR667 + DDR800 + DDR1066, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_2DIMM, DDR667 + DDR800, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
{_2DIMM, DDR1066 + DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1333 + DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
{_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntUFT3 = {
{PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (DramTermKBUDIMMFT3) / sizeof (PSCFG_RTT_ENTRY),
(VOID *)&DramTermKBUDIMMFT3
};
//
// MemClkDis
//
STATIC CONST UINT8 ROMDATA KBSODdr3CLKDisFT3[] = {0xFF, 0xFF, 0x00 , 0x00, 0x00, 0x00, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = {
{PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
{PSCFG_CLKDIS, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3CLKDisFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3CLKDisFT3
};
@ -99,7 +166,7 @@ CONST PSC_TBL_ENTRY KBClkDisMapEntSOFT3 = {
//
STATIC CONST UINT8 ROMDATA KBSODdr3ODTTriFT3[] = {0xFF, 0xFF, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = {
{PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
{PSCFG_ODTTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3ODTTriFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3ODTTriFT3
};
@ -109,7 +176,7 @@ CONST PSC_TBL_ENTRY KBSODdr3ODTTriEntFT3 = {
//
STATIC CONST UINT8 ROMDATA KBSODdr3CSTriFT3[] = {0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
CONST PSC_TBL_ENTRY KBSODdr3CSTriEntFT3 = {
{PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
{PSCFG_CSTRI, SODIMM_TYPE + UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBSODdr3CSTriFT3) / sizeof (UINT8),
(VOID *)&KBSODdr3CSTriFT3
};
@ -124,7 +191,7 @@ STATIC CONST PSCFG_S2D_ENTRY KBUDdr3S2DFT3[] = {
{2, ANY_SPEED, VOLT_ALL, NP + DIMM_SR + DIMM_DR, NP + DIMM_SR + DIMM_DR, NP, 1}
};
CONST PSC_TBL_ENTRY S2DTblEntUFT3 = {
{PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, SOCKET_FT3_KB, DDR3_TECHNOLOGY},
{PSCFG_S2D, UDIMM_TYPE + SODIMM_TYPE + SODWN_SODIMM_TYPE, NOD_DONT_CARE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, KB_SOCKET_FT3, DDR3_TECHNOLOGY},
sizeof (KBUDdr3S2DFT3) / sizeof (PSCFG_S2D_ENTRY),
(VOID *)&KBUDdr3S2DFT3
};

30
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpSkb3.c
View File

@ -95,24 +95,18 @@ STATIC CONST PSCFG_SAO_ENTRY KBSODdr3SAO[] = {
{_1DIMM, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_1DIMM, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR667 + DDR800, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
{_2DIMM, DDR667, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
{_2DIMM, DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
{_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_2DIMM, DDR1066, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
{_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
{_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntSO3 = {
{PSCFG_SAO, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -155,8 +149,6 @@ STATIC CONST PSCFG_SAO_ENTRY KBSoDwnDdr3SAO[] = {
{_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20110000, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0},
{_DIMM_NONE, DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30110000, 0},
{_DIMM_NONE, DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30110000, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntSoDwn3 = {
{PSCFG_SAO, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -186,14 +178,11 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSODIMM3[] = {
{_1DIMM, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR667 + DDR800 + DDR1066, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_2DIMM, DDR667 + DDR800, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
{_2DIMM, DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1066 + DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1333, VOLT_ALL, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR1333, V1_5 + V1_35, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1333, V1_25, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1600, V1_5 + V1_35, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
{_2DIMM, DDR1600, V1_35, DIMM_SR, DIMM_SR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
{_2DIMM, DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntSO3 = {
{PSCFG_RTT, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -250,7 +239,6 @@ STATIC CONST PSCFG_RTT_ENTRY KBDramTermSoDwn3[] = {
{_DIMM_NONE, DDR800 + DDR1066, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_DIMM_NONE, DDR1333, VOLT_ALL, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_DIMM_NONE, DDR1600, V1_5 + V1_35, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_DIMM_NONE, DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntSoDwn3 = {
{PSCFG_RTT, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -267,9 +255,9 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSODIMM6L[] = {
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1333_FREQUENCY, DDR1333_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSO6L = {
{PSCFG_MAXFREQ, SODIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -304,8 +292,8 @@ STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwnPlusSODIMM6L[] = {
{{_1DIMM, 1, 1, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 2, 0, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 1, 1, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 0, 2, 0, DDR1066_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
{{_1DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1066_FREQUENCY, DDR1066_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM6L = {
{PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _1DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -335,8 +323,8 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwnPlusSODIMM4L = {
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA KBMaxFreqSoDwn[] = {
{{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}},
{{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1066_FREQUENCY}},
{{_DIMM_NONE, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
{{_DIMM_NONE, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, DDR1333_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntSoDwn = {
{PSCFG_MAXFREQ, SODWN_SODIMM_TYPE, _DIMM_NONE, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},

106
src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c
View File

@ -82,77 +82,18 @@ RDATA_GROUP (G2_PEI)
*
*-----------------------------------------------------------------------------
*/
// Slow mode, POdtOff, Address timing and Output drive compensation
// Format :
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, SlowMode, AddTmgCtl, ODC, POdtOff
//
STATIC CONST PSCFG_SAO_ENTRY KBUDdr3SAO[] = {
{_1DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, NP, NP, 0, 0x00000000, 0x00002222, 0},
{_1DIMM, DDR1066, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_1DIMM, DDR1066, V1_5, DIMM_DR, NP, NP, 0, 0x00000000, 0x10002222, 0},
{_1DIMM, DDR1333, V1_5, DIMM_SR, NP, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_1DIMM, DDR1333, V1_5, DIMM_DR, NP, NP, 0, 0x00003D3D, 0x20112222, 0},
{_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_SR, NP, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_1DIMM, DDR1600 + DDR1866, V1_5, DIMM_DR, NP, NP, 1, 0x00003C3C, 0x30332222, 0},
{_2DIMM, DDR667 + DDR800, V1_5, NP, DIMM_SR + DIMM_DR, NP, 0, 0x00000000, 0x00002222, 0},
{_2DIMM, DDR667, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x10222323, 0},
{_2DIMM, DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x20222323, 0},
{_2DIMM, DDR1066, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x10002222, 0},
{_2DIMM, DDR1066, V1_5, NP, DIMM_DR, NP, 0, 0x00000000, 0x10002222, 0},
{_2DIMM, DDR1066 + DDR1333 + DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, 1, 0x00000000, 0x30222323, 0},
{_2DIMM, DDR1333, V1_5, NP, DIMM_SR, NP, 0, 0x003D3D3D, 0x20112222, 0},
{_2DIMM, DDR1333, V1_5, NP, DIMM_DR, NP, 0, 0x00003D3D, 0x20112222, 0},
{_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_SR, NP, 0, 0x003C3C3C, 0x30332222, 0},
{_2DIMM, DDR1600 + DDR1866, V1_5, NP, DIMM_DR, NP, 1, 0x00003C3C, 0x30332222, 0},
};
CONST PSC_TBL_ENTRY KBSAOTblEntU3 = {
{PSCFG_SAO, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
sizeof (KBUDdr3SAO) / sizeof (PSCFG_SAO_ENTRY),
(VOID *)&KBUDdr3SAO
};
// Dram Term and Dynamic Dram Term
// Format :
// DimmPerCh, DDRrate, VDDIO, Dimm0, Dimm1, Dimm2, Dimm, Rank, RttNom, RttWr
//
// RttNom:
// 0 On die termination disabled
// 1 60ohms
// 2 120ohms
// 3 40ohms
// 4 20ohms
// 5 30ohms
// RttWr:
// 0 Dynamic termination for writes disabled.
// 1 60ohms
// 2 120ohms
STATIC CONST PSCFG_RTT_ENTRY DramTermKBUDIMM[] = {
{_1DIMM, DDR667 + DDR800 + DDR1066, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_1DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, DIMM_SR + DIMM_DR, NP, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR667 + DDR800 + DDR1066, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 2, 0},
{_2DIMM, DDR667 + DDR800, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 3, 2},
{_2DIMM, DDR1066 + DDR1333, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 5, 2},
{_2DIMM, DDR1333 + DDR1600 + DDR1866, V1_5, NP, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 1, 0},
{_2DIMM, DDR1600, V1_5, DIMM_SR + DIMM_DR, DIMM_SR + DIMM_DR, NP, DIMM_SR + DIMM_DR, R0 + R1, 4, 1},
};
CONST PSC_TBL_ENTRY KBDramTermTblEntU = {
{PSCFG_RTT, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
sizeof (DramTermKBUDIMM) / sizeof (PSCFG_RTT_ENTRY),
(VOID *)&DramTermKBUDIMM
};
// Max Freq. for UDIMM <6-layer Motherboard Design> configuration
// Format :
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM6L[] = {
{{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
@ -160,18 +101,37 @@ CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = {
(VOID *)&MaxFreqKBUDIMM6L
};
// Max Freq. for UDIMM <6-layer Motherboard Design> configuration for microserver
// Format :
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBMicroSrvUDIMM6L[] = {
{{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},
sizeof (MaxFreqKBMicroSrvUDIMM6L) / sizeof (PSCFG_MAXFREQ_ENTRY),
(VOID *)&MaxFreqKBMicroSrvUDIMM6L
};
// Max Freq. for UDIMM <4-layer Motherboard Design> configuration
// Format :
// DimmPerCh, Dimms, SR, DR, QR, Speed1_5V, Speed1_35V, Speed1_25V
//
STATIC CONST PSCFG_MAXFREQ_ENTRY ROMDATA MaxFreqKBUDIMM4L[] = {
{{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_1DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
{{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}},
};
CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = {
{PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY},

19
src/vendorcode/amd/agesa/f16kb/Proc/Mem/mn.h
View File

@ -364,6 +364,8 @@ typedef struct _MEM_PS_BLOCK {
UINT8 NumOfDimmSlots; ///< See enum type NOD_SUPPORTED
UINT8 DimmType; ///< See enum type DIMM_TYPE
UINT16 RankType; ///< Rank type of all populated DIMMs. See MemPGetPsRankType.
UINT8 MotherboardLayer; ///< See enum type MB_LAYER_TYPE
UINT8 MotherboardPower; ///< See enum type MB_POWER_TYPE
} MEM_PS_BLOCK;
/// Structure parameters needed in frequency change of client NB.
@ -445,7 +447,8 @@ typedef enum {
AMPIsEnabled, ///< Check to detemine if AMP is exactly enabled.
ScrubberEn, ///< Check to determine if DRAM scrubber is already enabled
SwitchRdDqsDlyForMaxRdLatency, ///< Use the different RdDqsDly value for MaxRdLatency calculation before/after DQS training
SelectMotherboardLayer, ///< Check to determine if multiple motherboard layer design applies
SelectMotherboardPower, ///< Check to determine if multiple motherboard power design applies
EnumSize ///< Size of list
} NB_SUPPORTED;
@ -548,6 +551,7 @@ typedef enum {
DisableMemHoleMapping, ///< Disable Memory Hole Settings
RestoreMemHoleMapping, ///< Enable Memory Hole Settings
PhyInitVref, ///< Program VrefSel during phy init
IntermediateMemclkFreqVal, ///< Workaround for some families needing intermediate frequency valid
NumberOfHooks ///< Size of list
} FAMILY_SPECIFIC_FUNC_INDEX;
@ -629,6 +633,7 @@ typedef struct _MEM_NB_BLOCK {
BOOLEAN OrigDisAutoRefreshState; ///< Original state of Dis Auto Refresh
BOOLEAN Execute1dMaxRdLatTraining; ///< Indicates if 1D training should be executed
BOOLEAN Override2DTraining; ///< 2D training has been overriden
UINT8 PmuFirmwareImage; ///< PMU firmware image to be use.
MEM_DCT_CACHE DctCache[MAX_CHANNELS_PER_SOCKET]; ///< Allocate space for MCT_DCT_CACHE.
MEM_DCT_CACHE *DctCachePtr; ///< pointer to current Node's Node struct
@ -1575,5 +1580,17 @@ VOID
MemNSetEccExclusionRangeUnb (
IN OUT MEM_NB_BLOCK *NBPtr
);
UINT32
MemNGetNbClkFreqByPstateUnb (
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT32 NBPstate
);
BOOLEAN
MemNIntermediateMemclkFreqValUnb (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT VOID *OptParam
);
#endif /* _MN_H_ */

476
src/vendorcode/amd/agesa/f16kb/cpcarmac.inc
View File

@ -1,476 +0,0 @@
;*****************************************************************************
; AMD Generic Encapsulated Software Architecture
;
; Workfile: cpcarmac.inc $Revision:: 84150 $ $Date:: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
;
; Description: Code to setup and break down cache-as-stack
;
;*****************************************************************************
;
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
.XLIST
INCLUDE cpcar.inc
.LIST
.586P
.mmx
STACK_AT_TOP EQU 0 ; Stack is at the top of CAR
STACK_AT_BOTTOM EQU 1 ; Stack is at the bottom of CAR
;======================================================================
; AMD_ENABLE_STACK: Setup a stack
;
; In:
; EBX = Return address (preserved)
;
; Out:
; SS:ESP - Our new private stack location
;
; EAX = AGESA_STATUS
; EDX = Return status code if EAX contains a return code of higher
; severity than AGESA_SUCCESS
; ECX = Stack size in bytes
;
; Requirements:
; * This routine presently is limited to a max of 64 processor cores
; Preserved:
; ebx ebp
; Destroyed:
; eax, ecx, edx, edi, esi, ds, es, ss, esp
; mmx0, mmx1, mmx5
; Input Parameter:
; STACK_AT_TOP (default)
; Indicate stack is on the top of cache as RAM.
; STACK_AT_BOTTOM
; Indicate stack is at the bottom of cache as RAM.
;
; Description:
; Fixed MTRR address allocation to cores:
; The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
; There is a max of 1 BSP, 7 core0s and 56 other cores.
; Although each core has it's own cache storage, they share the address space. Each core must
; be assigned a private and unique address space for its stack. To support legacy systems,
; the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
; for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
;
; 80000h 40000h 00000h
; +----------+----------+----------+----------+----------+----------+----------+----------+
; 64K | | | | | | | | | 64K ea
; ea +----------+----------+----------+----------+----------+----------+----------+----------+
; | MTRR 0000_0250 MTRRfix64K_00000 |
; +----------+----------+----------+----------+----------+----------+----------+----------+
; | 3 | 2 | 1 | 0 | 0 | | | | <-node
; | 15..1 | 15..1 | 15..1 | 15..1 | 0 | | | | <-core
; +----------+----------+----------+----------+----------+----------+----------+----------+
;
; C0000h B0000h A0000h 90000h 80000h
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;16K | | | | | | | | | | | | | | | | |
; ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
; | > Dis|play B|uffer | < | | | | | | | | | | 3 | 2 | 1 | <-node
; | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| | | | | | 0 | 0 | 0 | <-core
; +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
;
; E0000h D0000h C0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;
; 100000h F0000h E0000h
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
; | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
;======================================================================
AMD_ENABLE_STACK MACRO StackPosition
local AmdEnableStackExit
; Note that SS:ESP will be default stack. Note that this stack
; routine will not be used after memory has been initialized. Because
; of its limited lifetime, it will not conflict with typical PCI devices.
movd mm0, ebx ; Put return address in a safe place
movd mm1, ebp ; Save some other user registers
; get node id and core id of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
; If we detected an unknown processor family or core combination, return AGESA_FATAL.
.if (esi & (1 SHL FLAG_UNKNOWN_FAMILY))
mov edx, CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.elseif (esi & (1 SHL FLAG_CORE_NOT_IDENTIFIED))
mov edx, CPU_EVENT_CORE_NOT_IDENTIFIED
mov eax, AGESA_FATAL
jmp AmdEnableStackExit
.endif
; determine if stack is already enabled. We are using the DefType MSR for this determination.
; It is =0 after reset; CAR setup sets it to enable the MTRRs
mov eax, cr0 ; Is cache enabled? (CD or NW bit set)
CR0_MASK TEXTEQU %((1 SHL CR0_CD) OR (1 SHL CR0_NW))
.if (!(eax & CR0_MASK))
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Are either of the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
MSR_MASK TEXTEQU %((1 SHL MTRR_DEF_TYPE_EN)+(1 SHL MTRR_DEF_TYPE_FIX_EN))
.if (eax & MSR_MASK)
bts esi, FLAG_STACK_REENTRY ; indicate stack has already been initialized
.endif
.endif
; Set node to map the first 16MB to node 0; 0000_0000 to 00FF_FFFF as DRAM
mov ebx, esi ; Get my Node/Core info
xor bl, bl
shl bh, 3 ; Isolate my node#, match alignment for PCI Dev#
mov eax, 8000C144h ; D18F1x44:DRAM Base/Limit; N is Base, N+4 is Limit
add ah, bh
mov ebx, eax ; Save PCI address for Base/Limit pair
mov dx, 0CF8h
out dx, eax
add dx, 4
xor eax, eax ; Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
out dx, eax ; DRAM Limit = node0, no interleave
mov eax, ebx
sub eax, 4 ; Now point to the Base register
mov dx, 0CF8h
out dx, eax
add dx, 4
mov eax, 00000003h ; Set the read and write enable bits
out dx, eax ; DRAM Base = 0x0000, R/W
AMD_ENABLE_STACK_FAMILY_HOOK
; Init CPU MSRs for our init routines
mov ecx, MTRR_SYS_CFG ; SYS_CFG
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Turn on modification enable bit
_WRMSR
mov eax, esi
bt eax, FLAG_STACK_REENTRY ; Is this a 2nd entry?
.if (!carry?) ; On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
bt eax, FLAG_IS_PRIMARY ; Is this core the primary in a compute unit?
.if (carry?) ; Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
; Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
; Clear all variable and Fixed MTRRs for non-shared cores
mov ecx, AMD_MTRR_VARIABLE_BASE0
xor eax, eax
xor edx, edx
.while (cl != 10h) ; Variable MTRRphysBase[n] and MTRRphysMask[n]
_WRMSR
inc cl
.endw
mov cx, AMD_MTRR_FIX64k_00000 ; MSR:0000_0250
_WRMSR
mov cx, AMD_MTRR_FIX16k_80000 ; MSR:0000_0258
_WRMSR
mov cx, AMD_MTRR_FIX16k_A0000 ; MSR:0000_0259
_WRMSR
mov cx, AMD_MTRR_FIX4k_C0000 ; Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
.while (cl != 70h)
_WRMSR
inc cl
.endw
; Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
; - not strictly needed since the FixedMTRRs take presedence.
mov eax, (16 * 1024 * 1024)
mov ecx, TOP_MEM ; MSR:C001_001A
_WRMSR
.endif ; End Is_Primary
.endif ; End Stack_ReEntry
; Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
xor eax, eax
xor edx, edx
mov ecx, IORR_BASE ; MSR:C001_0016 - 0019
.while (cl != 1Ah)
_WRMSR
inc cl
.endw
mov ecx, TOP_MEM2 ; MSR:C001_001D
_WRMSR
; setup MTTRs for stacks
; A speculative read can be generated by a speculative fetch mis-aligned in a code zone
; or due to a data zone being interpreted as code. When a speculative read occurs outside a
; controlled region (intentionally used by software), it could cause an unwanted cache eviction.
; To prevent speculative reads from causing an eviction, the unused cache ranges are set
; to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
; Note: some core stack regions will share an MTRR since the control granularity is much
; larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
; space covered by the MTRR when parseling out cache space for the various uses. In some cases
; this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
;
; Outcome of this block is that: (Note the MTRR map at the top of the file)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
; review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
;
mov eax, esi ; Load Flags, node, core
.if (al == 0) ; Is a core 0?
.if (ah == 0) ; Is Node 0? (BSP)
; Is BSP, assign a 64K stack; for F10/F12, foce to a 32K stack
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_64K / 1000h))
bt eax, FLAG_FORCE_32K_STACK
.if (carry?)
mov ebx, ((AMD_MTRR_FIX64k_00000 SHL 16) + (3 SHL 8) + (BSP_STACK_SIZE_32K / 1000h))
.endif
mov ebp, BSP_STACK_BASE_ADDR
.else ; node 1 to 7, core0
; Is a Core0 of secondary node, assign 16K stacks
mov bx, AMD_MTRR_FIX16k_80000
shl ebx, 16 ;
dec ah ; index from 0
mov bh, ah ; Node# is used as slot#
mov bl, (CORE0_STACK_SIZE / 1000h)
mov al, ah ; Base = (Node# * Size);
mul bl ;
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE0_STACK_BASE_ADDR
mov ebp, eax
.endif
.else ;core 1 thru core 15
; Is core 1-15 of any node, assign 4K stacks
mov al, 16 ; CoreIndex = ( (Node# * 16) ...
mul ah ;
mov bx, si ;
dec bl ; account for core 0 on P1, etc
add al, bl ; ... + Core#);
mov bx, AMD_MTRR_FIX64k_00000
shl ebx, 16 ;
mov bh, al ; Slot# = (CoreIndex / 16) + 4;
shr bh, 4 ;
add bh, 4 ;
mov bl, (CORE1_STACK_SIZE / 1000h)
mul bl ; Base = ( (CoreIndex * Size) ...
movzx eax, ax ;
shl eax, 12 ; Expand back to full byte count (* 4K)
add eax, CORE1_STACK_BASE_ADDR ; ... + Base_Addr);
mov ebp, eax
.endif
; Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
mov edi, WB_DRAM_TYPE ; Load Cache type in 1st slot
mov cl, bh ; ShiftCount = ((slot# ...
and cl, 03h ; ... % 4) ...
shl cl, 3 ; ... * 8);
shl edi, cl ; Cache type is now in correct position
ror ebx, 16 ; Get the MTRR address
movzx ecx, bx ;
rol ebx, 16 ; Put slot# & size back in BX
_RDMSR ; Read-modify-write the MSR
.if (bh < 4) ; Is value in lower or upper half of MSR?
or eax, edi ;
.else ;
or edx, edi ;
.endif ;
_WRMSR ;
; Enable MTRR defaults as UC type
mov ecx, AMD_MTRR_DEFTYPE ; MSR:0000_02FF
_RDMSR ; Read-modify-write the MSR
bts eax, MTRR_DEF_TYPE_EN ; MtrrDefTypeEn
bts eax, MTRR_DEF_TYPE_FIX_EN ; MtrrDefTypeFixEn
_WRMSR
; Close the modification window on the Fixed MTRRs
mov ecx, MTRR_SYS_CFG ; MSR:0C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_EN ; MtrrFixDramEn
bts eax, MTRR_VAR_DRAM_EN ; variable MTRR enable bit
btr eax, MTRR_FIX_DRAM_MOD_EN ; Turn off modification enable bit
_WRMSR
; Enable caching in CR0
mov eax, CR0 ; Enable WT/WB cache
btr eax, CR0_PG ; Make sure paging is disabled
btr eax, CR0_CD ; Clear CR0 NW and CD
btr eax, CR0_NW
mov CR0, eax
; Use the Stack Base & size to calculate SS and ESP values
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; ebp - start address of stack block
; ebx - [31:16] - MTRR MSR address
; - [15:8] - slot# in MTRR register
; - [7:0] - block size in #4K blocks
;
mov esp, ebp ; Initialize the stack pointer
mov edi, esp ; Copy the stack start to edi
movzx bx, bl
movzx ebx, bx ; Clear upper ebx, don't need MSR addr anymore
shl ebx, 12 ; Make size full byte count (* 4K)
IFNB <StackPosition>
IF (StackPosition EQ STACK_AT_BOTTOM)
shr ebx, 1 ; If stack is at the bottom of CAR, divide size by 2
ENDIF
ENDIF
add esp, ebx ; Set the Stack Pointer as full linear address
sub esp, 4
;
; review:
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - 32b start address of stack block
; ebx - size of stack block
; esp - 32b linear stack pointer
;
; Determine mode for SS base;
mov ecx, CR0 ; Check for 32-bit protect mode
bt ecx, CR0_PE ;
.if (!carry?) ; PE=0 means real mode
mov cx, cs ;
.if (cx >= 0D000h) ; If CS >= D000, it's a real mode segment. PM selector would be 08-> 1000
; alter SS:ESP for 16b Real Mode:
mov eax, edi ;
shr eax, 4 ; Create a Real Mode segment for ss, ds, es
mov ss, ax ;
mov ds, ax ;
mov es, ax ;
shl eax, 4 ;
sub edi, eax ; Adjust the clearing pointer for Seg:Offset mode
mov esp, ebx ; Make SP an offset from SS
sub esp, 4 ;
.endif ; endif
; else
; Default is to use Protected 32b Mode
.endif
IFNB <StackPosition>
IF (StackPosition EQ STACK_AT_BOTTOM)
shl ebx, 1 ; restore the size of CAR
ENDIF
ENDIF
;
; Clear The Stack
; Now that we have set the location and the MTRRs, initialize the cache by
; reading then writing to zero all of the stack area.
; review:
; ss - Stack base
; esp - stack pointer
; ebx - size of stack block
; esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
; edi - address of start of stack block
;
shr ebx, 2 ;
mov cx, bx ; set cx for size count of DWORDS
; Check our flags - Don't clear an existing stack
.if ( !(esi & (1 SHL FLAG_STACK_REENTRY)) )
cld
mov esi, edi
rep lods DWORD PTR [esi] ; Pre-load the range
xor eax, eax
mov cx, bx
mov esi, edi ; Preserve base for push on stack
rep stos DWORD PTR [edi] ; Clear the range
mov DWORD PTR [esp], 0ABCDDCBAh ; Put marker in top stack dword
shl ebx, 2 ; Put stack size and base
push ebx ; in top of stack
push esi
mov ecx, ebx ; Return size of stack in bytes
mov eax, AGESA_SUCCESS ; eax = AGESA_SUCCESS : no error return code
.else
movzx ecx, cx
shl ecx, 2 ; Return size of stack, in bytes
mov edx, CPU_EVENT_STACK_REENTRY
mov eax, AGESA_WARNING ; eax = AGESA_WARNING (Stack has already been set up)
.endif
AmdEnableStackExit:
movd ebx, mm0 ; Restore return address
movd ebp, mm1
ENDM
;======================================================================
; AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
; should only be executed on the BSP
;
; In:
; none
;
; Out:
; EAX = AGESA_SUCCESS
;
; Preserved:
; ebx
; Destroyed:
; eax, ecx, edx, esp, mmx5
;======================================================================
AMD_DISABLE_STACK MACRO
mov esp, ebx ; Save return address
; get node/core/flags of current executing core
GET_NODE_ID_CORE_ID ; Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
; Turn on modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
bts eax, MTRR_FIX_DRAM_MOD_EN ; Enable modifications
_WRMSR
; Set lower 640K MTRRs for Write-Back memory caching
mov ecx, AMD_MTRR_FIX64k_00000
mov eax, 1E1E1E1Eh
mov edx, eax
_WRMSR ; 0 - 512K = WB Mem
mov ecx, AMD_MTRR_FIX16k_80000
_WRMSR ; 512K - 640K = WB Mem
; Turn off modification enable bit
mov ecx, MTRR_SYS_CFG ; MSR:C001_0010
_RDMSR
btr eax, MTRR_FIX_DRAM_MOD_EN ; Disable modification
_WRMSR
AMD_DISABLE_STACK_FAMILY_HOOK ; Re-Enable 'normal' cache operations
mov ebx, esp ; restore return address (ebx)
xor eax, eax
ENDM