Revert "mb/aopen/dxplplusu: Remove board"

This reverts commit eb76a455cd
and applies minor fixes to make it build again.

PARALLEL_MP was working prior to board removal and no
relevant SMI handlers were implemented. So NO_SMM choice
is now selected.

Change-Id: Ia1cd02278240d1b5d006fb2a7730d3d86390f85b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/e7505/Kconfig

@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config NORTHBRIDGE_INTEL_E7505
+	bool
+
+if NORTHBRIDGE_INTEL_E7505
+
+config NORTHBRIDGE_SPECIFIC_OPTIONS
+	def_bool y
+	select NO_ECAM_MMCONF_SUPPORT
+	select HAVE_DEBUG_RAM_SETUP
+	select NO_CBFS_MCACHE
+
+endif

src/northbridge/intel/e7505/Makefile.inc

@@ -0,0 +1,10 @@
+ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
+
+ramstage-y += northbridge.c
+ramstage-y += memmap.c
+
+romstage-y += romstage.c
+romstage-y += raminit.c
+romstage-y += memmap.c
+
+endif

src/northbridge/intel/e7505/e7505.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/*
+ * e7505.h: PCI configuration space for the Intel E7501 memory controller
+ */
+
+#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
+#define NORTHBRIDGE_INTEL_E7505_E7505_H
+
+/************  D0:F0 ************/
+// Register offsets
+#define SMRBASE		0x14	/* System Memory RCOMP Base Address Register, 32 bit? */
+#define MCHCFGNS	0x52	/* MCH (scrubber) configuration register, 16 bit */
+
+#define PAM_0		0x59
+
+#define DRB_ROW_0	0x60	/* DRAM Row Boundary register, 8 bit */
+#define DRB_ROW_1	0x61
+#define DRB_ROW_2	0x62
+#define DRB_ROW_3	0x63
+#define DRB_ROW_4	0x64
+#define DRB_ROW_5	0x65
+#define DRB_ROW_6	0x66
+#define DRB_ROW_7	0x67
+
+#define DRA		0x70	/* DRAM Row Attributes registers, 4 x 8 bit */
+#define DRT		0x78	/* DRAM Timing register, 32 bit */
+#define DRC		0x7C	/* DRAM Controller Mode register, 32 bit */
+#define DRDCTL		0x80	/* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
+#define CKDIS		0x8C	/* Clock disable register, 8 bit */
+#define SMRAMC		0x9D
+#define ESMRAMC		0x9E
+#define APSIZE		0xB4
+#define TOLM		0xC4	/* Top of Low Memory register, 16 bit */
+#define REMAPBASE	0xC6	/* Remap Base Address register, 16 bit */
+#define REMAPLIMIT	0xC8	/* Remap Limit Address register, 16 bit */
+#define SKPD		0xDE	/* Scratchpad register, 16 bit */
+#define DVNP		0xE0	/* Device Not Present, 16 bit */
+#define MCHTST		0xF4	/* MCH Test Register, 32 bit? (if similar to 855PM) */
+
+// CAS# Latency bits in the DRAM Timing (DRT) register
+#define DRT_CAS_2_5		(0<<4)
+#define DRT_CAS_2_0		(1<<4)
+#define DRT_CAS_MASK		(3<<4)
+
+// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
+#define RAM_COMMAND_NOP		(1<<4)
+#define RAM_COMMAND_PRECHARGE	(2<<4)
+#define RAM_COMMAND_MRS		(3<<4)
+#define RAM_COMMAND_EMRS	(4<<4)
+#define RAM_COMMAND_CBR		(6<<4)
+#define RAM_COMMAND_NORMAL	(7<<4)
+
+#define DRC_DONE		(1 << 29)
+
+// RCOMP Memory Map offsets
+// Conjecture based on apparent similarity between E7501 and 855PM
+// Intel doc. 252613-003 describes these for 855PM
+
+#define SMRCTL		0x20	/* System Memory RCOMP Control Register? */
+#define DQCMDSTR	0x30	/* Strength control for DQ and CMD signal groups? */
+#define CKESTR		0x31	/* Strength control for CKE signal group? */
+#define CSBSTR		0x32	/* Strength control for CS# signal group? */
+#define CKSTR		0x33	/* Strength control for CK signal group? */
+#define RCVENSTR	0x34	/* Strength control for RCVEnOut# signal group? */
+
+/************  D0:F1 ************/
+// Register offsets
+#define FERR_GLOBAL	0x40	/* First global error register, 32 bits */
+#define NERR_GLOBAL	0x44	/* Next global error register, 32 bits */
+#define DRAM_FERR	0x80	/* DRAM first error register, 8 bits */
+#define DRAM_NERR	0x82	/* DRAM next error register, 8 bits */
+
+/************  D1:F0 ************/
+
+#define APSIZE1		0x74
+
+#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */

src/northbridge/intel/e7505/memmap.c

@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <device/pci_ops.h>
+#include <arch/romstage.h>
+#include <cbmem.h>
+#include <cpu/x86/mtrr.h>
+#include <program_loading.h>
+#include "e7505.h"
+
+void *cbmem_top_chipset(void)
+{
+	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
+	uintptr_t tolm;
+
+	/* This is at 128 MiB boundary. */
+	tolm = pci_read_config16(mch, TOLM) >> 11;
+	tolm <<= 27;
+
+	return (void *)tolm;
+}
+
+void northbridge_write_smram(u8 smram);
+
+void northbridge_write_smram(u8 smram)
+{
+	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
+	pci_write_config8(mch, SMRAMC, smram);
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+	uintptr_t top_of_ram;
+
+	/*
+	 * Choose to NOT set ROM as WP cacheable here.
+	 * Timestamps indicate the CPU this northbridge code is
+	 * connected to, performs better for memcpy() and un-lzma
+	 * operations when source is left as UC.
+	 */
+
+	pcf->skip_common_mtrr = 1;
+
+	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+
+	/* Cache CBMEM region as WB. */
+	top_of_ram = (uintptr_t)cbmem_top();
+	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
+		MTRR_TYPE_WRBACK);
+}

src/northbridge/intel/e7505/northbridge.c

@@ -0,0 +1,82 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <assert.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <cpu/cpu.h>
+
+#include "e7505.h"
+
+static void mch_domain_read_resources(struct device *dev)
+{
+	int idx;
+	unsigned long tolmk;
+	uint64_t tom, remapbase, remaplimit;
+	struct device *mc_dev;
+
+	pci_domain_read_resources(dev);
+
+	mc_dev = pcidev_on_root(0, 0);
+	if (!mc_dev)
+		die("Could not find MCH device\n");
+
+	tolmk = pci_read_config16(mc_dev, TOLM) >> 11;
+	tolmk <<= 17;
+
+	tom = pci_read_config8(mc_dev, DRB_ROW_7);
+	tom <<= 26;
+
+	/* Remapped region with a 64 MiB granularity in register
+	   definition. Limit is inclusive, so add one. */
+	remapbase = pci_read_config16(mc_dev, REMAPBASE) & 0x3ff;
+	remapbase <<= 26;
+
+	remaplimit = pci_read_config16(mc_dev, REMAPLIMIT) & 0x3ff;
+	remaplimit += 1;
+	remaplimit <<= 26;
+
+	/* Report the memory regions */
+	idx = 10;
+	ram_resource_kb(dev, idx++, 0, tolmk);
+	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+
+
+	ASSERT(tom == remapbase);
+	upper_ram_end(dev, idx++, remaplimit);
+}
+
+static void mch_domain_set_resources(struct device *dev)
+{
+	assign_resources(dev->link_list);
+}
+
+static struct device_operations pci_domain_ops = {
+	.read_resources   = mch_domain_read_resources,
+	.set_resources    = mch_domain_set_resources,
+	.scan_bus         = pci_domain_scan_bus,
+	.ops_pci          = &pci_dev_ops_pci,
+};
+
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = noop_read_resources,
+	.set_resources    = noop_set_resources,
+	.init             = mp_cpu_bus_init,
+};
+
+static void enable_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_e7505_ops = {
+	CHIP_NAME("Intel E7505 Northbridge")
+	.enable_dev = enable_dev,
+};

src/northbridge/intel/e7505/raminit.h

@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef RAMINIT_H
+#define RAMINIT_H
+
+#include <stdint.h>
+
+#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
+#define MAX_NUM_CHANNELS 2
+#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
+
+struct mem_controller {
+	pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
+
+	// SMBus addresses of DIMM slots for each channel,
+	// in order from closest to MCH to furthest away
+	// 0 == not present
+	uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
+	uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
+};
+
+void sdram_initialize(void);
+
+#endif /* RAMINIT_H */

src/northbridge/intel/e7505/romstage.c

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbmem.h>
+#include <arch/romstage.h>
+
+#include <southbridge/intel/i82801dx/i82801dx.h>
+#include <northbridge/intel/e7505/raminit.h>
+
+void mainboard_romstage_entry(void)
+{
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	i82801dx_early_init();
+
+	sdram_initialize();
+
+	cbmem_recovery(0);
+}