mb/google/trulo/var/orisa: Add overridetree
Add override devicetree based on schematic_20240607. BUG=b:333486830 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id3ceff41fdb8e4a57bd6dab6247b622a5d13587d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82714 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Amanda Huang
Eric Lai
@@ -1,6 +1,531 @@
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chip soc/intel/alderlake
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fw_config
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field THERMAL_SOLUTION 0 0
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device domain 0 on
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option THERMAL_SOLUTION_6W 0
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end
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option THERMAL_SOLUTION_15W 1
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end
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end
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chip soc/intel/alderlake
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register "sagv" = "SaGv_Enabled"
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# GPE configuration
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register "pmc_gpe0_dw1" = "GPP_B"
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# S0ix enable
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register "s0ix_enable" = "1"
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# DPTF enable
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register "dptf_enable" = "1"
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register "tcc_offset" = "10" # TCC of 90
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# Enable CNVi BT
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register "cnvi_bt_core" = "true"
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# eMMC HS400
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register "emmc_enable_hs400_mode" = "1"
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#eMMC DLL tuning parameters
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# EMMC Tx CMD Delay
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# Refer to EDS-Vol2-42.3.7.
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# [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
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# EMMC TX DATA Delay 1
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# Refer to EDS-Vol2-42.3.8.
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# [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
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# [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909"
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# EMMC TX DATA Delay 2
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# Refer to EDS-Vol2-42.3.9.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
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# [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828"
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# EMMC RX CMD/DATA Delay 1
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# Refer to EDS-Vol2-42.3.10.
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# [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
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# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
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# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
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# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
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# EMMC RX CMD/DATA Delay 2
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# Refer to EDS-Vol2-42.3.12.
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# [17:16] stands for Rx Clock before Output Buffer,
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# 00: Rx clock after output buffer,
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# 01: Rx clock before output buffer,
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# 10: Automatic selection based on working mode.
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# 11: Reserved
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# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
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# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
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register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1004E"
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# EMMC Rx Strobe Delay
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# Refer to EDS-Vol2-42.3.11.
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# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
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# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
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register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x01515"
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
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register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
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register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1
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register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
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# Bit 0 - C0 has no redriver, so enable SBU muxing in the SoC.
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# Bit 2 - C1 has a redriver which does SBU muxing.
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# Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1.
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register "tcss_aux_ori" = "0"
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# Configure external V1P05/Vnn/VnnSx Rails
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register "ext_fivr_settings" = "{
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.configure_ext_fivr = 1,
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.v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0,
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.vnn_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX,
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.v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL,
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.vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE,
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.v1p05_voltage_mv = 1050,
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.vnn_voltage_mv = 780,
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.vnn_sx_voltage_mv = 1050,
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.v1p05_icc_max_ma = 500,
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.vnn_icc_max_ma = 500,
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}"
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register "serial_io_i2c_mode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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register "serial_io_gspi_mode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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}"
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register "serial_io_uart_mode" = "{
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[PchSerialIoIndexUART0] = PchSerialIoPci,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# FIXME: To be enabled in future based on PNP impact data.
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# Disable Package C-state demotion for nissa baseboard.
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register "disable_package_c_state_demotion" = "1"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| I2C0 | TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| I2C1 | Trackpad |
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#| I2C5 | Touchscreen |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.i2c[0] = {
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.early_init = 1,
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.speed = I2C_SPEED_FAST_PLUS,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST_PLUS,
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.scl_lcnt = 55,
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.scl_hcnt = 30,
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.sda_hold = 7,
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}
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},
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.i2c[1] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 158,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.speed_config[0] = {
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.speed = I2C_SPEED_FAST,
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.scl_lcnt = 158,
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.scl_hcnt = 79,
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.sda_hold = 7,
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}
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},
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}"
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register "power_limits_config[ADL_N_041_6W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 25,
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.tdp_pl4 = 78,
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}"
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register "power_limits_config[ADL_N_081_15W_CORE]" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 35,
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.tdp_pl4 = 83,
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}"
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device domain 0 on
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device ref igpu on end
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device ref dtt on
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chip drivers/intel/dptf
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## sensor information
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register "options.tsr[0].desc" = ""DDR""
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register "options.tsr[1].desc" = ""charger""
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register "options.tsr[2].desc" = ""ambient""
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## Active Policy
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register "policies.active" = "{
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[0] = {
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.target = DPTF_CPU,
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.thresholds = {
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TEMP_PCT(70, 100),
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TEMP_PCT(60, 65),
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TEMP_PCT(42, 60),
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TEMP_PCT(39, 55),
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TEMP_PCT(38, 50),
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TEMP_PCT(35, 43),
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TEMP_PCT(31, 30),
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}
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {
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TEMP_PCT(60, 100),
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TEMP_PCT(55, 65),
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TEMP_PCT(52, 60),
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TEMP_PCT(50, 55),
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TEMP_PCT(48, 50),
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TEMP_PCT(45, 43),
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TEMP_PCT(41, 30),
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}
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}
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}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
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[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
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}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
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}"
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register "controls.power_limits" = "{
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.pl1 = {
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.min_power = 6000,
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.max_power = 20000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 28 * MSECS_PER_SEC,
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.granularity = 500
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},
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.pl2 = {
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.min_power = 25000,
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.max_power = 25000,
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.time_window_min = 32 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 500
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}
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}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }
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}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 100, 6000, 220, 2200, },
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[1] = { 92, 5500, 180, 1800, },
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[2] = { 85, 5000, 145, 1450, },
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[3] = { 70, 4400, 115, 1150, },
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[4] = { 56, 3900, 90, 900, },
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[5] = { 45, 3300, 55, 550, },
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[6] = { 38, 3000, 30, 300, },
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[7] = { 33, 2900, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }
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}"
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## Fan options
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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|
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device generic 0 on
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||||||
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probe THERMAL_SOLUTION THERMAL_SOLUTION_6W
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||||||
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end
|
||||||
|
end
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||||||
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chip drivers/intel/dptf
|
||||||
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## sensor information
|
||||||
|
register "options.tsr[0].desc" = ""DDR""
|
||||||
|
register "options.tsr[1].desc" = ""charger""
|
||||||
|
register "options.tsr[2].desc" = ""ambient""
|
||||||
|
|
||||||
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## Active Policy
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||||||
|
register "policies.active" = "{
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||||||
|
[0] = {
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||||||
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.target = DPTF_CPU,
|
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|
.thresholds = {
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||||||
|
TEMP_PCT(70, 100),
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|
TEMP_PCT(60, 65),
|
||||||
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TEMP_PCT(42, 58),
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||||||
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TEMP_PCT(39, 53),
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||||||
|
TEMP_PCT(38, 47),
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||||||
|
TEMP_PCT(35, 43),
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||||||
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TEMP_PCT(31, 30),
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}
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||||||
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},
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[1] = {
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.target = DPTF_TEMP_SENSOR_0,
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||||||
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.thresholds = {
|
||||||
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TEMP_PCT(60, 100),
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|
TEMP_PCT(55, 65),
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||||||
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TEMP_PCT(52, 58),
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||||||
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TEMP_PCT(50, 53),
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||||||
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TEMP_PCT(48, 47),
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||||||
|
TEMP_PCT(45, 43),
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||||||
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TEMP_PCT(41, 30),
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||||||
|
}
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||||||
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}
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||||||
|
}"
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||||||
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|
||||||
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## Passive Policy
|
||||||
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register "policies.passive" = "{
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||||||
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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||||||
|
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 5000),
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||||||
|
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 70, 5000),
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||||||
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 70, 5000),
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||||||
|
}"
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||||||
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||||||
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## Critical Policy
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||||||
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register "policies.critical" = "{
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||||||
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[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN),
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||||||
|
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN),
|
||||||
|
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN),
|
||||||
|
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN),
|
||||||
|
}"
|
||||||
|
|
||||||
|
register "controls.power_limits" = "{
|
||||||
|
.pl1 = {
|
||||||
|
.min_power = 15000,
|
||||||
|
.max_power = 20000,
|
||||||
|
.time_window_min = 28 * MSECS_PER_SEC,
|
||||||
|
.time_window_max = 28 * MSECS_PER_SEC,
|
||||||
|
.granularity = 500
|
||||||
|
},
|
||||||
|
.pl2 = {
|
||||||
|
.min_power = 35000,
|
||||||
|
.max_power = 35000,
|
||||||
|
.time_window_min = 32 * MSECS_PER_SEC,
|
||||||
|
.time_window_max = 32 * MSECS_PER_SEC,
|
||||||
|
.granularity = 500
|
||||||
|
}
|
||||||
|
}"
|
||||||
|
|
||||||
|
## Charger Performance Control (Control, mA)
|
||||||
|
register "controls.charger_perf" = "{
|
||||||
|
[0] = { 255, 1700 },
|
||||||
|
[1] = { 24, 1500 },
|
||||||
|
[2] = { 16, 1000 },
|
||||||
|
[3] = { 8, 500 }
|
||||||
|
}"
|
||||||
|
|
||||||
|
## Fan Performance Control (Percent, Speed, Noise, Power)
|
||||||
|
register "controls.fan_perf" = "{
|
||||||
|
[0] = { 100, 6000, 220, 2200, },
|
||||||
|
[1] = { 92, 5500, 180, 1800, },
|
||||||
|
[2] = { 85, 5000, 145, 1450, },
|
||||||
|
[3] = { 70, 4400, 115, 1150, },
|
||||||
|
[4] = { 56, 3900, 90, 900, },
|
||||||
|
[5] = { 45, 3300, 55, 550, },
|
||||||
|
[6] = { 38, 3000, 30, 300, },
|
||||||
|
[7] = { 33, 2900, 15, 150, },
|
||||||
|
[8] = { 10, 800, 10, 100, },
|
||||||
|
[9] = { 0, 0, 0, 50, }
|
||||||
|
}"
|
||||||
|
|
||||||
|
## Fan options
|
||||||
|
register "options.fan.fine_grained_control" = "1"
|
||||||
|
register "options.fan.step_size" = "2"
|
||||||
|
|
||||||
|
device generic 1 on
|
||||||
|
probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref tcss_xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
device ref tcss_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-C Port C0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||||
|
device ref tcss_usb3_port1 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref xhci on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
device ref xhci_root_hub on
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-C Port C0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
|
||||||
|
device ref usb2_port5 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port A0 (DB)""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||||
|
device ref usb2_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Type-A Port A1 (DB)""
|
||||||
|
register "type" = "UPC_TYPE_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||||
|
device ref usb2_port2 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Camera""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
device ref usb2_port3 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
register "reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
|
||||||
|
device ref usb2_port6 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB2 Bluetooth""
|
||||||
|
register "type" = "UPC_TYPE_INTERNAL"
|
||||||
|
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)"
|
||||||
|
device ref usb2_port10 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port A0 (MLB)""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
|
||||||
|
device ref usb3_port1 on end
|
||||||
|
end
|
||||||
|
chip drivers/usb/acpi
|
||||||
|
register "desc" = ""USB3 Type-A Port A1 (DB)""
|
||||||
|
register "type" = "UPC_TYPE_USB3_A"
|
||||||
|
register "use_custom_pld" = "true"
|
||||||
|
register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
|
||||||
|
device ref usb3_port2 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref shared_sram on end
|
||||||
|
device ref cnvi_wifi on
|
||||||
|
chip drivers/wifi/generic
|
||||||
|
register "wake" = "GPE0_PME_B0"
|
||||||
|
register "enable_cnvi_ddr_rfim" = "true"
|
||||||
|
register "add_acpi_dma_property" = "true"
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref i2c0 on
|
||||||
|
chip drivers/i2c/tpm
|
||||||
|
register "hid" = ""GOOG0005""
|
||||||
|
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A17_IRQ)"
|
||||||
|
device i2c 50 on end
|
||||||
|
end
|
||||||
|
end #I2C0
|
||||||
|
device ref i2c1 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0000""
|
||||||
|
register "desc" = ""ELAN Touchpad""
|
||||||
|
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_B3_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW1_03"
|
||||||
|
register "detect" = "1"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
end #I2C1
|
||||||
|
device ref i2c5 on
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""ELAN9004""
|
||||||
|
register "generic.desc" = ""ELAN Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)"
|
||||||
|
register "generic.detect" = "1"
|
||||||
|
register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "generic.reset_delay_ms" = "20"
|
||||||
|
register "generic.reset_off_delay_ms" = "2"
|
||||||
|
register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E17)"
|
||||||
|
register "generic.enable_delay_ms" = "1"
|
||||||
|
register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
|
||||||
|
register "generic.stop_delay_ms" = "150"
|
||||||
|
register "generic.stop_off_delay_ms" = "2"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 10 on end
|
||||||
|
end
|
||||||
|
end #I2C5
|
||||||
|
device ref heci1 on end
|
||||||
|
device ref pcie_rp7 off end
|
||||||
|
device ref emmc on end
|
||||||
|
device ref ish on
|
||||||
|
chip drivers/intel/ish
|
||||||
|
register "add_acpi_dma_property" = "true"
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref ufs on end
|
||||||
|
device ref uart0 on end
|
||||||
|
device ref pch_espi on
|
||||||
|
chip ec/google/chromeec
|
||||||
|
use conn0 as mux_conn[0]
|
||||||
|
device pnp 0c09.0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
device ref pmc hidden
|
||||||
|
chip drivers/intel/pmc_mux
|
||||||
|
device generic 0 on
|
||||||
|
chip drivers/intel/pmc_mux/conn
|
||||||
|
use usb2_port5 as usb2_port
|
||||||
|
use tcss_usb3_port1 as usb3_port
|
||||||
|
device generic 0 alias conn0 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
Reference in New Issue
Block a user