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intel/spi: Switch to native PCI config accessors

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Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
2019-02-07 12:44:00 +02:00
parent 17387f67ad
commit 7ba14406c3
6 changed files with 22 additions and 191 deletions
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37
src/southbridge/intel/common/spi.c
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@ -24,6 +24,7 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <spi_flash.h>
@ -34,36 +35,6 @@
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
#ifdef __SMM__
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
*(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
*(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
pci_write_config32(dev, reg, val)
#else /* !__SMM__ */
#include <device/device.h>
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
*(targ) = pci_read_config16(dev, reg)
#define pci_read_config_dword(dev, reg, targ)\
*(targ) = pci_read_config32(dev, reg)
#define pci_write_config_byte(dev, reg, val)\
pci_write_config8(dev, reg, val)
#define pci_write_config_word(dev, reg, val)\
pci_write_config16(dev, reg, val)
#define pci_write_config_dword(dev, reg, val)\
pci_write_config32(dev, reg, val)
#endif /* !__SMM__ */
static int spi_is_multichip(void);
typedef struct spi_slave ich_spi_slave;
@ -308,7 +279,7 @@ void spi_init(void)
struct device *dev = pcidev_on_root(31, 0);
#endif
pci_read_config_dword(dev, 0xf0, &rcba);
rcba = pci_read_config32(dev, 0xf0);
/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
rcrb = (uint8_t *)(rcba & 0xffffc000);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
@ -356,10 +327,10 @@ void spi_init(void)
ich_set_bbar(0);
/* Disable the BIOS write protect so write commands are allowed. */
pci_read_config_byte(dev, 0xdc, &bios_cntl);
bios_cntl = pci_read_config8(dev, 0xdc);
/* Deassert SMM BIOS Write Protect Disable. */
bios_cntl &= ~(1 << 5);
pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
pci_write_config8(dev, 0xdc, bios_cntl | 0x1);
}
static void spi_init_cb(void *unused)