diff --git a/src/mainboard/system76/thelio-b1/devicetree.cb b/src/mainboard/system76/thelio-b1/devicetree.cb index 50d6aca6ff..9b4af67f6b 100644 --- a/src/mainboard/system76/thelio-b1/devicetree.cb +++ b/src/mainboard/system76/thelio-b1/devicetree.cb @@ -1,240 +1,240 @@ chip soc/intel/cannonlake - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" # ACPI (soc/intel/cannonlake/acpi.c) - # Enable s0ix - register "s0ix_enable" = "0" + # Enable s0ix + register "s0ix_enable" = "0" - # PM Timer Enabled - register "PmTimerDisabled" = "0" + # PM Timer Enabled + register "PmTimerDisabled" = "0" - # Disable DPTF - register "dptf_enable" = "0" + # Disable DPTF + register "dptf_enable" = "0" # CPU (soc/intel/cannonlake/cpu.c) - # Power limit - #register "tdp_pl1_override" = "15" - #register "tdp_pl2_override" = "25" + # Power limit + #register "tdp_pl1_override" = "15" + #register "tdp_pl2_override" = "25" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" # FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + #register "enable_c6dram" = "1" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # SATA - register "SataMode" = "Sata_AHCI" - register "SataSalpSupport" = "0" + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsEnable[3]" = "1" - register "SataPortsEnable[4]" = "1" - register "SataPortsEnable[5]" = "1" - register "SataPortsEnable[6]" = "0" - register "SataPortsEnable[7]" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "0" + register "SataPortsEnable[7]" = "0" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" - register "SataPortsDevSlp[2]" = "0" - register "SataPortsDevSlp[3]" = "0" - register "SataPortsDevSlp[4]" = "0" - register "SataPortsDevSlp[5]" = "0" - register "SataPortsDevSlp[6]" = "0" - register "SataPortsDevSlp[7]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataPortsDevSlp[3]" = "0" + register "SataPortsDevSlp[4]" = "0" + register "SataPortsDevSlp[5]" = "0" + register "SataPortsDevSlp[6]" = "0" + register "SataPortsDevSlp[7]" = "0" - # Audio - register "PchHdaDspEnable" = "0" - register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "1" - register "PchHdaAudioLinkDmic1" = "1" - register "PchHdaAudioLinkSsp0" = "0" - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkSsp2" = "0" - register "PchHdaAudioLinkSndw1" = "0" - register "PchHdaAudioLinkSndw2" = "0" - register "PchHdaAudioLinkSndw3" = "0" - register "PchHdaAudioLinkSndw4" = "0" + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" - # USB - register "SsicPortEnable" = "0" + # USB + register "SsicPortEnable" = "0" - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2 - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 - register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC - register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C + register "usb2_ports[3]" = "USB2_PORT_EMPTY" + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + register "usb2_ports[14]" = "USB2_PORT_EMPTY" + register "usb2_ports[15]" = "USB2_PORT_EMPTY" - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P3 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P4 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P5 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8 - register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC - register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P4 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P5 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8 + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" - # PCI Express Root port #5 x1, Clock 6 (I219-V) - register "PcieRpEnable[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieClkSrcUsage[6]" = "4" - register "PcieClkSrcClkReq[6]" = "6" + # PCI Express Root port #5 x1, Clock 6 (I219-V) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[6]" = "4" + register "PcieClkSrcClkReq[6]" = "6" - # PCI Express Root port #6 x1, Clock 7 (I211-AT) - register "PcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[7]" = "5" - register "PcieClkSrcClkReq[7]" = "7" + # PCI Express Root port #6 x1, Clock 7 (I211-AT) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[7]" = "5" + register "PcieClkSrcClkReq[7]" = "7" - # PCI Express Root port #9 x4, Clock 5 (M.2 P) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[5]" = "8" - register "PcieClkSrcClkReq[5]" = "5" + # PCI Express Root port #9 x4, Clock 5 (M.2 P) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[5]" = "8" + register "PcieClkSrcClkReq[5]" = "5" - # PCI Express Root port #21 x4, Clock 3 (M.2 Q) - register "PcieRpEnable[20]" = "1" - register "PcieRpLtrEnable[20]" = "1" - register "PcieClkSrcUsage[3]" = "20" - register "PcieClkSrcClkReq[3]" = "3" + # PCI Express Root port #21 x4, Clock 3 (M.2 Q) + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieClkSrcUsage[3]" = "20" + register "PcieClkSrcClkReq[3]" = "3" - # TODO: Clock 0 is used for PCIE X16 + # TODO: Clock 0 is used for PCIE X16 - # Misc - register "Device4Enable" = "1" - register "HeciEnabled" = "1" - register "AcousticNoiseMitigation" = "1" - #register "dmipwroptimize" = "1" - #register "satapwroptimize" = "1" + # Misc + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s - # Thermal - register "tcc_offset" = "12" + # Thermal + register "tcc_offset" = "12" - # Serial IRQ Continuous - register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Serial IRQ Continuous + register "serirq_mode" = "SERIRQ_CONTINUOUS" # LPC (soc/intel/cannonlake/lpc.c) - # LPC configuration from lspci -xxx - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x00040069" - register "gen3_dec" = "0x000c3321" - register "gen4_dec" = "0x00000000" + # LPC configuration from lspci -xxx + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x000c3321" + register "gen4_dec" = "0x00000000" - # 8254 - register "clock_gate_8254" = "0" + # 8254 + register "clock_gate_8254" = "0" # PMC (soc/intel/cannonlake/pmc.c) - # Enable deep Sx states - register "deep_s3_enable_ac" = "0" - register "deep_s3_enable_dc" = "0" - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - register "deep_sx_config" = "0" + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" # PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" # Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on + device lapic 0 on end + end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - #chip drivers/intel/wifi - # register "wake" = "PME_B0_EN_BIT" - device pci 14.3 on end # CNVi wifi - #end - device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on end # LPC Interface - device pci 1f.1 off end # P2SB - device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + #chip drivers/intel/wifi + # register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + #end + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end end