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mb/hp: Get rid of whitespace before tab

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Change-Id: I3f85e2ef0682b808f6e99dc406bccb88badcb82c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2018-05-28 13:32:07 +02:00
committed by Patrick Georgi
parent 808fc8ef87
commit 7bbcb4c424
8 changed files with 9 additions and 9 deletions
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2
src/mainboard/hp/8770w/devicetree.cb
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@@ -37,7 +37,7 @@ chip northbridge/intel/sandybridge
subsystemid 0x103c 0x176c subsystemid 0x103c 0x176c
end end
device pci 01.0 on # PCIe Bridge for discrete graphics device pci 01.0 on # PCIe Bridge for discrete graphics
device pci 00.0 on end # GPU device pci 00.0 on end # GPU
device pci 00.1 on end # HDMI Audio on GPU device pci 00.1 on end # HDMI Audio on GPU
end end
device pci 02.0 off # Internal graphics VGA controller device pci 02.0 off # Internal graphics VGA controller

2
src/mainboard/hp/abm/acpi/gpe.asl
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@@ -71,4 +71,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/hp/abm/dsdt.asl
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@@ -46,7 +46,7 @@ DefinitionBlock (
/* System Bus */ /* System Bus */
Scope(\_SB) { /* Start \_SB scope */ Scope(\_SB) { /* Start \_SB scope */
/* global utility methods expected within the \_SB scope */ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl> #include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

2
src/mainboard/hp/dl165_g6_fam10/devicetree.cb
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@@ -16,7 +16,7 @@ chip northbridge/amd/amdfam10/root_complex
end end
device pci 2.0 on device pci 2.0 on
end # unused end # unused
device pci 3.0 on # bridge to slot PCI-E 16x ?? device pci 3.0 on # bridge to slot PCI-E 16x ??
end end
device pci 4.0 on device pci 4.0 on
end # unused end # unused

2
src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl
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@@ -73,4 +73,4 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
} }
} /* End Scope GPE */ } /* End Scope GPE */

2
src/mainboard/hp/pavilion_m6_1035dx/acpi/sleep.asl
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@@ -44,7 +44,7 @@ Method(\_PTS, 1) {
/* On older chips, clear PciExpWakeDisEn */ /* On older chips, clear PciExpWakeDisEn */
/*if (LLessEqual(\_SB.SBRI, 0x13)) { /*if (LLessEqual(\_SB.SBRI, 0x13)) {
* Store(0,\_SB.PWDE) * Store(0,\_SB.PWDE)
*} *}
*/ */

4
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
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@@ -171,8 +171,8 @@
#if IS_ENABLED(CONFIG_GFXUMA) #if IS_ENABLED(CONFIG_GFXUMA)
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif #endif

2
src/mainboard/hp/pavilion_m6_1035dx/mainboard.h
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@@ -30,7 +30,7 @@
/* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but
* we make the distinction between GEVENT pin and SCI. * we make the distinction between GEVENT pin and SCI.
*/ */
#define EC_SCI_GPE EC_SCI_GEVENT #define EC_SCI_GPE EC_SCI_GEVENT
#define EC_LID_GPE EC_LID_GEVENT #define EC_LID_GPE EC_LID_GEVENT
#define PME_GPE 0x0b #define PME_GPE 0x0b
#define PCIE_GPE 0x18 #define PCIE_GPE 0x18