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vendorcode/{amd,cavium,intel}: Remove trailing whitespace

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find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \;

Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30959
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peter Lemenkov
2018-12-07 11:23:21 +01:00
committed by Patrick Georgi
parent d5292bf9a5
commit 7bbe3bb9f0
395 changed files with 9717 additions and 9717 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h
View File

@@ -218,7 +218,7 @@ EFI_STATUS
and defined for each FSP binary. This will be documented in Integration guide with
each FSP release.
After FspMemInit completes its execution, it passes the pointer to the HobList and
returns to the boot loader from where it was called. Bootloader is responsible to
returns to the boot loader from where it was called. Bootloader is responsible to
migrate it's stack and data to Memory.
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
complete the silicon initialization and provides bootloader an opportunity to get

6
src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h
View File

@@ -693,7 +693,7 @@ typedef struct {
UINT8 LanLtrEnable;
/** Offset 0x033D - SATA eSATASpeedLimit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable.
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable.
$EN_DIS
**/
UINT8 eSATASpeedLimit;
@@ -1030,7 +1030,7 @@ typedef struct {
} UPD_DATA_REGION;
#define FSP_IMAGE_ID 0x245053464C4B5324 /* '$SKLFSP$' */
#define FSP_IMAGE_REV 0x01090000
#define FSP_IMAGE_REV 0x01090000
/** VPD data structure
**/
@@ -1054,7 +1054,7 @@ typedef struct {
UINT8 UnusedVpdSpace0[32];
/** Offset 0x0030 - PcdSerialIoUartDebugEnable
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
**/
UINT8 PcdSerialIoUartDebugEnable;

10
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
View File

@@ -998,7 +998,7 @@ typedef struct {
/** Offset 0x020D - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
@@ -2133,18 +2133,18 @@ typedef struct {
/** Offset 0x04F7 - TcritMax
Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
has to be greater than THIGHMax .\n
Critical temperature will be TcritMax
Critical temperature will be TcritMax
**/
UINT8 TsodTcritMax;
/** Offset 0x04F8 - Event mode
/** Offset 0x04F8 - Event mode
Disable:Comparator mode.\n
Enable:Interrupt mode
$EN_DIS
**/
UINT8 TsodEventMode;
/** Offset 0x04F9 - EVENT polarity
/** Offset 0x04F9 - EVENT polarity
Disable:Active LOW.\n
Enable:Active HIGH
$EN_DIS
@@ -2609,7 +2609,7 @@ typedef struct {
/** Offset 0x059B - ChipsetInit HECI message
Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
If disabled, it prevents from sending ChipsetInit HECI message.
If disabled, it prevents from sending ChipsetInit HECI message.
$EN_DIS
**/
UINT8 ChipsetInitMessage;

14
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
View File

@@ -500,8 +500,8 @@ typedef struct {
**/
UINT8 PchCnviMfUart1Type;
/** Offset 0x014C - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
/** Offset 0x014C - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
$EN_DIS
**/
UINT8 PchEspiLgmrEnable;
@@ -836,7 +836,7 @@ typedef struct {
/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
Alpine ridge
Alpine ridge
**/
UINT8 PcieRootPortGen2PllL1CgDisable[24];
@@ -1611,7 +1611,7 @@ typedef struct {
Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
when debug is enabled. \n
Note: This BIOS option should keep 'Auto', other options are intended for advanced
Note: This BIOS option should keep 'Auto', other options are intended for advanced
configuration only.
0:Disabled, 1:Enabled, 2:Auto
**/
@@ -1622,7 +1622,7 @@ typedef struct {
keep PMC default settings. Or select the desired debug probe type for S0ix Override
settings.\n
Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
Note: This BIOS option should keep 'Auto', other options are intended for advanced
Note: This BIOS option should keep 'Auto', other options are intended for advanced
configuration only.
0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
**/
@@ -2218,7 +2218,7 @@ typedef struct {
/** Offset 0x0785 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
@@ -2310,7 +2310,7 @@ typedef struct {
**/
UINT32 Signature;
/** Offset 0x07B1 - Enable/Disable Device 7
/** Offset 0x07B1 - Enable/Disable Device 7
Enable: Device 7 enabled, Disable (Default): Device 7 disabled
$EN_DIS
**/

6
src/vendorcode/intel/fsp/fsp2_0/cannonlake/FsptUpd.h
View File

@@ -68,7 +68,7 @@ typedef struct {
typedef struct {
/** Offset 0x0040 - PcdSerialIoUartDebugEnable
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
**/
UINT8 PcdSerialIoUartDebugEnable;
@@ -96,12 +96,12 @@ typedef struct {
UINT32 PcdSerialIoUartInputClock;
/** Offset 0x0048 - Pci Express Base Address
Base address to be programmed for Pci Express
Base address to be programmed for Pci Express
**/
UINT64 PcdPciExpressBaseAddress;
/** Offset 0x0050 - Pci Express Region Length
Region Length to be programmed for Pci Express
Region Length to be programmed for Pci Express
**/
UINT32 PcdPciExpressRegionLength;