vendorcode/{amd,cavium,intel}: Remove trailing whitespace

find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \;

Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30959
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/agesa/common/Makefile.inc

@@ -10,8 +10,8 @@
 #     * Redistributions in binary form must reproduce the above copyright
 #       notice, this list of conditions and the following disclaimer in the
 #       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-#       its contributors may be used to endorse or promote products derived 
+#       its contributors may be used to endorse or promote products derived
 #       from this software without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -117,7 +117,7 @@
 
     Or (ShiftLeft (Arg0, 3), 0x1, Local0)
     procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
-    
+
     if (LAnd (Arg1, 1)) {
       while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
       	Store ("--Wait Ack--", Debug)

src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlib.esl

@@ -16,7 +16,7 @@
 *
 * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -139,7 +139,7 @@ DefinitionBlock (
         procSmuRcuWrite (0x8490, Local0)
       }
     }
-    Name (AD0A, 1)	
+    Name (AD0A, 1)
 #ifdef  ALTVDDNB_SUPPORT
     /*----------------------------------------------------------------------------------------*/
     /**

src/vendorcode/amd/agesa/f12/gcccar.inc

@@ -259,7 +259,7 @@ MSR_MASK    = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
     jnz     node_core_exit              # Br if yes
 
    mov     $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
-	
+
     mov     $APIC_BASE_ADDRESS, %ecx      # MSR:0000_001B
     _RDMSR
     bt      $APIC_BSC, %eax               # Is this the BSC?
@@ -978,7 +978,7 @@ fam15_enable_stack_hook_exit:
     btr     $DIS_HW_PF, %eax              # Turn on hardware prefetches
     #.endif                              # End workaround for erratum 498
     0:
-    _WRMSR	
+    _WRMSR
     #--------------------------------------------------------------------------
     # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
     #--------------------------------------------------------------------------

src/vendorcode/amd/agesa/f14/Makefile.inc

@@ -10,8 +10,8 @@
 #     * Redistributions in binary form must reproduce the above copyright
 #       notice, this list of conditions and the following disclaimer in the
 #       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-#       its contributors may be used to endorse or promote products derived 
+#       its contributors may be used to endorse or promote products derived
 #       from this software without specific prior written permission.
 #
 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND

src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibConfig.esl

@@ -16,7 +16,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */

src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl

@@ -16,7 +16,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
@@ -67,7 +67,7 @@
    *  PCIe port info
    *
    */
-   
+
   Name (
     AD07,
     Package () {
@@ -100,19 +100,19 @@
   Method (ALIB, 2, NotSerialized) {
     If (Lequal (Arg0, 0x1)) {
       return (procPsppReportAcDsState (Arg1))
-    } 
+    }
     If (LEqual (Arg0, 0x2)) {
       return (procPsppPerformanceRequest (Arg1))
-    } 
+    }
     If (LEqual (Arg0, 0x3)) {
       return (procPsppControl (Arg1))
-    } 
+    }
     If (LEqual (Arg0, 0x4)) {
       return (procPcieSetBusWidth (Arg1))
-    } 
+    }
     If (LEqual (Arg0, 0x5)) {
       return (procAlibInit ())
-    } 
+    }
     If (LEqual (Arg0, 0x6)) {
       return (procPciePortHotplug (Arg1))
     }
@@ -180,7 +180,7 @@
     procPciDwordWrite (Arg0, Arg1, Local0)
   }
 
-  Mutex(varPciePortAccessMutex, 0)    
+  Mutex(varPciePortAccessMutex, 0)
   /*----------------------------------------------------------------------------------------*/
   /**
    *  Read PCIe port indirect register
@@ -194,7 +194,7 @@
     Store (ShiftLeft (Add( Arg0, 2), 3), Local0)
     procPciDwordWrite (Local0, 0xe0, Arg1)
     Store (procPciDwordRead (Local0, 0xe4), Local0)
-    Release (varPciePortAccessMutex)  
+    Release (varPciePortAccessMutex)
     return (Local0)
   }
 
@@ -281,7 +281,7 @@
 
   /*----------------------------------------------------------------------------------------*/
   /**
-   *  
+   *
    *
    *  Arg0 	- Port ID
    *  Retval	- buffer that represent port data set
@@ -320,7 +320,7 @@
 
   /*----------------------------------------------------------------------------------------*/
   /**
-   *  
+   *
    *
    *  Arg0 	- Aspm
    *  Arg1 	- 0: Read, 1: Write
@@ -336,7 +336,7 @@
 	  IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve)
 	  {
 	  	Offset(0xE0),               // IO Base address of A-Link Express/ A-Link Bridge register
-	  	ABAR, 32, 
+	  	ABAR, 32,
 	  }
     OperationRegion (ACFG, SystemIO, ABAR, 0x8)
 	  Field (ACFG, DWordAcc, Nolock, Preserve) //AB_INDX/AB_DATA

src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibHotplug.esl

@@ -24,8 +24,8 @@
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived 
+*       its contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
@@ -446,7 +446,7 @@ Name (varLinkWidthBuffer, Buffer () {0, 1, 2, 4, 8, 12, 16})
     Store (Concatenate ("Lane Bitmap : ", ToHexString (varLaneBitmapOrMaskLocal3), varStringBuffer), Debug)
     if (Lequal (Arg3, 1)) {
       Store (0, varLaneBitmapOrMaskLocal3)
-    } 
+    }
     procIndirectRegisterRMW (0x0, 0xE0, Or (ShiftLeft (varWrapperId, 16), 0x8023), varLaneBitmapAndMaskLocal4, varLaneBitmapOrMaskLocal3);
     Stall (10)
     Store ("PcieLaneEnableControl Exit", Debug)

src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPspp.esl

@@ -24,8 +24,8 @@
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in the
 *       documentation and/or other materials provided with the distribution.
-*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-*       its contributors may be used to endorse or promote products derived 
+*       its contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND

src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSmuLib.esl

@@ -16,7 +16,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
@@ -118,7 +118,7 @@
 
     Or (ShiftLeft (Arg0, 3), 0x1, Local0)
     procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
-    
+
     if (LAnd (Arg1, 1)) {
       while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
       	Store ("--Wait Ack--", Debug)

src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl

@@ -16,7 +16,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -24,10 +24,10 @@
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived 
+ *       its contributors may be used to endorse or promote products derived
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
@@ -79,7 +79,7 @@ DefinitionBlock (
             //This is a battery <20><>idle<6C><65> state along with a <20><>perf<72><66> state that will be programmed to the max LCLK achievable at the Gen2 VID
             And (Local0, 0xFFFFFFA0, Local0)
             Or (Local0, 0xA0, Local0)
-          
+
         } else {
         	if (LEqual (Arg1, 0)) {
             //If AC, & if only Gen1 supported, activate state DPM0 and DPM1
@@ -104,7 +104,7 @@ DefinitionBlock (
      *
      *  Arg0 - Start Lane ID
      *  Arg1 - End Lane ID
-     *  Arg2 - Power ON(1) / OFF(0) 
+     *  Arg2 - Power ON(1) / OFF(0)
      */
     Method (procPcieLanePowerControl, 3, NotSerialized) {
        // stub function
@@ -115,7 +115,7 @@ DefinitionBlock (
      *  Adjust PLL settings stub
      *
      *  Arg0 	- 1 - GEN1 2 - GEN2
-     *  
+     *
      */
     Method (procPcieAdjustPll, 1, NotSerialized) {
       //stub function

src/vendorcode/cavium/bdk/libbdk-boot/bdk-boot-qlm.c

@@ -423,7 +423,7 @@ static void boot_init_qlm_mode(void)
             }
         }
     }
-   /* 
+   /*
     * Check if QLM autoconfig from DIP switch settings is requested
     */
     else if (bdk_config_get_int(BDK_CONFIG_QLM_DIP_AUTO_CONFIG))

src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-address.c

@@ -170,7 +170,7 @@ bdk_dram_address_construct_info(bdk_node_t node, int lmc, int dimm,
     if (lmcx_control.s.xor_bank)
         new_bank ^= EXTRACT(address, 12 + xbits, bank_width);
     INSERT(address, new_bank, bank_lsb, bank_width);
-      
+
     /* Determine the actual C bits from the input LMC controller arg */
     /* The input LMC number was probably aliased with other fields */
     BDK_CSR_INIT(l2c_ctl, node, BDK_L2C_CTL);

src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c

@@ -75,7 +75,7 @@ int bdk_dram_config(int node, int ddr_clock_override)
 }
 
 /**
- * Do all the DRAM Margin tests 
+ * Do all the DRAM Margin tests
  *
  * @param node   Node to test
  *

src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-size.c

@@ -136,7 +136,7 @@ int __bdk_dram_get_num_bank_bits(bdk_node_t node, int lmc)
     if (__bdk_dram_is_lmc_in_dreset(node, lmc)) // check LMCn
         return 0;
     BDK_CSR_INIT(lmcx_config, node, BDK_LMCX_CONFIG(lmc)); // sample LMCn
-    int bank_width = (__bdk_dram_is_ddr4(node, lmc) && (lmcx_config.s.bg2_enable)) ? 4 : 3; 
+    int bank_width = (__bdk_dram_is_ddr4(node, lmc) && (lmcx_config.s.bg2_enable)) ? 4 : 3;
     return bank_width;
 }
 

src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c

@@ -380,7 +380,7 @@ static int __bdk_dram_run_test(const dram_test_info_t *test_info, uint64_t start
         /* Wait for threads to finish, with progress */
         int cur_count;
         uint64_t cur_time;
-        uint64_t period = bdk_clock_get_rate(bdk_numa_local(), BDK_CLOCK_TIME) * TIMEOUT_SECS; // FIXME? 
+        uint64_t period = bdk_clock_get_rate(bdk_numa_local(), BDK_CLOCK_TIME) * TIMEOUT_SECS; // FIXME?
         uint64_t timeout = bdk_clock_get_count(BDK_CLOCK_TIME) + period;
         do {
             cur_count = bdk_atomic_get64(&dram_test_thread_done);
@@ -652,7 +652,7 @@ static void __bdk_dram_report_address_decode_new(uint64_t address, uint64_t orig
  * @param data    Data read from memory
  * @param correct Correct data
  * @param burst   Which burst this is from, informational only
- * @param fails   -1 for no retries done, >= 0 number of failures during retries 
+ * @param fails   -1 for no retries done, >= 0 number of failures during retries
  *
  * @return Zero if a message was logged, non-zero if the error limit has been reached
  */
@@ -691,7 +691,7 @@ void __bdk_dram_report_error(uint64_t address, uint64_t data, uint64_t correct,
  * @param address2 Second address involved in the failure
  * @param data2    Data from second address
  * @param burst    Which burst this is from, informational only
- * @param fails    -1 for no retries done, >= 0 number of failures during retries 
+ * @param fails    -1 for no retries done, >= 0 number of failures during retries
  *
  * @return Zero if a message was logged, non-zero if the error limit has been reached
  */

src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c

@@ -498,7 +498,7 @@ bdk_config_info_t config_info[] = {
         .min_value = 0,
         .max_value = 1,
     },
-    
+
     [BDK_CONFIG_QLM_MODE] = {
         .format = "QLM-MODE.N%d.QLM%d", /* Parameters: Node, QLM */
         .ctype = BDK_CONFIG_TYPE_STR,

src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-marvell.c

@@ -81,7 +81,7 @@ static void setup_marvell_phy(bdk_node_t node, int mdio_bus, int mdio_addr)
           phy_status = bdk_mdio_read(node, mdio_bus, mdio_addr, 22);
           if (phy_status < 0)
                        return;
-      
+
       phy_status = bdk_mdio_read(node, mdio_bus, mdio_addr, 17);
       if (phy_status < 0)
            return;
@@ -99,14 +99,14 @@ int bdk_if_phy_marvell_setup(bdk_node_t node, int qlm, int mdio_bus, int phy_add
     /* Check that the GSER mode is SGMII */
     /* Switch the marvell PHY to the correct mode */
     bdk_qlm_modes_t qlm_mode = bdk_qlm_get_mode(node, qlm);
-    
+
     BDK_TRACE(PHY,"%s: QLM:%d QLM_MODE:%d\n",__FUNCTION__, qlm, qlm_mode);
-    
+
     if ((qlm_mode != BDK_QLM_MODE_SGMII_1X1) &&
         (qlm_mode != BDK_QLM_MODE_SGMII_2X1))
         return 0;
 
-    BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__);    
+    BDK_TRACE(PHY,"%s: Detected Marvell Phy in SGMII mode\n", __FUNCTION__);
     for (int port = 0; port < 2; port++)
     {
         setup_marvell_phy(node, mdio_bus, phy_addr + port);

src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c

@@ -90,7 +90,7 @@ static void vitesse_init_script(bdk_node_t node, int mdio_bus, int phy_addr)
     uint16_t    reg_addr;
     uint16_t    reg_val;
     uint16_t    mask;
-    
+
     BDK_TRACE(PHY,"In %s\n",__FUNCTION__);
     BDK_TRACE(PHY,"Loading init script for VSC8514\n");
 
@@ -122,20 +122,20 @@ static void vitesse_program(bdk_node_t node, int mdio_bus, int phy_addr)
 
 /**
  * Setup Vitesse PHYs
- * This function sets up one port in a Vitesse VSC8514 
+ * This function sets up one port in a Vitesse VSC8514
  */
 static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr)
 {
     /*setting MAC if*/
     bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_GPIO_PAGE);
-    wr_masked(node,mdio_bus,phy_addr, 19, 0x4000, 0xc000); 
+    wr_masked(node,mdio_bus,phy_addr, 19, 0x4000, 0xc000);
     bdk_mdio_write(node, mdio_bus, phy_addr, 18, 0x80e0);
 
     /*Setting media if*/
     bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_STD_PAGE);
     // Reg23, 10:8 Select copper,  CAT5 copper only
     wr_masked(node,mdio_bus,phy_addr, 23, 0x0000, 0x0700);
-    
+
     // Reg0:15, soft Reset
     wr_masked(node,mdio_bus,phy_addr, 0, 0x8000, 0x8000);
     int time_out = 100;
@@ -159,9 +159,9 @@ static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr)
     bdk_mdio_write(node, mdio_bus, phy_addr, 16, 0x80);
     // Select main registers
     bdk_mdio_write(node, mdio_bus, phy_addr, 31, VSC_PHY_STD_PAGE);
-    
+
   /*
-  
+
     if (LOOP_INTERNAL)
     {
         reg0 = bdk_mdio_read(node, mdio_bus, phy_addr, 0);
@@ -176,7 +176,7 @@ static void setup_vitesse_phy(bdk_node_t node, int mdio_bus, int phy_addr)
         reg23 = bdk_insert(reg23, 1, 3, 1);
         bdk_mdio_write(node, mdio_bus, phy_addr, 23, reg23);
     }
-    
+
 
     // Dump registers
     if (false)

src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c

@@ -48,10 +48,10 @@ BDK_REQUIRE_DEFINE(XFI);
 
 /*
 Rate Select Settings
-Mode State			: 6/8 
+Mode State			: 6/8
-Rate Select State	: 0 
+Rate Select State	: 0
-RSEL1				: 0 
+RSEL1				: 0
-RSEL0				: 0 
+RSEL0				: 0
 Ref Clock Gen(MHz)	: 156.25
 Data Rate(Gbps)		: 10.3125
 Description			: 10 GbE
@@ -60,60 +60,60 @@ Description			: 10 GbE
 Data Rate Detection Configuration Registers
 
 Mode Pin Settings:
-Mode State	: 0 
+Mode State	: 0
-MODE1		: 0 
+MODE1		: 0
-MODE0		: 0 
+MODE0		: 0
 Mode		: Two-wire serial interface mode
 
 LOS Pin Strap Mode Settings
-Mode State			: 2/6/8 
+Mode State			: 2/6/8
-State				: 4 
+State				: 4
 LOS1				: Float
-LOS0				: Float 
+LOS0				: Float
-LOS Amplitude(mVpp)	: 20 
+LOS Amplitude(mVpp)	: 20
 LOS Hysteresis(dB)	: 2
 
 Input Equalization Retimer Mode Settings
 Mode State		: 6/8
-EQ State		: 0 
+EQ State		: 0
-EQ1				: 0 
+EQ1				: 0
-EQ0				: 0 
+EQ0				: 0
-EQ(dB)			: Auto 
+EQ(dB)			: Auto
-DFE				: Auto 
+DFE				: Auto
 Comment			: Full Auto
 
 Input Equalization Re-Driver Mode Settings
-Mode State		: 
+Mode State		:
-EQ State		: 0 
+EQ State		: 0
-EQ1				: 0 
+EQ1				: 0
-EQ0				: 0 
+EQ0				: 0
-EQ(dB)			: Auto 
+EQ(dB)			: Auto
-DFE				: APowered Down 
+DFE				: APowered Down
 Comment			: Analog EQ Only
 
 
 
 Output De-Emphasis Retimer Mode Settings
-Mode State		: 6/8 
+Mode State		: 6/8
-DE State		: 3 
+DE State		: 3
-TX1				: Float 
+TX1				: Float
-TX0				: 0 
+TX0				: 0
-PRE  c(-1) mA	: -1 
+PRE  c(-1) mA	: -1
 MAIN c( 0) mA	: 15
-POST c(+1) mA	: 4 
+POST c(+1) mA	: 4
 DC Amplitude(mV): 500
 De-Emphasis(dB)	: -6.02
-Comment			: 
+Comment			:
 
 
 Output De-Emphasis Re-Driver Mode Settings
-Mode State		: 2 
+Mode State		: 2
-DE State		: 3 
+DE State		: 3
-TX1				: Float 
+TX1				: Float
-TX0				: 0 
+TX0				: 0
-Frequency(Gbps)	: 10.3125 
+Frequency(Gbps)	: 10.3125
 DC Amplitude(mV): 600
-De-Emphasis(dB)	: 4 
+De-Emphasis(dB)	: 4
 Comment			: 10GbE
 
 
@@ -181,10 +181,10 @@ Page Reg Position Mask val RegFieldName
 0x00 0x97 b09 0x0200 1 PD_OD
 0x00 0xA0 b11 0x0800 1 PD_LOS
 0x00 0xA4 b15 0x8000 1 PD_CH
-0x00 0xB5 b07 0x0080 1 PD_INBUF 
+0x00 0xB5 b07 0x0080 1 PD_INBUF
-0x00 0xB9 b15 0x8000 1 ASYN_SYNN 
+0x00 0xB9 b15 0x8000 1 ASYN_SYNN
 0x00 0xB9 b09 0x0200 1 PD_OD
-0x00 0xBF b07 0x0080 1 PD_INBUF 
+0x00 0xBF b07 0x0080 1 PD_INBUF
 0x00 0xF0 b15 0x8000 1 ASYN_SYNN
 0x00 0xF0 b09 0x0200 1 PD_OD
 0x00 0xF6 b07 0x0080 1 PD_INBUF

src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c

@@ -80,7 +80,7 @@
 #define USE_ORIG_TEST_DRAM_BYTE 1
 
 // collect and print LMC utilization using SWL software algorithm
-#define ENABLE_SW_WLEVEL_UTILIZATION 0 
+#define ENABLE_SW_WLEVEL_UTILIZATION 0
 
 #define COUNT_RL_CANDIDATES 1
 
@@ -224,7 +224,7 @@ change_wr_deskew_ena(bdk_node_t node, int ddr_interface_num, int new_state)
 {
     bdk_lmcx_dll_ctl3_t ddr_dll_ctl3;
     int saved_wr_deskew_ena;
-    
+
     // return original WR_DESKEW_ENA setting
     ddr_dll_ctl3.u = BDK_CSR_READ(node, BDK_LMCX_DLL_CTL3(ddr_interface_num));
     saved_wr_deskew_ena = !!GET_DDR_DLL_CTL3(wr_deskew_ena);
@@ -270,15 +270,15 @@ Validate_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_
     uint64_t bl_mask[2]; // enough for 128 values
     int bit_values;
 #endif
-    deskew_data_t dskdat;    
+    deskew_data_t dskdat;
     int bit_index;
     int16_t flags, deskew;
     const char *fc = " ?-=+*#&";
     int saved_wr_deskew_ena;
     int bit_last;
-    
+
     // save original WR_DESKEW_ENA setting, and disable it for read deskew
-    saved_wr_deskew_ena = change_wr_deskew_ena(node, ddr_interface_num, 0); 
+    saved_wr_deskew_ena = change_wr_deskew_ena(node, ddr_interface_num, 0);
 
     lmc_config.u = BDK_CSR_READ(node, BDK_LMCX_CONFIG(ddr_interface_num));
     byte_limit = ((!lmc_config.s.mode32b) ? 8 : 4) + lmc_config.s.ecc_ena;
@@ -407,7 +407,7 @@ Validate_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_
         // just for completeness, allow print of the stuck values bitmask after the bytelane print
         if ((bit_values < 3) && print_enable) {
             VB_PRT(VBL_DEV, "N%d.LMC%d: Deskew byte %d STUCK on value 0x%016lx.%016lx\n",
-                   node, ddr_interface_num, byte_lane, 
+                   node, ddr_interface_num, byte_lane,
                    bl_mask[1], bl_mask[0]);
         }
 #endif
@@ -415,7 +415,7 @@ Validate_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_
     } /* for (byte_lane = 0; byte_lane < byte_limit; byte_lane++) */
 
     // restore original WR_DESKEW_ENA setting
-    change_wr_deskew_ena(node, ddr_interface_num, saved_wr_deskew_ena); 
+    change_wr_deskew_ena(node, ddr_interface_num, saved_wr_deskew_ena);
 
     return;
 }
@@ -433,13 +433,13 @@ unsigned short load_dac_override(int node, int ddr_interface_num,
 
     ddr_dll_ctl3.s.bit_select    = 0x9; /* No-op */
     DRAM_CSR_WRITE(node, BDK_LMCX_DLL_CTL3(ddr_interface_num), ddr_dll_ctl3.u);
-               
+
     ddr_dll_ctl3.s.bit_select    = 0xC; /* Vref bypass setting load */
     DRAM_CSR_WRITE(node, BDK_LMCX_DLL_CTL3(ddr_interface_num), ddr_dll_ctl3.u);
-               
+
     ddr_dll_ctl3.s.bit_select    = 0xD; /* Vref bypass on. */
     DRAM_CSR_WRITE(node, BDK_LMCX_DLL_CTL3(ddr_interface_num), ddr_dll_ctl3.u);
-               
+
     ddr_dll_ctl3.s.bit_select    = 0x9; /* No-op */
     DRAM_CSR_WRITE(node, BDK_LMCX_DLL_CTL3(ddr_interface_num), ddr_dll_ctl3.u);
 
@@ -545,9 +545,9 @@ Perform_Offset_Training(bdk_node_t node, int rank_mask, int ddr_interface_num)
 
     /*
      * 6.9.8 LMC Offset Training
-     * 
+     *
      * LMC requires input-receiver offset training.
-     * 
+     *
      * 1. Write LMC(0)_PHY_CTL[DAC_ON] = 1
      */
     lmc_phy_ctl.u = BDK_CSR_READ(node, BDK_LMCX_PHY_CTL(ddr_interface_num));
@@ -576,7 +576,7 @@ Perform_Offset_Training(bdk_node_t node, int rank_mask, int ddr_interface_num)
     /*
      * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0B and
      *    LMC(0)_SEQ_CTL[INIT_START] = 1.
-     * 
+     *
      * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1.
      */
     perform_octeon3_ddr3_sequence(node, rank_mask, ddr_interface_num, 0x0B); /* Offset training sequence */
@@ -590,9 +590,9 @@ Perform_Internal_VREF_Training(bdk_node_t node, int rank_mask, int ddr_interface
 
     /*
      * 6.9.9 LMC Internal Vref Training
-     * 
+     *
      * LMC requires input-reference-voltage training.
-     * 
+     *
      * 1. Write LMC(0)_EXT_CONFIG[VREFINT_SEQ_DESKEW] = 0.
      */
     ext_config.u = BDK_CSR_READ(node, BDK_LMCX_EXT_CONFIG(ddr_interface_num));
@@ -606,7 +606,7 @@ Perform_Internal_VREF_Training(bdk_node_t node, int rank_mask, int ddr_interface
     /*
      * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0a and
      *    LMC(0)_SEQ_CTL[INIT_START] = 1.
-     * 
+     *
      * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1.
      */
     perform_octeon3_ddr3_sequence(node, rank_mask, ddr_interface_num, 0x0A); /* LMC Internal Vref Training */
@@ -646,7 +646,7 @@ process_samples_average(int16_t *bytes, int num_samples, int lmc, int lane_no)
         ret = trunc;
     else if (sadj & 1)
         ret = sadj;
-    else 
+    else
         ret = trunc + 1;
 
     dbg_avg(" -> %3d\n", ret);
@@ -678,7 +678,7 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
     VB_PRT(VBL_FAE, "N%d.LMC%d: Performing Read Deskew Training.\n", node, ddr_interface_num);
 
     // save original WR_DESKEW_ENA setting, and disable it for read deskew
-    saved_wr_deskew_ena = change_wr_deskew_ena(node, ddr_interface_num, 0); 
+    saved_wr_deskew_ena = change_wr_deskew_ena(node, ddr_interface_num, 0);
 
     sat_retries = 0;
     lock_retries_total = 0;
@@ -718,9 +718,9 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
 
         /*
          * 6.9.10 LMC Deskew Training
-         * 
+         *
          * LMC requires input-read-data deskew training.
-         * 
+         *
          * 1. Write LMC(0)_EXT_CONFIG[VREFINT_SEQ_DESKEW] = 1.
          */
         VB_PRT(VBL_SEQ, "N%d.LMC%d: Performing LMC sequence: Set vrefint_seq_deskew = 1\n",
@@ -731,7 +731,7 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
         /*
          * 2. Write LMC(0)_SEQ_CTL[SEQ_SEL] = 0x0A and
          *    LMC(0)_SEQ_CTL[INIT_START] = 1.
-         * 
+         *
          * 3. Wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be set to 1.
          */
         DRAM_CSR_MODIFY(phy_ctl, node, BDK_LMCX_PHY_CTL(ddr_interface_num),
@@ -742,7 +742,7 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
 
     perform_read_deskew_training:
         // maybe perform the NORMAL deskew training sequence multiple times before looking at lock status
-        for (loops = 0; loops < normal_loops; loops++) { 
+        for (loops = 0; loops < normal_loops; loops++) {
             DRAM_CSR_MODIFY(phy_ctl, node, BDK_LMCX_PHY_CTL(ddr_interface_num),
                             phy_ctl.s.phy_dsk_reset = 0); /* Normal Deskew sequence */
             perform_octeon3_ddr3_sequence(node, rank_mask, ddr_interface_num, 0x0A); /* LMC Deskew Training */
@@ -823,7 +823,7 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
            sat_retries-1, lock_retries_total);
 
     // restore original WR_DESKEW_ENA setting
-    change_wr_deskew_ena(node, ddr_interface_num, saved_wr_deskew_ena); 
+    change_wr_deskew_ena(node, ddr_interface_num, saved_wr_deskew_ena);
 
     if ((dsk_counts.nibrng_errs != 0) || (dsk_counts.nibunl_errs != 0)) {
         debug_print("N%d.LMC%d: NIBBLE ERROR(S) found, returning FAULT\n",
@@ -831,7 +831,7 @@ Perform_Read_Deskew_Training(bdk_node_t node, int rank_mask, int ddr_interface_n
         return -1; // we did retry locally, they did not help
     }
 
-    // NOTE: we (currently) always print one last training validation before starting Read Leveling... 
+    // NOTE: we (currently) always print one last training validation before starting Read Leveling...
 
     return 0;
 }
@@ -907,7 +907,7 @@ Set_Write_Deskew_Settings(bdk_node_t node, int ddr_interface_num, int value)
     VB_PRT(VBL_DEV2, "N%d.LMC%d: SetWriteDeskew: WRITE %d\n", node, ddr_interface_num, value);
 
     for (bit_num = 0; bit_num <= 7; ++bit_num) {
- 
+
         // write a bit-deskew value to all bit-lanes of all bytes
         ddr_dll_ctl3.u = BDK_CSR_READ(node, BDK_LMCX_DLL_CTL3(ddr_interface_num));
         SET_DDR_DLL_CTL3(bit_select, bit_num);
@@ -949,13 +949,13 @@ Neutral_Write_Deskew_Setup(bdk_node_t node, int ddr_interface_num)
 {
     // first: NO-OP, Select all bytes, Disable write bit-deskew
     ddr_print("N%d.LMC%d: NEUTRAL Write Deskew Setup: first: NOOP\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0); 
+    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0);
     //Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     //Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 
     // enable write bit-deskew and RESET the settings
     ddr_print("N%d.LMC%d: NEUTRAL Write Deskew Setup: wr_ena: RESET\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_RESET, ALL_BYTES, 1); 
+    do_write_deskew_op(node, ddr_interface_num, BS_RESET, ALL_BYTES, 1);
     //Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     //Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 }
@@ -982,20 +982,20 @@ Perform_Write_Deskew_Training(bdk_node_t node, int ddr_interface_num)
 
     // first: NO-OP, Select all bytes, Disable write bit-deskew
     ddr_print("N%d.LMC%d: WriteDeskewConfig: first: NOOP\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0); 
+    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0);
     //Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     //Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 
     // enable write bit-deskew and RESET the settings
     ddr_print("N%d.LMC%d: WriteDeskewConfig: wr_ena: RESET\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_RESET, ALL_BYTES, 1); 
+    do_write_deskew_op(node, ddr_interface_num, BS_RESET, ALL_BYTES, 1);
     //Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     //Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 
 #if 0
     // enable write bit-deskew and REUSE read bit-deskew settings
     ddr_print("N%d.LMC%d: WriteDeskewConfig: wr_ena: REUSE\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_REUSE, ALL_BYTES, 1); 
+    do_write_deskew_op(node, ddr_interface_num, BS_REUSE, ALL_BYTES, 1);
     Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 #endif
@@ -1107,7 +1107,7 @@ Perform_Write_Deskew_Training(bdk_node_t node, int ddr_interface_num)
 
     // last: NO-OP, Select all bytes, MUST leave write bit-deskew enabled
     ddr_print("N%d.LMC%d: WriteDeskewConfig: last: wr_ena: NOOP\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 1); 
+    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 1);
     //Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     //Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 
@@ -1115,7 +1115,7 @@ Perform_Write_Deskew_Training(bdk_node_t node, int ddr_interface_num)
     // FIXME: disable/delete this when write bit-deskew works...
     // final: NO-OP, Select all bytes, do NOT leave write bit-deskew enabled
     ddr_print("N%d.LMC%d: WriteDeskewConfig: final: read: NOOP\n", node, ddr_interface_num);
-    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0); 
+    do_write_deskew_op(node, ddr_interface_num, BS_NOOP, ALL_BYTES, 0);
     Get_Deskew_Settings(node, ddr_interface_num, &dskdat);
     Display_Deskew_Data(node, ddr_interface_num, &dskdat, VBL_NORM);
 #endif
@@ -1291,7 +1291,7 @@ compute_vref_value(bdk_node_t node, int ddr_interface_num,
         BDK_CSR_INIT(lmc_config, node, BDK_LMCX_CONFIG(ddr_interface_num));
         /*
           New computed Vref = existing computed Vref – X
- 
+
           The value of X is depending on different conditions. Both #122 and #139 are 2Rx4 RDIMM,
           while #124 is stacked die 2Rx4, so I conclude the results into two conditions:
 
@@ -1315,7 +1315,7 @@ compute_vref_value(bdk_node_t node, int ddr_interface_num,
             }
             // we have adjusted it, so print it out if verbosity is right
             VB_PRT(VBL_TME, "N%d.LMC%d.R%d: adjusting computed vref from %2d (0x%02x) to %2d (0x%02x)\n",
-                   node, ddr_interface_num, rankx, 
+                   node, ddr_interface_num, rankx,
                    saved_final_vref_value, saved_final_vref_value,
                    computed_final_vref_value, computed_final_vref_value);
         }
@@ -1505,7 +1505,7 @@ validate_ddr3_rlevel_bitmask(rlevel_bitmask_t *rlevel_bitmask_p, int ddr_type)
                     extras++; // count the number of extra bits
             }
         }
-        
+
         /* Penalize any extra 1's beyond the maximum desired mask */
         if (extras > 0)
             toolong = RLEVEL_BITMASK_TOOLONG_ERROR * ((1 << extras) - 1);
@@ -1634,13 +1634,13 @@ Validate_HW_WL_Settings(bdk_node_t node, int ddr_interface_num,
 {
     int wl[9], byte, errors;
 
-    // arrange the sequences so 
+    // arrange the sequences so
     int useq[] = { 0,1,2,3,8,4,5,6,7,-1 }; // index 0 has byte 0, etc, ECC in middle
     int rseq1[] = { 8,3,2,1,0,-1 }; // index 0 is ECC, then go down
     int rseq2[] = { 4,5,6,7,-1 }; // index 0 has byte 4, then go up
     int useqno[] = { 0,1,2,3,4,5,6,7,-1 }; // index 0 has byte 0, etc, no ECC
     int rseq1no[] = { 3,2,1,0,-1 }; // index 0 is byte 3, then go down, no ECC
-    
+
     // in the CSR, bytes 0-7 are always data, byte 8 is ECC
     for (byte = 0; byte < 8+ecc_ena; byte++) {
         wl[byte] = (get_wlevel_rank_struct(lmc_wlevel_rank, byte) >> 1) & 3; // preprocess :-)
@@ -1683,7 +1683,7 @@ static int  get_rlevel_rank_struct(bdk_lmcx_rlevel_rankx_t *lmc_rlevel_rank,
 }
 #endif
 
-static void unpack_rlevel_settings(int ddr_interface_bytemask, int ecc_ena, 
+static void unpack_rlevel_settings(int ddr_interface_bytemask, int ecc_ena,
                                    rlevel_byte_data_t *rlevel_byte,
                                    bdk_lmcx_rlevel_rankx_t lmc_rlevel_rank)
 {
@@ -1713,11 +1713,11 @@ static void unpack_rlevel_settings(int ddr_interface_bytemask, int ecc_ena,
     rlevel_byte[0].delay = lmc_rlevel_rank.cn83xx.byte0;
 }
 
-static void pack_rlevel_settings(int ddr_interface_bytemask, int ecc_ena, 
+static void pack_rlevel_settings(int ddr_interface_bytemask, int ecc_ena,
                                  rlevel_byte_data_t *rlevel_byte,
                                  bdk_lmcx_rlevel_rankx_t *final_rlevel_rank)
 {
-    bdk_lmcx_rlevel_rankx_t lmc_rlevel_rank = *final_rlevel_rank; 
+    bdk_lmcx_rlevel_rankx_t lmc_rlevel_rank = *final_rlevel_rank;
 
     if ((ddr_interface_bytemask & 0xff) == 0xff) {
         if (ecc_ena) {
@@ -1808,7 +1808,7 @@ static int nonsequential_delays(rlevel_byte_data_t *rlevel_byte,
         }
 
         delay_inc = _abs(delay_diff); // how big was the delay change, if any
-        
+
         /* Even if the trend did not change to the opposite direction, check for
            the magnitude of the change, and scale the penalty by the amount that
            the size is larger than the provided limit.
@@ -1954,9 +1954,9 @@ display_RL_with_computed(bdk_node_t node, int ddr_interface_num, bdk_lmcx_rlevel
 // control
 #define SKIP_SKIPPING 1
 
-static const char *with_rodt_canned_msgs[4] = { "          ", "SKIPPING  ", "BEST ROW  ", "BEST SCORE" }; 
+static const char *with_rodt_canned_msgs[4] = { "          ", "SKIPPING  ", "BEST ROW  ", "BEST SCORE" };
 
-static void display_RL_with_RODT(bdk_node_t node, int ddr_interface_num, 
+static void display_RL_with_RODT(bdk_node_t node, int ddr_interface_num,
                                  bdk_lmcx_rlevel_rankx_t lmc_rlevel_rank, int rank, int score,
                                  int nom_ohms, int rodt_ohms, int flag)
 {
@@ -1969,9 +1969,9 @@ static void display_RL_with_RODT(bdk_node_t node, int ddr_interface_num,
     if (nom_ohms < 0) {
         snprintf(set_buf, sizeof(set_buf), "    RODT %3d    ", rodt_ohms);
     } else {
-        snprintf(set_buf, sizeof(set_buf), "NOM %3d RODT %3d", nom_ohms, rodt_ohms);        
+        snprintf(set_buf, sizeof(set_buf), "NOM %3d RODT %3d", nom_ohms, rodt_ohms);
     }
-    
+
     VB_PRT(VBL_TME, "N%d.LMC%d.R%d: Rlevel %s   %s  : %5d %5d %5d %5d %5d %5d %5d %5d %5d (%d)\n",
            node, ddr_interface_num, rank,
            set_buf, msg_buf,
@@ -2249,7 +2249,7 @@ void perform_octeon3_ddr3_sequence(bdk_node_t node, int rank_mask, int ddr_inter
      *    LMC(0)_SEQ_CTL[SEQ_SEL,INIT_START] = 1 with a single CSR write
      *    operation. LMC(0)_CONFIG[RANKMASK] bits should be set to indicate
      *    the ranks that will participate in the sequence.
-     * 
+     *
      *    The LMC(0)_SEQ_CTL[SEQ_SEL] value should select power-up/init or
      *    selfrefresh exit, depending on whether the DRAM parts are in
      *    self-refresh and whether their contents should be preserved. While
@@ -2257,7 +2257,7 @@ void perform_octeon3_ddr3_sequence(bdk_node_t node, int rank_mask, int ddr_inter
      *    transactions. When the sequence is complete, hardware sets the
      *    LMC(0)_CONFIG[INIT_STATUS] bits for the ranks that have been
      *    initialized.
-     * 
+     *
      *    If power-up/init is selected immediately following a DRESET
      *    assertion, LMC executes the sequence described in the "Reset and
      *    Initialization Procedure" section of the JEDEC DDR3
@@ -2270,16 +2270,16 @@ void perform_octeon3_ddr3_sequence(bdk_node_t node, int rank_mask, int ddr_inter
      *    the first DDR3 mode register write operation.
      *    LMC(0)_DIMM_CTL[DIMM*_WMASK] should be cleared to 0 if the
      *    corresponding DIMM is not present.
-     * 
+     *
      *    If self-refresh exit is selected, LMC executes the required SRX
      *    command followed by a refresh and ZQ calibration. Section 4.5
      *    describes behavior of a REF + ZQCS.  LMC does not write the DDR3
      *    mode registers as part of this sequence, and the mode register
      *    parameters must match at self-refresh entry and exit times.
-     * 
+     *
      * 4. Read LMC(0)_SEQ_CTL and wait for LMC(0)_SEQ_CTL[SEQ_COMPLETE] to be
      *    set.
-     * 
+     *
      * 5. Read LMC(0)_CONFIG[INIT_STATUS] and confirm that all ranks have
      *    been initialized.
      */
@@ -2351,8 +2351,8 @@ void ddr4_mrw(bdk_node_t node, int ddr_interface_num, int rank,
     lmc_mr_mpr_ctl.s.mr_wr_rank                 = rank;
     //lmc_mr_mpr_ctl.s.mr_wr_pda_mask           =
     //lmc_mr_mpr_ctl.s.mr_wr_pda_enable         =
-    //lmc_mr_mpr_ctl.s.mpr_loc                  = 
+    //lmc_mr_mpr_ctl.s.mpr_loc                  =
-    //lmc_mr_mpr_ctl.s.mpr_wr                   = 
+    //lmc_mr_mpr_ctl.s.mpr_wr                   =
     //lmc_mr_mpr_ctl.s.mpr_bit_select           =
     //lmc_mr_mpr_ctl.s.mpr_byte_select          =
     //lmc_mr_mpr_ctl.s.mpr_whole_byte_enable    =
@@ -3032,7 +3032,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
     if ((s = lookup_env_parameter("ddr_deskew_validation_delay")) != NULL) {
         deskew_validation_delay = strtoul(s, NULL, 0);
     }
-    // this one is in Perform_Read_Deskew_Training and controls lock retries 
+    // this one is in Perform_Read_Deskew_Training and controls lock retries
     if ((s = lookup_env_parameter("ddr_lock_retries")) != NULL) {
         default_lock_retry_limit = strtoul(s, NULL, 0);
     }
@@ -3164,7 +3164,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
             // FIXME: print non-zero monolithic device definition
             ddr_print("DDR4: Package Type MONOLITHIC: %d die, signal load %d\n",
                       ((spd_package >> 4) & 7) + 1, (spd_package & 3));
-        }   
+        }
 
         asymmetric = (spd_org >> 6) & 1;
         if (asymmetric) {
@@ -3208,7 +3208,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
             ddr_print("DDR4: RDIMM Register Manufacturer ID 0x%x Revision 0x%x\n",
                       spd_mfgr_id, spd_register_rev);
 
-            // RAWCARD A or B must be bit 7=0 and bits 4-0 either 00000(A) or 00001(B) 
+            // RAWCARD A or B must be bit 7=0 and bits 4-0 either 00000(A) or 00001(B)
             spd_rawcard_AorB = ((spd_rawcard & 0x9fUL) <= 1);
         }
     } else {
@@ -3762,14 +3762,14 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
      /*
      * 6.9.7 Early LMC Initialization
-     * 
+     *
      * All of DDR PLL, LMC CK, and LMC DRESET initializations must be
      * completed prior to starting this LMC initialization sequence.
-     * 
+     *
      * Perform the following five substeps for early LMC initialization:
-     * 
+     *
      * 1. Software must ensure there are no pending DRAM transactions.
-     * 
+     *
      * 2. Write LMC(0)_CONFIG, LMC(0)_CONTROL, LMC(0)_TIMING_PARAMS0,
      *    LMC(0)_TIMING_PARAMS1, LMC(0)_MODEREG_PARAMS0,
      *    LMC(0)_MODEREG_PARAMS1, LMC(0)_DUAL_MEMCFG, LMC(0)_NXM,
@@ -5073,7 +5073,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
  perform_internal_vref_training:
 
-    for (sample = 0; sample < num_samples; sample++) { 
+    for (sample = 0; sample < num_samples; sample++) {
 
         dac_eval_retries = 0;
 
@@ -5265,48 +5265,48 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
     /*
      * 6.9.11 LMC Write Leveling
-     * 
+     *
      * LMC supports an automatic write leveling like that described in the
      * JEDEC DDR3 specifications separately per byte-lane.
-     * 
+     *
      * All of DDR PLL, LMC CK, LMC DRESET, and early LMC initializations must
      * be completed prior to starting this LMC write-leveling sequence.
-     * 
+     *
      * There are many possible procedures that will write-level all the
      * attached DDR3 DRAM parts. One possibility is for software to simply
      * write the desired values into LMC(0)_WLEVEL_RANK(0..3). This section
      * describes one possible sequence that uses LMC's autowrite-leveling
      * capabilities.
-     * 
+     *
      * 1. If the DQS/DQ delays on the board may be more than the ADD/CMD
      *    delays, then ensure that LMC(0)_CONFIG[EARLY_DQX] is set at this
      *    point.
-     * 
+     *
      * Do the remaining steps 2-7 separately for each rank i with attached
      * DRAM.
-     * 
+     *
      * 2. Write LMC(0)_WLEVEL_RANKi = 0.
-     * 
+     *
      * 3. For ×8 parts:
-     * 
+     *
      *    Without changing any other fields in LMC(0)_WLEVEL_CTL, write
      *    LMC(0)_WLEVEL_CTL[LANEMASK] to select all byte lanes with attached
      *    DRAM.
-     * 
+     *
      *    For ×16 parts:
-     * 
+     *
      *    Without changing any other fields in LMC(0)_WLEVEL_CTL, write
      *    LMC(0)_WLEVEL_CTL[LANEMASK] to select all even byte lanes with
      *    attached DRAM.
-     * 
+     *
      * 4. Without changing any other fields in LMC(0)_CONFIG,
-     * 
+     *
      *    o write LMC(0)_SEQ_CTL[SEQ_SEL] to select write-leveling
-     * 
+     *
      *    o write LMC(0)_CONFIG[RANKMASK] = (1 << i)
-     * 
+     *
      *    o write LMC(0)_SEQ_CTL[INIT_START] = 1
-     * 
+     *
      *    LMC will initiate write-leveling at this point. Assuming
      *    LMC(0)_WLEVEL_CTL [SSET] = 0, LMC first enables write-leveling on
      *    the selected DRAM rank via a DDR3 MR1 write, then sequences through
@@ -5315,17 +5315,17 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
      *    LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] = 0, increasing by 1/8 CK each
      *    setting, covering a total distance of one CK, then disables the
      *    write-leveling via another DDR3 MR1 write.
-     * 
+     *
      *    After the sequence through 16 delay settings is complete:
-     * 
+     *
      *    o LMC sets LMC(0)_WLEVEL_RANKi[STATUS] = 3
-     * 
+     *
      *    o LMC sets LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] (for all ranks selected
      *      by LMC(0)_WLEVEL_CTL[LANEMASK]) to indicate the first write
      *      leveling result of 1 that followed result of 0 during the
      *      sequence, except that the LMC always writes
      *      LMC(0)_WLEVEL_RANKi[BYTE*<0>]=0.
-     * 
+     *
      *    o Software can read the eight write-leveling results from the first
      *      pass through the delay settings by reading
      *      LMC(0)_WLEVEL_DBG[BITMASK] (after writing
@@ -5333,66 +5333,66 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
      *      results from the second pass through the eight delay
      *      settings. They should often be identical to the
      *      LMC(0)_WLEVEL_DBG[BITMASK] results, though.)
-     * 
+     *
      * 5. Wait until LMC(0)_WLEVEL_RANKi[STATUS] != 2.
-     * 
+     *
      *    LMC will have updated LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] for all byte
      *    lanes selected by LMC(0)_WLEVEL_CTL[LANEMASK] at this point.
      *    LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] will still be the value that
      *    software wrote in substep 2 above, which is 0.
-     * 
+     *
      * 6. For ×16 parts:
-     * 
+     *
      *    Without changing any other fields in LMC(0)_WLEVEL_CTL, write
      *    LMC(0)_WLEVEL_CTL[LANEMASK] to select all odd byte lanes with
      *    attached DRAM.
-     * 
+     *
      *    Repeat substeps 4 and 5 with this new LMC(0)_WLEVEL_CTL[LANEMASK]
      *    setting. Skip to substep 7 if this has already been done.
-     * 
+     *
      *    For ×8 parts:
-     * 
+     *
      *    Skip this substep. Go to substep 7.
-     * 
+     *
      * 7. Calculate LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] settings for all byte
      *    lanes on all ranks with attached DRAM.
-     * 
+     *
      *    At this point, all byte lanes on rank i with attached DRAM should
      *    have been write-leveled, and LMC(0)_WLEVEL_RANKi[BYTE*<2:0>] has
      *    the result for each byte lane.
-     * 
+     *
      *    But note that the DDR3 write-leveling sequence will only determine
      *    the delay modulo the CK cycle time, and cannot determine how many
      *    additional CK cycles of delay are present. Software must calculate
      *    the number of CK cycles, or equivalently, the
      *    LMC(0)_WLEVEL_RANKi[BYTE*<4:3>] settings.
-     * 
+     *
      *    This BYTE*<4:3> calculation is system/board specific.
-     * 
+     *
      * Many techniques can be used to calculate write-leveling BYTE*<4:3> values,
      * including:
-     * 
+     *
      *    o Known values for some byte lanes.
-     * 
+     *
      *    o Relative values for some byte lanes relative to others.
-     * 
+     *
      *    For example, suppose lane X is likely to require a larger
      *    write-leveling delay than lane Y. A BYTEX<2:0> value that is much
      *    smaller than the BYTEY<2:0> value may then indicate that the
      *    required lane X delay wrapped into the next CK, so BYTEX<4:3>
      *    should be set to BYTEY<4:3>+1.
-     * 
+     *
      *    When ECC DRAM is not present (i.e. when DRAM is not attached to the
      *    DDR_CBS_0_* and DDR_CB<7:0> chip signals, or the DDR_DQS_<4>_* and
      *    DDR_DQ<35:32> chip signals), write LMC(0)_WLEVEL_RANK*[BYTE8] =
      *    LMC(0)_WLEVEL_RANK*[BYTE0], using the final calculated BYTE0 value.
      *    Write LMC(0)_WLEVEL_RANK*[BYTE4] = LMC(0)_WLEVEL_RANK*[BYTE0],
      *    using the final calculated BYTE0 value.
-     * 
+     *
      * 8. Initialize LMC(0)_WLEVEL_RANK* values for all unused ranks.
-     * 
+     *
      *    Let rank i be a rank with attached DRAM.
-     * 
+     *
      *    For all ranks j that do not have attached DRAM, set
      *    LMC(0)_WLEVEL_RANKj = LMC(0)_WLEVEL_RANKi.
      */
@@ -5794,18 +5794,18 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
     /*
      * 6.9.12 LMC Read Leveling
-     * 
+     *
      * LMC supports an automatic read-leveling separately per byte-lane using
      * the DDR3 multipurpose register predefined pattern for system
      * calibration defined in the JEDEC DDR3 specifications.
-     * 
+     *
      * All of DDR PLL, LMC CK, and LMC DRESET, and early LMC initializations
      * must be completed prior to starting this LMC read-leveling sequence.
-     * 
+     *
      * Software could simply write the desired read-leveling values into
      * LMC(0)_RLEVEL_RANK(0..3). This section describes a sequence that uses
      * LMC's autoread-leveling capabilities.
-     * 
+     *
      * When LMC does the read-leveling sequence for a rank, it first enables
      * the DDR3 multipurpose register predefined pattern for system
      * calibration on the selected DRAM rank via a DDR3 MR3 write, then
@@ -5814,13 +5814,13 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
      * operation. LMC determines the pass or fail of each of the 64 settings
      * independently for each byte lane, then writes appropriate
      * LMC(0)_RLEVEL_RANK(0..3)[BYTE*] values for the rank.
-     * 
+     *
      * After read-leveling for a rank, software can read the 64 pass/fail
      * indications for one byte lane via LMC(0)_RLEVEL_DBG[BITMASK]. Software
      * can observe all pass/fail results for all byte lanes in a rank via
      * separate read-leveling sequences on the rank with different
      * LMC(0)_RLEVEL_CTL[BYTE] values.
-     * 
+     *
      * The 64 pass/fail results will typically have failures for the low
      * delays, followed by a run of some passing settings, followed by more
      * failures in the remaining high delays.  LMC sets
@@ -5834,46 +5834,46 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
      * the run (rounding earlier when necessary). We expect the read-leveling
      * sequence to produce good results with the reset values
      * LMC(0)_RLEVEL_CTL [OFFSET_EN]=1, LMC(0)_RLEVEL_CTL[OFFSET] = 2.
-     * 
+     *
      * The read-leveling sequence has the following steps:
-     * 
+     *
      * 1. Select desired LMC(0)_RLEVEL_CTL[OFFSET_EN,OFFSET,BYTE] settings.
      *    Do the remaining substeps 2-4 separately for each rank i with
      *    attached DRAM.
-     * 
+     *
      * 2. Without changing any other fields in LMC(0)_CONFIG,
-     * 
+     *
      *    o write LMC(0)_SEQ_CTL[SEQ_SEL] to select read-leveling
-     * 
+     *
      *    o write LMC(0)_CONFIG[RANKMASK] = (1 << i)
-     * 
+     *
      *    o write LMC(0)_SEQ_CTL[INIT_START] = 1
-     * 
+     *
      *    This initiates the previously-described read-leveling.
-     * 
+     *
      * 3. Wait until LMC(0)_RLEVEL_RANKi[STATUS] != 2
-     * 
+     *
      *    LMC will have updated LMC(0)_RLEVEL_RANKi[BYTE*] for all byte lanes
      *    at this point.
-     * 
+     *
      *    If ECC DRAM is not present (i.e. when DRAM is not attached to the
      *    DDR_CBS_0_* and DDR_CB<7:0> chip signals, or the DDR_DQS_<4>_* and
      *    DDR_DQ<35:32> chip signals), write LMC(0)_RLEVEL_RANK*[BYTE8] =
      *    LMC(0)_RLEVEL_RANK*[BYTE0]. Write LMC(0)_RLEVEL_RANK*[BYTE4] =
      *    LMC(0)_RLEVEL_RANK*[BYTE0].
-     * 
+     *
      * 4. If desired, consult LMC(0)_RLEVEL_DBG[BITMASK] and compare to
      *    LMC(0)_RLEVEL_RANKi[BYTE*] for the lane selected by
      *    LMC(0)_RLEVEL_CTL[BYTE]. If desired, modify LMC(0)_RLEVEL_CTL[BYTE]
      *    to a new value and repeat so that all BITMASKs can be observed.
-     * 
+     *
      * 5. Initialize LMC(0)_RLEVEL_RANK* values for all unused ranks.
-     * 
+     *
      *    Let rank i be a rank with attached DRAM.
-     * 
+     *
      *    For all ranks j that do not have attached DRAM, set
      *    LMC(0)_RLEVEL_RANKj = LMC(0)_RLEVEL_RANKi.
-     * 
+     *
      * This read-leveling sequence can help select the proper CN70XX ODT
      * resistance value (LMC(0)_COMP_CTL2[RODT_CTL]). A hardware-generated
      * LMC(0)_RLEVEL_RANKi[BYTEj] value (for a used byte lane j) that is
@@ -6083,7 +6083,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                 i = 0;
                 while (custom_lmc_config->rlevel_table[i].part != NULL) {
                     debug_print("DIMM part number:\"%s\", SPD: \"%s\"\n", custom_lmc_config->rlevel_table[i].part, part_number);
-                    if ((strcmp(part_number, custom_lmc_config->rlevel_table[i].part) == 0) 
+                    if ((strcmp(part_number, custom_lmc_config->rlevel_table[i].part) == 0)
                         && (_abs(custom_lmc_config->rlevel_table[i].speed - 2*ddr_hertz/(1000*1000)) < 10 ))
                     {
                         ddr_print("Using hard-coded read leveling for DIMM part number: \"%s\"\n", part_number);
@@ -6290,7 +6290,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                     rlevel_bitmask[7].bm = octeon_read_lmcx_ddr3_rlevel_dbg(node, ddr_interface_num, 7);
                                     /* B-side complete */
 
-                        
+
                                     update_rlevel_rank_struct(&lmc_rlevel_rank, 0, lmc_rlevel_rank_aside.cn83xx.byte0);
                                     update_rlevel_rank_struct(&lmc_rlevel_rank, 1, lmc_rlevel_rank_aside.cn83xx.byte1);
                                     update_rlevel_rank_struct(&lmc_rlevel_rank, 2, lmc_rlevel_rank_aside.cn83xx.byte2);
@@ -6390,7 +6390,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 #else
                                 rlevel_rank_errors = rlevel_bitmask_errors + rlevel_nonseq_errors;
 #endif
-                                
+
                                 // print original sample here only if we are not really averaging or picking best
                                 // also do not print if we were redoing the NONSEQ score for using COMPUTED
                                 if (!redoing_nonseq_errs && ((rlevel_avg_loops < 2) || dram_is_verbose(VBL_DEV2))) {
@@ -6833,7 +6833,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                 best_rank_ohms      = next_ohms;
                                 best_rankx          = orankx;
                                 lmc_rlevel_rank.u   = rlevel_scoreboard[rtt_nom][rodt_ctl][orankx].setting;
- 
+
                             } /* for (int orankx = 0; orankx < dimm_count * 4; orankx++) */
                         } /* for (rodt_ctl = max_rodt_ctl; rodt_ctl >= min_rodt_ctl; --rodt_ctl) */
                     } /* for (rtt_idx = min_rtt_nom_idx; rtt_idx <= max_rtt_nom_idx; ++rtt_idx) */
@@ -7233,7 +7233,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                             if (delay_value >= 0) {
                                 if (ties != 0) {
                                     if (ties & (1UL << (int)new_byte)) {
-                                        // leave choice as new_byte if any tied one is the same... 
+                                        // leave choice as new_byte if any tied one is the same...
 
 
                                         delay_value = (int)new_byte;
@@ -7251,7 +7251,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                 if (delay_value != (int)new_byte) {
                                     delay_count = rank_perfect_counts[rankx].count[byte_idx][(int)new_byte];
                                     VB_PRT(VBL_DEV, "N%d.LMC%d.R%d: PERFECT: Byte %d: DIFF from %d (%d), USING %d (%d)\n",
-                                           node, ddr_interface_num, rankx, byte_idx, (int)new_byte, 
+                                           node, ddr_interface_num, rankx, byte_idx, (int)new_byte,
                                            delay_count, delay_value, delay_max);
                                     new_byte = (uint64_t)delay_value; // FIXME: make this optional via envvar?
                                 } else {
@@ -7522,7 +7522,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
         /* Get the measured_vref setting from the config, check for an override... */
         /* NOTE: measured_vref=1 (ON) means force use of MEASURED Vref... */
-        // NOTE: measured VREF can only be done for DDR4 
+        // NOTE: measured VREF can only be done for DDR4
         if (ddr_type == DDR4_DRAM) {
             measured_vref_flag = custom_lmc_config->measured_vref;
             if ((s = lookup_env_parameter("ddr_measured_vref")) != NULL) {
@@ -7650,7 +7650,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                     } else {
                                         vrlo = 1; vvlo -= VREF_RANGE2_LIMIT;
                                     }
-                                    
+
                                     int vvhi = best_vref_values_start + best_vref_values_count - 1;
                                     int vrhi;
                                     if (vvhi < VREF_RANGE2_LIMIT) {
@@ -7678,7 +7678,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                 ddr_print("N%d.LMC%d.R%d: Vref Using Default                    :"
                                           "    %2d <----- %2d (0x%02x) -----> %2d, range%1d\n",
                                           node, ddr_interface_num, rankx,
-                                          final_vref_value, final_vref_value, 
+                                          final_vref_value, final_vref_value,
                                           final_vref_value, final_vref_value, final_vref_range+1);
                             }
                         }
@@ -7890,7 +7890,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
                                 if (!measured_vref_flag) {
                                     test_byte8 &= ~1; /* Use only even settings, rounding down... */
 
-                                    // do validity check on the calculated ECC delay value 
+                                    // do validity check on the calculated ECC delay value
                                     // this depends on the DIMM type
                                     if (spd_rdimm) { // RDIMM
                                         if (spd_dimm_type != 5) { // but not mini-RDIMM
@@ -8155,7 +8155,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
                     // do the test
                     if (sw_wlevel_hw) {
-                        errors = run_best_hw_patterns(node, ddr_interface_num, rank_addr, 
+                        errors = run_best_hw_patterns(node, ddr_interface_num, rank_addr,
                                                       DBTRAIN_TEST, NULL) & 0x0ff;
                     } else {
 #if USE_ORIG_TEST_DRAM_BYTE
@@ -8323,7 +8323,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
     process_custom_dll_offsets(node, ddr_interface_num, "ddr_dll_write_offset",
                                custom_lmc_config->dll_write_offset, "ddr%d_dll_write_offset_byte%d", 1);
-    process_custom_dll_offsets(node, ddr_interface_num, "ddr_dll_read_offset", 
+    process_custom_dll_offsets(node, ddr_interface_num, "ddr_dll_read_offset",
                                custom_lmc_config->dll_read_offset,  "ddr%d_dll_read_offset_byte%d",  2);
 
     // we want to train write bit-deskew here...
@@ -8337,29 +8337,29 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
 
     /*
      * 6.9.14 Final LMC Initialization
-     * 
+     *
      * Early LMC initialization, LMC write-leveling, and LMC read-leveling
      * must be completed prior to starting this final LMC initialization.
-     * 
+     *
      * LMC hardware updates the LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1,
      * LMC(0)_SLOT_CTL2 CSRs with minimum values based on the selected
      * readleveling and write-leveling settings. Software should not write
      * the final LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1, and LMC(0)_SLOT_CTL2
      * values until after the final read-leveling and write-leveling settings
      * are written.
-     * 
+     *
      * Software must ensure the LMC(0)_SLOT_CTL0, LMC(0)_SLOT_CTL1, and
      * LMC(0)_SLOT_CTL2 CSR values are appropriate for this step. These CSRs
      * select the minimum gaps between read operations and write operations
      * of various types.
-     * 
+     *
      * Software must not reduce the values in these CSR fields below the
      * values previously selected by the LMC hardware (during write-leveling
      * and read-leveling steps above).
-     * 
+     *
      * All sections in this chapter may be used to derive proper settings for
      * these registers.
-     * 
+     *
      * For minimal read latency, L2C_CTL[EF_ENA,EF_CNT] should be programmed
      * properly. This should be done prior to the first read.
      */

src/vendorcode/cavium/bdk/libdram/dram-internal.h

@@ -72,7 +72,7 @@
 // 1. looking for the best sample score
 // 2. averaging the samples into a composite score
 // symbol PICK_BEST_RANK_SCORE_NOT_AVG is used to choose
-// (see dram-init-ddr3.c: 
+// (see dram-init-ddr3.c:
 #define RLEVEL_AVG_LOOPS_DEFAULT 3
 #define PICK_BEST_RANK_SCORE_NOT_AVG 1
 
@@ -125,7 +125,7 @@ extern int dram_tuning_mem_xor(bdk_node_t node, int ddr_interface_num, uint64_t
 
 // "mode" arg
 #define DBTRAIN_TEST 0
-#define DBTRAIN_DBI  1 
+#define DBTRAIN_DBI  1
 #define DBTRAIN_LFSR 2
 extern int test_dram_byte_hw(bdk_node_t node, int ddr_interface_num,
                              uint64_t p, int mode, uint64_t *xor_data);

src/vendorcode/cavium/bdk/libdram/dram-spd.c

@@ -155,7 +155,7 @@ int read_spd(bdk_node_t node, const dimm_config_t *dimm_config, int spd_field)
         if (bank) {
             bdk_twsix_write_ia(node, bus, 0x36 | 0, 0, 2, 1, 0);
         }
-        
+
         return data;
     }
     else

src/vendorcode/cavium/bdk/libdram/dram-tune-ddr3.c

@@ -46,7 +46,7 @@
 #include <libbdk-hal/bdk-rng.h>
 #include <libbdk-os/bdk-init.h>
 
-// if enhanced verbosity levels are defined, use them 
+// if enhanced verbosity levels are defined, use them
 #if defined(VB_PRT)
 #define ddr_print2(format, ...) VB_PRT(VBL_FAE,  format, ##__VA_ARGS__)
 #define ddr_print3(format, ...) VB_PRT(VBL_TME,  format, ##__VA_ARGS__)
@@ -149,7 +149,7 @@ static const uint64_t *dram_tune_test_pattern = test_pattern_1;
 
 // set this to 1 to shorten the testing to exit when all byte lanes have errors
 // having this at 0 forces the testing to take place over the entire range every iteration,
-// hopefully ensuring an even load on the memory subsystem 
+// hopefully ensuring an even load on the memory subsystem
 #define EXIT_WHEN_ALL_LANES_HAVE_ERRORS 0
 
 #define DEFAULT_TEST_BURSTS 5 // FIXME: this is what works so far...// FIXME: was 7
@@ -198,7 +198,7 @@ get_speed_bin(bdk_node_t node, int lmc)
             ret = 1;
     }
 
-    debug_print("N%d.LMC%d: %s: returning bin %d for MTS %d\n", 
+    debug_print("N%d.LMC%d: %s: returning bin %d for MTS %d\n",
                 node, lmc, __FUNCTION__, ret, mts_speed);
 
     return ret;
@@ -260,13 +260,13 @@ int dram_tuning_mem_xor(bdk_node_t node, int lmc, uint64_t p, uint64_t bitmask,
 #define I_INC  (1ULL <<  3)
 #define I_MAX  (1ULL <<  7)
 
-    debug_print("N%d.LMC%d: dram_tuning_mem_xor: phys_addr=0x%lx\n", 
+    debug_print("N%d.LMC%d: dram_tuning_mem_xor: phys_addr=0x%lx\n",
               node, lmc, p);
 
 #if 0
     int ix;
     // add this loop to fill memory with the test pattern first
-    // loops are ordered so that only entire cachelines are written 
+    // loops are ordered so that only entire cachelines are written
     for (ii = 0; ii < II_MAX; ii += II_INC) { // FIXME? extend the range of memory tested!!
         for (k = 0; k < K_MAX; k += K_INC) {
             for (j = 0; j < J_MAX; j += J_INC) {
@@ -329,7 +329,7 @@ int dram_tuning_mem_xor(bdk_node_t node, int lmc, uint64_t p, uint64_t bitmask,
 
     BDK_DCACHE_INVALIDATE;
 
-    debug_print("N%d.LMC%d: dram_tuning_mem_xor: done INIT loop\n", 
+    debug_print("N%d.LMC%d: dram_tuning_mem_xor: done INIT loop\n",
               node, lmc);
 
     /* Make a series of passes over the memory areas. */
@@ -384,7 +384,7 @@ int dram_tuning_mem_xor(bdk_node_t node, int lmc, uint64_t p, uint64_t bitmask,
 
         BDK_DCACHE_INVALIDATE;
 
-        debug_print("N%d.LMC%d: dram_tuning_mem_xor: done MODIFY loop\n", 
+        debug_print("N%d.LMC%d: dram_tuning_mem_xor: done MODIFY loop\n",
                   node, lmc);
 
 #if ENABLE_PREFETCH
@@ -460,7 +460,7 @@ int dram_tuning_mem_xor(bdk_node_t node, int lmc, uint64_t p, uint64_t bitmask,
             }
         } /* for (ii = 0; ii < (1ULL << 31); ii += (1ULL << 29)) */
 
-        debug_print("N%d.LMC%d: dram_tuning_mem_xor: done TEST loop\n", 
+        debug_print("N%d.LMC%d: dram_tuning_mem_xor: done TEST loop\n",
                   node, lmc);
 
     } /* for (int burst = 0; burst < dram_tune_use_bursts; burst++) */
@@ -534,7 +534,7 @@ run_dram_tuning_threads(bdk_node_t node, int num_lmcs, uint64_t bytemask)
         /* Wait for threads to finish, with progress */
         int cur_count;
         uint64_t cur_time;
-        uint64_t period = bdk_clock_get_rate(bdk_numa_local(), BDK_CLOCK_TIME) * TIMEOUT_SECS; // FIXME? 
+        uint64_t period = bdk_clock_get_rate(bdk_numa_local(), BDK_CLOCK_TIME) * TIMEOUT_SECS; // FIXME?
         uint64_t timeout = bdk_clock_get_count(BDK_CLOCK_TIME) + period;
         do {
 //            bdk_thread_yield();        /* FIXME(dhendrix): don't yield... */
@@ -854,7 +854,7 @@ auto_set_dll_offset(bdk_node_t node, int dll_offset_mode,
     } /* for (lmc = 0; lmc < num_lmcs; lmc++) */
 
     // FIXME: only when verbose, or only when there are errors?
-    // run the test one last time 
+    // run the test one last time
     // print whether there are errors or not, but only when verbose...
     bdk_watchdog_poke();
     debug_print("N%d: %s: Start running test one last time\n", node, __FUNCTION__);
@@ -912,7 +912,7 @@ int perform_dll_offset_tuning(bdk_node_t node, int dll_offset_mode, int do_tune)
         loops = strtoul(s, NULL, 0);
     }
 
-    // see if we want to change the granularity of the byte_offset sampling 
+    // see if we want to change the granularity of the byte_offset sampling
     if ((s = getenv("ddr_tune_use_gran"))) {
         dram_tune_use_gran = strtoul(s, NULL, 0);
     }
@@ -1018,7 +1018,7 @@ int perform_dll_offset_tuning(bdk_node_t node, int dll_offset_mode, int do_tune)
     limit_l2_ways(node, ways, ways_print);
 #endif
 
-    // perform cleanup on all active LMCs   
+    // perform cleanup on all active LMCs
     debug_print("N%d: %s: starting LMCs cleanup.\n", node, __FUNCTION__);
     for (lmc = 0; lmc < num_lmcs; lmc++) {
 
@@ -1420,7 +1420,7 @@ hw_assist_test_dll_offset(bdk_node_t node, int dll_offset_mode,
             ddr_print("%5d ", new_best_offset[byte]);
         else
             ddr_print("(byte %d) %5d ", byte, new_best_offset[byte]);
-        
+
 
 #if 1
         // done with testing, load up the best offsets we found...
@@ -1433,7 +1433,7 @@ hw_assist_test_dll_offset(bdk_node_t node, int dll_offset_mode,
     ddr_print("\n");
 
 #if 0
-    // run the test one last time 
+    // run the test one last time
     // print whether there are errors or not, but only when verbose...
     tot_errors = run_test_dram_byte_threads(node, num_lmcs, bytemask);
     printf("N%d.LMC%d: Bytelane %d DLL %s Offset Final Test: errors 0x%x\n",

src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c

@@ -460,7 +460,7 @@ int test_dram_byte_hw(bdk_node_t node, int ddr_interface_num,
 
     // FIXME: K iterations set to 4 for now.
     // FIXME: decrement to increase interations.
-    // FIXME: must be no less than 22 to stay above an LMC hash field. 
+    // FIXME: must be no less than 22 to stay above an LMC hash field.
     int kshift = 26;
     const char *s;
 
@@ -560,8 +560,8 @@ int test_dram_byte_hw(bdk_node_t node, int ddr_interface_num,
         dbtrain_ctl.s.column_a       = col;
         dbtrain_ctl.s.row_a          = row;
         dbtrain_ctl.s.bg             = (bank >> 2) & 3;
-        dbtrain_ctl.s.prank          = (dimm * 2) + prank; // FIXME? 
+        dbtrain_ctl.s.prank          = (dimm * 2) + prank; // FIXME?
-        dbtrain_ctl.s.lrank          = lrank; // FIXME? 
+        dbtrain_ctl.s.lrank          = lrank; // FIXME?
         dbtrain_ctl.s.activate       = (mode == DBTRAIN_DBI);
         dbtrain_ctl.s.write_ena      = 1;
         dbtrain_ctl.s.read_cmd_count = 31; // max count pass 1.x
@@ -892,7 +892,7 @@ int initialize_ddr_clock(bdk_node_t node,
          *
          * 13. DRAM Vref Training for DDR4
 	 *
-         * 14. Final LMC initialization	 
+         * 14. Final LMC initialization
          *
          * CN88XX supports two modes:
          *
@@ -1014,7 +1014,7 @@ int initialize_ddr_clock(bdk_node_t node,
                 ddr_print("LMC0: override DDR_PLL_CTL[dclk_invert] to %d\n",
                           ddr_pll_ctl.cn83xx.dclk_invert);
             }
-            
+
             // always write LMC0 CSR, it must be active
             DRAM_CSR_WRITE(node, BDK_LMCX_DDR_PLL_CTL(0), ddr_pll_ctl.u);
             ddr_print("%-45s : 0x%016llx\n", "LMC0: DDR_PLL_CTL", ddr_pll_ctl.u);
@@ -1719,8 +1719,8 @@ static void dbi_switchover_interface(int node, int lmc)
     read_DAC_DBI_settings(node, lmc, /*DBI*/0, dbi_settings);
 
     display_DAC_DBI_settings(node, lmc, /* DBI */0, ecc_ena, dbi_settings, " INIT");
- 
+
-   /* 2. set DBI related CSRs as below and issue MR write. 
+   /* 2. set DBI related CSRs as below and issue MR write.
          MODEREG_PARAMS3.WR_DBI=1
          MODEREG_PARAMS3.RD_DBI=1
          PHY_CTL.DBI_MODE_ENA=1
@@ -1738,7 +1738,7 @@ static void dbi_switchover_interface(int node, int lmc)
 
     /*
         there are two options for data to send.  Lets start with (1) and could move to (2) in the future:
-        
+
         1) DBTRAIN_CTL[LFSR_PATTERN_SEL] = 0 (or for older chips where this does not exist)
            set data directly in these reigsters.  this will yield a clk/2 pattern:
            GENERAL_PURPOSE0.DATA == 64'h00ff00ff00ff00ff;
@@ -1756,10 +1756,10 @@ static void dbi_switchover_interface(int node, int lmc)
     DRAM_CSR_WRITE(node, BDK_LMCX_GENERAL_PURPOSE1(lmc), dbi_pattern[1]);
     DRAM_CSR_WRITE(node, BDK_LMCX_GENERAL_PURPOSE2(lmc), dbi_pattern[2]);
 
-    /* 
+    /*
       3. adjust cas_latency (only necessary if RD_DBI is set).
          here is my code for doing this:
- 
+
          if (csr_model.MODEREG_PARAMS3.RD_DBI.value == 1) begin
            case (csr_model.MODEREG_PARAMS0.CL.value)
              0,1,2,3,4: csr_model.MODEREG_PARAMS0.CL.value += 2; // CL 9-13 -> 11-15
@@ -1774,7 +1774,7 @@ static void dbi_switchover_interface(int node, int lmc)
              7: csr_model.MODEREG_PARAMS0.CL.value = 14; // 16->19
              8: csr_model.MODEREG_PARAMS0.CL.value = 15; // 18->21
              default:
-             `cn_fatal(("Error mem_cfg (%s) CL (%d) with RD_DBI=1, I am not sure what to do.", 
+             `cn_fatal(("Error mem_cfg (%s) CL (%d) with RD_DBI=1, I am not sure what to do.",
                         mem_cfg, csr_model.MODEREG_PARAMS3.RD_DBI.value))
            endcase
         end
@@ -2056,7 +2056,7 @@ int octeon_ddr_initialize(bdk_node_t node,
 	    continue;
 
     try_again:
-        // if we are LMC0 
+        // if we are LMC0
         if (interface_index == 0) {
             // if we are asking for 100 MHz refclk, we can only get it via alternate, so switch to it
             if (ddr_ref_hertz == 100000000) {

src/vendorcode/cavium/bdk/libdram/libdram.c

@@ -157,13 +157,13 @@ static int bdk_libdram_tune_node(int node)
 
     // Automatically tune the data byte DLL read offsets
     // always done by default, but allow use of HW-assist
-    // NOTE: HW-assist will also tune the ECC byte 
+    // NOTE: HW-assist will also tune the ECC byte
 
     BDK_TRACE(DRAM, "N%d: Starting DLL Read Offset Tuning for LMCs\n", node);
     if (!do_dllro_hw || (lmc_config.s.mode32b != 0)) {
-        errs = perform_dll_offset_tuning(node, 2, /* tune */1); 
+        errs = perform_dll_offset_tuning(node, 2, /* tune */1);
     } else {
-        errs = perform_HW_dll_offset_tuning(node, /* read */2, 0x0A/* all bytelanes */); 
+        errs = perform_HW_dll_offset_tuning(node, /* read */2, 0x0A/* all bytelanes */);
     }
     BDK_TRACE(DRAM, "N%d: Finished DLL Read Offset Tuning for LMCs, %d errors)\n",
               node, errs);
@@ -183,10 +183,10 @@ static int bdk_libdram_tune_node(int node)
     // disabled by default for now, does not seem to be needed much?
     // Automatically tune the ECC byte DLL read offsets
     // FIXME? allow override of the filtering
-    // FIXME? allow programmatic override, not via envvar? 
+    // FIXME? allow programmatic override, not via envvar?
     if (do_eccdll && !do_dllro_hw && (lmc_config.s.mode32b == 0)) { // do not do HW-assist twice for ECC
         BDK_TRACE(DRAM, "N%d: Starting ECC DLL Read Offset Tuning for LMCs\n", node);
-        errs = perform_HW_dll_offset_tuning(node, 2, 8/* ECC bytelane */); 
+        errs = perform_HW_dll_offset_tuning(node, 2, 8/* ECC bytelane */);
         BDK_TRACE(DRAM, "N%d: Finished ECC DLL Read Offset Tuning for LMCs, %d errors\n",
                   node, errs);
         tot_errs += errs;
@@ -207,7 +207,7 @@ static int bdk_libdram_tune_node(int node)
 
 // FIXME: DDR3 is not tuned
 static const uint32_t ddr_speed_filter[2][2][2] = {
-    [IS_DDR4] = { 
+    [IS_DDR4] = {
         [IS_RDIMM] = {
             [IS_1SLOT] =  940,
             [IS_2SLOT] =  800
@@ -473,7 +473,7 @@ int libdram_tune(int node)
         ddr_print("N%d: %s: non-zero node, not worrying about L2C lock status\n", node, __FUNCTION__);
     }
 
-    // make sure to clear memory and any ECC errs when done... 
+    // make sure to clear memory and any ECC errs when done...
     bdk_dram_clear_mem(node);
     bdk_dram_clear_ecc(node);
 
@@ -498,7 +498,7 @@ int libdram_margin_write_voltage(int node)
     // call the margining routine
     tot_errs = perform_margin_write_voltage(node);
 
-    // make sure to clear memory and any ECC errs when done... 
+    // make sure to clear memory and any ECC errs when done...
     bdk_dram_clear_mem(node);
     bdk_dram_clear_ecc(node);
 
@@ -523,7 +523,7 @@ int libdram_margin_read_voltage(int node)
     // call the margining routine
     tot_errs = perform_margin_read_voltage(node);
 
-    // make sure to clear memory and any ECC errs when done... 
+    // make sure to clear memory and any ECC errs when done...
     bdk_dram_clear_mem(node);
     bdk_dram_clear_ecc(node);
 
@@ -548,7 +548,7 @@ int libdram_margin_write_timing(int node)
     // call the tuning routine, tell it we are margining not tuning...
     tot_errs = perform_dll_offset_tuning(node, /* write offsets */1, /* margin */0);
 
-    // make sure to clear memory and any ECC errs when done... 
+    // make sure to clear memory and any ECC errs when done...
     bdk_dram_clear_mem(node);
     bdk_dram_clear_ecc(node);
 
@@ -573,7 +573,7 @@ int libdram_margin_read_timing(int node)
     // call the tuning routine, tell it we are margining not tuning...
     tot_errs = perform_dll_offset_tuning(node, /* read offsets */2, /* margin */0);
 
-    // make sure to clear memory and any ECC errs when done... 
+    // make sure to clear memory and any ECC errs when done...
     bdk_dram_clear_mem(node);
     bdk_dram_clear_ecc(node);
 
@@ -596,7 +596,7 @@ int libdram_margin(int node)
     const char *risk[2] = { "Low Risk", "Needs Review" };
     int l2c_is_locked = bdk_l2c_is_locked(node);
 
-    // for now, no margining on 81xx, until we can reduce the dynamic runtime size... 
+    // for now, no margining on 81xx, until we can reduce the dynamic runtime size...
     if (CAVIUM_IS_MODEL(CAVIUM_CN81XX)) {
         printf("Sorry, margining is not available on 81xx yet...\n");
         return 0;
@@ -637,7 +637,7 @@ int libdram_margin(int node)
       >>> N0: Read Timing Margin   : Low Risk
       >>> N0: Write Timing Margin  : Low Risk
       >>> N0: Read Voltage Margin  : Low Risk
-      >>> N0: Write Voltage Margin : Low Risk  
+      >>> N0: Write Voltage Margin : Low Risk
      */
     printf("  \n");
     printf("-------------------------------------\n");
@@ -647,7 +647,7 @@ int libdram_margin(int node)
     printf("N%d: Write Timing Margin  : %s\n", node, risk[!!ret_wt]);
 
     // these may not have been done due to DDR3 and/or THUNDER pass 1.x
-    // FIXME? would it be better to print an appropriate message here? 
+    // FIXME? would it be better to print an appropriate message here?
     if (ret_rv != -1) printf("N%d: Read Voltage Margin  : %s\n", node, risk[!!ret_rv]);
     if (ret_wv != -1) printf("N%d: Write Voltage Margin : %s\n", node, risk[!!ret_wv]);
 

src/vendorcode/cavium/include/bdk/libbdk-arch/bdk-asm.h

@@ -85,7 +85,7 @@
 #define BDK_CACHE_WB_L2(address) { asm volatile ("sys " BDK_SYS_CVMCACHE_WB_L2 ", %0" : : "r" (address)); } // Push to memory, don't invalidate, don't unlock
 #define BDK_CACHE_LCK_L2(address) { asm volatile ("sys " BDK_SYS_CVMCACHE_LCK_L2 ", %0" : : "r" (address)); } // Lock into L2
 #define BDK_DCACHE_INVALIDATE { asm volatile ("sys " BDK_SYS_CVMCACHE_INVALL_DC ", xzr"); } // Invalidate the entire Dcache on local core
-#define BDK_CACHE_LTG_L2_INDEXED(encoded) { asm volatile ("sys " BDK_SYS_CVMCACHE_LTG_L2_INDEXED ", %0" : : "r" (encoded)); } // Load L2 TAG, index by set/way 
+#define BDK_CACHE_LTG_L2_INDEXED(encoded) { asm volatile ("sys " BDK_SYS_CVMCACHE_LTG_L2_INDEXED ", %0" : : "r" (encoded)); } // Load L2 TAG, index by set/way
 
 #define BDK_STORE_PAIR(ptr, data1, data2) { asm volatile ("stp %x[d1], %x[d2], [%[b]]" : [mem] "+m" (*(__uint128_t*)ptr) : [b] "r" (ptr), [d1] "r" (data1), [d2] "r" (data2)); }
 

src/vendorcode/cavium/include/bdk/libdram/libdram-config.h

@@ -163,7 +163,7 @@ typedef struct {
   	the delays of adjacent bytes.  A value of 0 disables this
   	check.
 
-    .fprch2 Front Porch Enable: When set, the turn-off               
+    .fprch2 Front Porch Enable: When set, the turn-off
         time for the default DDR_DQ/DQS drivers is FPRCH2 CKs earlier.
         00 = 0 CKs
         01 = 1 CKs

src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/FspEas/FspApi.h

@@ -216,7 +216,7 @@ EFI_STATUS
   and defined for each FSP binary. This will be documented in Integration guide with
   each FSP release.
   After FspMemInit completes its execution, it passes the pointer to the HobList and
-  returns to the boot loader from where it was called. BootLoader is responsible to 
+  returns to the boot loader from where it was called. BootLoader is responsible to
   migrate it's stack and data to Memory.
   FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
   complete the silicon initialization and provides bootloader an opportunity to get

src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h

@@ -144,7 +144,7 @@ typedef struct {
   ///
   UINT8   Reserved;
   ///
-  /// Byte 0x0A: FSP producer identification string 
+  /// Byte 0x0A: FSP producer identification string
   ///
   CHAR8   FspProducerId[6];
   ///

src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Library/FspCommonLib.h

@@ -268,7 +268,7 @@ SetFspApiCallingIndex (
 
 /**
   This function gets FSP Phase StatusCode.
-  
+
   @retval StatusCode
 **/
 UINT32

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Arm/ProcessorBind.h

@@ -3,13 +3,13 @@
 
   Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
   Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -35,7 +35,7 @@
 #define UNREACHABLE()
 #endif
 
-#if _MSC_EXTENSIONS 
+#if _MSC_EXTENSIONS
   //
   // use Microsoft* C compiler dependent integer width types
   //
@@ -52,7 +52,7 @@
   typedef signed char         INT8;
 #else
   //
-  // Assume standard ARM alignment. 
+  // Assume standard ARM alignment.
   // Need to check portability of long long
   //
   typedef unsigned long long  UINT64;
@@ -121,7 +121,7 @@ typedef INT32   INTN;
 // use the correct C calling convention. All protocol member functions and
 // EFI intrinsics are required to modify their member functions with EFIAPI.
 //
-#define EFIAPI    
+#define EFIAPI
 
 // When compiling with Clang, we still use GNU as for the assembler, so we still
 // need to define the GCC_ASM* macros.
@@ -142,34 +142,34 @@ typedef INT32   INTN;
 
     #define GCC_ASM_EXPORT(func__)  \
              .global  _CONCATENATE (__USER_LABEL_PREFIX__, func__)    ;\
-             .type ASM_PFX(func__), %function  
+             .type ASM_PFX(func__), %function
 
     #define GCC_ASM_IMPORT(func__)  \
              .extern  _CONCATENATE (__USER_LABEL_PREFIX__, func__)
-             
+
   #else
     //
-    // .type not supported by Apple Xcode tools 
+    // .type not supported by Apple Xcode tools
     //
-    #define INTERWORK_FUNC(func__)  
+    #define INTERWORK_FUNC(func__)
 
     #define GCC_ASM_EXPORT(func__)  \
              .globl  _CONCATENATE (__USER_LABEL_PREFIX__, func__)    \
-  
+
-    #define GCC_ASM_IMPORT(name)  
+    #define GCC_ASM_IMPORT(name)
 
   #endif
 #endif
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On ARM CPU architectures, these two pointer values are the same, 
+  On ARM CPU architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
-  
+
 **/
 #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Base.h

@@ -65,8 +65,8 @@ VERIFY_SIZE_OF (CHAR16, 2);
 
 //
 // The following three enum types are used to verify that the compiler
-// configuration for enum types is compliant with Section 2.3.1 of the 
+// configuration for enum types is compliant with Section 2.3.1 of the
-// UEFI 2.3 Specification. These enum types and enum values are not 
+// UEFI 2.3 Specification. These enum types and enum values are not
 // intended to be used. A prefix of '__' is used avoid conflicts with
 // other types.
 //
@@ -766,7 +766,7 @@ typedef CHAR8 *VA_LIST;
 
   This macro initializes Dest as a copy of Start, as if the VA_START macro had been applied to Dest
   followed by the same sequence of uses of the VA_ARG macro as had previously been used to reach
-  the present state of Start. 
+  the present state of Start.
 
   @param   Dest   VA_LIST used to traverse the list of arguments.
   @param   Start  VA_LIST used to traverse the list of arguments.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ebc/ProcessorBind.h

@@ -5,13 +5,13 @@
   specific functions in this file.
 
 Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -91,7 +91,7 @@ typedef unsigned long         UINTN;
 /// A value of native width with the highest bit set.
 /// Scalable macro to set the most significant bit in a natural number.
 ///
-#define MAX_BIT     (1ULL << (sizeof (INTN) * 8 - 1)) 
+#define MAX_BIT     (1ULL << (sizeof (INTN) * 8 - 1))
 ///
 /// A value of native width with the two highest bits set.
 /// Scalable macro to set the most 2 significant bits in a natural number.
@@ -130,14 +130,14 @@ typedef unsigned long         UINTN;
   /// If EFIAPI is already defined, then we use that definition.
   ///
 #else
-#define EFIAPI    
+#define EFIAPI
 #endif
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On EBC architectures, these two pointer values are the same, 
+  On EBC architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
@@ -148,5 +148,5 @@ typedef unsigned long         UINTN;
 #define __USER_LABEL_PREFIX__
 #endif
 
-#endif 
+#endif
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Acpi.h

@@ -2,17 +2,17 @@
   GUIDs used for ACPI entries in the EFI system table
 
   These GUIDs point the ACPI tables as defined in the ACPI specifications.
-  ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the 
+  ACPI 2.0 specification defines the ACPI 2.0 GUID. UEFI 2.0 defines the
   ACPI 2.0 Table GUID and ACPI Table GUID.
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Apriori.h

@@ -4,13 +4,13 @@
   the dependency grammar.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/AprioriFileName.h

@@ -4,13 +4,13 @@
   volume.
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.
@@ -24,7 +24,7 @@
   { 0x1b45cc0a, 0x156a, 0x428a, { 0x62, 0XAF, 0x49, 0x86, 0x4d, 0xa0, 0xe6, 0xe6 } }
 
 
-///   
+///
 ///  This file must be of type EFI_FV_FILETYPE_FREEFORM and must
 ///  contain a single section of type EFI_SECTION_RAW. For details on
 ///  firmware volumes, firmware file types, and firmware file section
@@ -33,7 +33,7 @@
 typedef struct {
   ///
   /// An array of zero or more EFI_GUID type entries that match the file names of PEIM
-  /// modules in the same Firmware Volume. The maximum number of entries. 
+  /// modules in the same Firmware Volume. The maximum number of entries.
   ///
   EFI_GUID  FileNamesWithinVolume[1];
 } PEI_APRIORI_FILE_CONTENTS;

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/CapsuleReport.h

@@ -1,6 +1,6 @@
 /** @file
   Guid & data structure used for Capsule process result variables
-  
+
   Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -84,14 +84,14 @@ typedef struct {
 
   ///
   /// In case of capsule loaded from disk, the zero-terminated array containing file name of capsule that was processed.
-  /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character 
+  /// In case of capsule submitted directly to UpdateCapsule() there is no file name, and this field is required to contain a single 16-bit zero character
   ///  which is included in VariableTotalSize.
   ///
   /// CHAR16 CapsuleFileName[];
   ///
 
   ///
-  /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol  
+  /// This field will contain a zero-terminated CHAR16 string containing the text representation of the device path of device publishing Firmware Management Protocol
   /// (if present). In case where device path is not present and the target is not otherwise known to firmware, or when payload was blocked by policy, or skipped,
   /// this field is required to contain a single 16-bit zero character which is included in VariableTotalSize.
   ///

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/DebugImageInfoTable.h

@@ -2,13 +2,13 @@
   GUID and related data structures used with the Debug Image Info Table.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID defined in UEFI 2.0 spec.
@@ -35,7 +35,7 @@
 
 typedef struct {
   UINT64                Signature;          ///< A constant UINT64 that has the value EFI_SYSTEM_TABLE_SIGNATURE
-  EFI_PHYSICAL_ADDRESS  EfiSystemTableBase; ///< The physical address of the EFI system table. 
+  EFI_PHYSICAL_ADDRESS  EfiSystemTableBase; ///< The physical address of the EFI system table.
   UINT32                Crc32;              ///< A 32-bit CRC value that is used to verify the EFI_SYSTEM_TABLE_POINTER structure is valid.
 } EFI_SYSTEM_TABLE_POINTER;
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/DxeServices.h

@@ -2,13 +2,13 @@
   GUID used to identify the DXE Services Table
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/EventGroup.h

@@ -2,20 +2,20 @@
   GUIDs for gBS->CreateEventEx Event Groups. Defined in UEFI spec 2.0 and PI 1.2.1.
 
 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
 #ifndef __EVENT_GROUP_GUID__
 #define __EVENT_GROUP_GUID__
 
-                                             
+
 #define EFI_EVENT_GROUP_EXIT_BOOT_SERVICES \
   { 0x27abf055, 0xb1b8, 0x4c26, { 0x80, 0x48, 0x74, 0x8f, 0x37, 0xba, 0xa2, 0xdf } }
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/EventLegacyBios.h

@@ -1,16 +1,16 @@
 /** @file
-  GUID is the name of events used with CreateEventEx in order to be notified 
+  GUID is the name of events used with CreateEventEx in order to be notified
   when the EFI boot manager is about to boot a legacy boot option.
-  Events of this type are notificated just before Int19h is invoked. 
+  Events of this type are notificated just before Int19h is invoked.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileInfo.h

@@ -4,13 +4,13 @@
   This GUID is defined in UEFI specification.
 
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileSystemInfo.h

@@ -4,13 +4,13 @@
   This GUID is defined in UEFI specification.
 
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.                                                        
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FileSystemVolumeLabelInfo.h

@@ -4,13 +4,13 @@
   This GUID is defined in UEFI specification.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareContentsSigned.h

@@ -2,13 +2,13 @@
   GUID is used to define the signed section.
 
   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.2.1.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareFileSystem2.h

@@ -2,13 +2,13 @@
   Guid used to define the Firmware File System 2.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.
@@ -18,18 +18,18 @@
 #ifndef __FIRMWARE_FILE_SYSTEM2_GUID_H__
 #define __FIRMWARE_FILE_SYSTEM2_GUID_H__
 
-/// 
+///
-/// The firmware volume header contains a data field for 
+/// The firmware volume header contains a data field for
 /// the file system GUID
-/// 
+///
 #define EFI_FIRMWARE_FILE_SYSTEM2_GUID \
   { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }
 
 ///
-/// A Volume Top File (VTF) is a file that must be 
+/// A Volume Top File (VTF) is a file that must be
-/// located such that the last byte of the file is 
+/// located such that the last byte of the file is
 /// also the last byte of the firmware volume
-/// 
+///
 #define EFI_FFS_VOLUME_TOP_FILE_GUID \
   { 0x1BA0062E, 0xC779, 0x4582, { 0x85, 0x66, 0x33, 0x6A, 0xE8, 0xF7, 0x8F, 0x9 } }
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/FirmwareFileSystem3.h

@@ -2,13 +2,13 @@
   Guid used to define the Firmware File System 3.
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.
@@ -18,7 +18,7 @@
 #ifndef __FIRMWARE_FILE_SYSTEM3_GUID_H__
 #define __FIRMWARE_FILE_SYSTEM3_GUID_H__
 
-/// 
+///
 /// The firmware volume header contains a data field for the file system GUID
 /// {5473C07A-3DCB-4dca-BD6F-1E9689E7349A}
 ///

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/GlobalVariable.h

@@ -2,13 +2,13 @@
   GUID for EFI (NVRAM) Variables.
 
   Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID defined in UEFI 2.1

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Gpt.h

@@ -1,17 +1,17 @@
 /** @file
   Guids used for the GPT (GUID Partition Table)
 
-  GPT defines a new disk partitioning scheme and also describes 
+  GPT defines a new disk partitioning scheme and also describes
-  usage of the legacy Master Boot Record (MBR) partitioning scheme. 
+  usage of the legacy Master Boot Record (MBR) partitioning scheme.
 
   Copyright (c) 2006 - 2007, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.1 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiFormMapMethodGuid.h

@@ -2,13 +2,13 @@
   Guid used to identify HII FormMap configuration method.
 
   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID defined in UEFI 2.2 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiKeyBoardLayout.h

@@ -1,15 +1,15 @@
 /** @file
 
   HII keyboard layout GUID as defined in UEFI2.1 specification
-  
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.1 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HiiPlatformSetupFormset.h

@@ -1,15 +1,15 @@
 /** @file
-  GUID indicates that the form set contains forms designed to be used 
+  GUID indicates that the form set contains forms designed to be used
   for platform configuration and this form set will be displayed.
 
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID defined in UEFI 2.1.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/HobList.h

@@ -4,13 +4,13 @@
   These GUIDs point the HOB List passed from PEI to DXE.
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID introduced in PI Version 1.0.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/ImageAuthentication.h

@@ -319,7 +319,7 @@ typedef struct {
   /// Zero or more image signatures. If the image contained no signatures,
   /// then this field is empty.
   /// EFI_SIGNATURE_LIST            Signature;
-  /// 
+  ///
 } EFI_IMAGE_EXECUTION_INFO;
 
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MdePkgTokenSpace.h

@@ -1,5 +1,5 @@
 /** @file
-  GUID for MdePkg PCD Token Space 
+  GUID for MdePkg PCD Token Space
 
   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MemoryAllocationHob.h

@@ -2,13 +2,13 @@
   GUIDs for HOBs used in memory allcation
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs introduced in PI Version 1.0.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/MemoryOverwriteControl.h

@@ -1,20 +1,20 @@
 /** @file
-  GUID used for MemoryOverwriteRequestControl UEFI variable defined in 
+  GUID used for MemoryOverwriteRequestControl UEFI variable defined in
   TCG Platform Reset Attack Mitigation Specification 1.00.
   See http://trustedcomputinggroup.org for the latest specification
 
-  The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to 
+  The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to
-  indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon 
+  indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon
-  a restart. The OS loader should not create the variable. Rather, the  firmware is required to create it. 
+  a restart. The OS loader should not create the variable. Rather, the  firmware is required to create it.
 
   Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -27,17 +27,17 @@
   }
 
 ///
-///  Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value. 
+///  Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.
-///  The attributes should be: 
+///  The attributes should be:
-///  EFI_VARIABLE_NON_VOLATILE | 
+///  EFI_VARIABLE_NON_VOLATILE |
-///  EFI_VARIABLE_BOOTSERVICE_ACCESS | 
+///  EFI_VARIABLE_BOOTSERVICE_ACCESS |
-///  EFI_VARIABLE_RUNTIME_ACCESS 
+///  EFI_VARIABLE_RUNTIME_ACCESS
 ///
 #define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"
 
 ///
 /// 0 = Firmware MUST clear the MOR bit
-/// 1 = Firmware MUST set the MOR bit 
+/// 1 = Firmware MUST set the MOR bit
 ///
 #define MOR_CLEAR_MEMORY_BIT_MASK        0x01
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/Mps.h

@@ -4,13 +4,13 @@
   included to support Itanium-based platform power on. So don't use it if you don't have too.
 
   Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/PcAnsi.h

@@ -2,13 +2,13 @@
   Terminal Device Path Vendor Guid.
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.
@@ -42,7 +42,7 @@
   { \
     0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \
   }
-  
+
 #define EFI_SAS_DEVICE_PATH_GUID \
   { \
     0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/SalSystemTable.h

@@ -5,13 +5,13 @@
   the system.
 
   Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.0 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/SmBios.h

@@ -6,13 +6,13 @@
   tables.
 
   Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUIDs defined in UEFI 2.5 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/StatusCodeDataTypeId.h

@@ -11,7 +11,7 @@
   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
-  These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2 
+  These GUIDs and structures are defined in UEFI Platform Initialization Specification 1.2
   Volume 3: Shared Architectural Elements
 
 **/
@@ -38,12 +38,12 @@ typedef enum {
   ///
   EfiStringUnicode,
   ///
-  /// An EFI_STATUS_CODE_STRING_TOKEN representing the string.  The actual 
+  /// An EFI_STATUS_CODE_STRING_TOKEN representing the string.  The actual
   /// string can be obtained by querying the HII Database
   ///
   EfiStringToken
 } EFI_STRING_TYPE;
- 
+
 ///
 /// Specifies the format of the data in EFI_STATUS_CODE_STRING_DATA.String.
 ///
@@ -60,7 +60,7 @@ typedef struct {
   ///
   EFI_STRING_ID   Token;
 } EFI_STATUS_CODE_STRING_TOKEN;
- 
+
 typedef union {
   ///
   /// ASCII formatted string.
@@ -75,11 +75,11 @@ typedef union {
   ///
   EFI_STATUS_CODE_STRING_TOKEN  Hii;
 } EFI_STATUS_CODE_STRING;
- 
+
 ///
-/// This data type defines a string type of extended data. A string can accompany 
+/// This data type defines a string type of extended data. A string can accompany
-/// any status code. The string can provide additional information about the 
+/// any status code. The string can provide additional information about the
-/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure 
+/// status code. The string can be ASCII, Unicode, or a Human Interface Infrastructure
 /// (HII) token/GUID pair.
 ///
 typedef struct {
@@ -89,14 +89,14 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_STRING_DATA) - HeaderSize, and
   /// DataHeader.Type should be
   /// EFI_STATUS_CODE_DATA_TYPE_STRING_GUID.
-  /// 
+  ///
-  EFI_STATUS_CODE_DATA           DataHeader; 
+  EFI_STATUS_CODE_DATA           DataHeader;
   ///
   /// Specifies the format of the data in String.
   ///
   EFI_STRING_TYPE                StringType;
   ///
-  /// A pointer to the extended data. The data follows the format specified by 
+  /// A pointer to the extended data. The data follows the format specified by
   /// StringType.
   ///
   EFI_STATUS_CODE_STRING         String;
@@ -123,7 +123,7 @@ extern EFI_GUID gEfiStatusCodeDataTypeStringGuid;
   { 0x335984bd, 0xe805, 0x409a, { 0xb8, 0xf8, 0xd2, 0x7e, 0xce, 0x5f, 0xf7, 0xa6 } }
 
 ///
-/// Extended data about the device path, which is used for many errors and 
+/// Extended data about the device path, which is used for many errors and
 /// progress codes to point to the device.
 ///
 /// The device path is used to point to the physical device in case there is more than one device
@@ -148,7 +148,7 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA                 DataHeader;
   ///
-  /// The device path to the controller or the hardware device. Note that this parameter is a 
+  /// The device path to the controller or the hardware device. Note that this parameter is a
   /// variable-length device path structure and not a pointer to such a structure. This structure is
   /// populated only if it is a physical device. For virtual devices, the Size field in DataHeader
   /// is set to zero and this field is not populated.
@@ -183,7 +183,7 @@ typedef struct {
 ///
 /// This structure defines extended data describing a PCI resource allocation error.
 ///
-/// @par Note: 
+/// @par Note:
 ///   The following structure contains variable-length fields and cannot be defined as a C-style
 ///   structure.
 ///
@@ -209,7 +209,7 @@ typedef struct {
   ///
   /// DevicePathSize should be zero if it is a virtual device that is not associated with
   /// a device path. Otherwise, this parameter is the length of the variable-length
-  /// DevicePath. 
+  /// DevicePath.
   ///
   UINT16                             DevicePathSize;
   ///
@@ -223,9 +223,9 @@ typedef struct {
   ///
   UINT16                             AllocResSize;
   ///
-  /// The device path to the controller or the hardware device that did not get the requested 
+  /// The device path to the controller or the hardware device that did not get the requested
-  /// resources. Note that this parameter is the variable-length device path structure and not 
+  /// resources. Note that this parameter is the variable-length device path structure and not
-  /// a pointer to this structure. 
+  /// a pointer to this structure.
   ///
   //  EFI_DEVICE_PATH_PROTOCOL       DevicePath;
   ///
@@ -234,7 +234,7 @@ typedef struct {
   ///
   //  UINT8                          ReqRes[];
   ///
-  /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This 
+  /// The allocated resources in the format of an ACPI 2.0 resource descriptor. This
   /// parameter is not a pointer; it is the complete resource descriptor.
   ///
   //  UINT8                          AllocRes[];
@@ -244,7 +244,7 @@ typedef struct {
 /// This structure provides a calculation for base-10 representations.
 ///
 /// Not consistent with PI 1.2 Specification.
-/// This data type is not defined in the PI 1.2 Specification, but is 
+/// This data type is not defined in the PI 1.2 Specification, but is
 /// required by several of the other data structures in this file.
 ///
 typedef struct {
@@ -253,16 +253,16 @@ typedef struct {
   ///
   INT16                            Value;
   ///
-  /// The INT16 number by which to raise the base-2 calculation. 
+  /// The INT16 number by which to raise the base-2 calculation.
   ///
   INT16                            Exponent;
 } EFI_EXP_BASE10_DATA;
 
 ///
-/// This structure provides the voltage at the time of error. It also provides 
+/// This structure provides the voltage at the time of error. It also provides
-/// the threshold value indicating the minimum or maximum voltage that is considered 
+/// the threshold value indicating the minimum or maximum voltage that is considered
-/// an error. If the voltage is less then the threshold, the error indicates that the 
+/// an error. If the voltage is less then the threshold, the error indicates that the
-/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold, 
+/// voltage fell below the minimum acceptable value. If the voltage is greater then the threshold,
 /// the error indicates that the voltage rose above the maximum acceptable value.
 ///
 typedef struct {
@@ -312,7 +312,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_COMPUTING_UNIT_TIMER_EXPIRED_ERROR_DATA) -
   /// HeaderSize, and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -341,11 +341,11 @@ typedef struct {
 ///
 /// This structure defines extended data for processor mismatch errors.
 ///
-/// This provides information to indicate which processors mismatch, and how they mismatch. The 
+/// This provides information to indicate which processors mismatch, and how they mismatch. The
-/// status code contains the instance number of the processor that is in error. This structure's 
+/// status code contains the instance number of the processor that is in error. This structure's
-/// Instance indicates the second processor that does not match. This differentiation allows the 
+/// Instance indicates the second processor that does not match. This differentiation allows the
-/// consumer to determine which two processors do not match. The Attributes indicate what 
+/// consumer to determine which two processors do not match. The Attributes indicate what
-/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be 
+/// mismatch is being reported. Because Attributes is a bit field, more than one mismatch can be
 /// reported with one error code.
 ///
 typedef struct {
@@ -354,23 +354,23 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_ HOST_PROCESSOR_MISMATCH_ERROR_DATA) -
   /// HeaderSize , and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
   /// The unit number of the computing unit that does not match.
-  ///  
+  ///
   UINT32                Instance;
-  /// 
+  ///
-  /// The attributes describing the failure. 
+  /// The attributes describing the failure.
-  ///  
+  ///
   UINT16                Attributes;
 } EFI_HOST_PROCESSOR_MISMATCH_ERROR_DATA;
 
 ///
 /// This structure provides details about the computing unit thermal failure.
 ///
-/// This structure provides the temperature at the time of error. It also provides the threshold value 
+/// This structure provides the temperature at the time of error. It also provides the threshold value
 /// indicating the minimum temperature that is considered an error.
 ///
 typedef struct {
@@ -379,7 +379,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_COMPUTING_UNIT_THERMAL_ERROR_DATA) -
   /// HeaderSize , and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -429,7 +429,7 @@ typedef struct {
 typedef UINT32  EFI_CPU_STATE_CHANGE_CAUSE;
 
 ///
-/// The reasons that the processor is disabled.  
+/// The reasons that the processor is disabled.
 /// Used to fill in EFI_COMPUTING_UNIT_CPU_DISABLED_ERROR_DATA.Cause.
 ///
 ///@{
@@ -447,8 +447,8 @@ typedef UINT32  EFI_CPU_STATE_CHANGE_CAUSE;
 ///
 /// This structure provides information about the disabled computing unit.
 ///
-/// This structure provides details as to why and how the computing unit was disabled. The causes 
+/// This structure provides details as to why and how the computing unit was disabled. The causes
-/// should cover the typical reasons a processor would be disabled. How the processor was disabled is 
+/// should cover the typical reasons a processor would be disabled. How the processor was disabled is
 /// important because there are distinct differences between hardware and software disabling.
 ///
 typedef struct {
@@ -461,12 +461,12 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
-  /// The reason for disabling the processor. 
+  /// The reason for disabling the processor.
-  /// 
+  ///
   UINT32                Cause;
   ///
-  /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables. 
+  /// TRUE if the processor is disabled via software means such as not listing it in the ACPI tables.
-  /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware 
+  /// Such a processor will respond to Interprocessor Interrupts (IPIs). FALSE if the processor is hardware
   /// disabled, which means it is invisible to software and will not respond to IPIs.
   ///
   BOOLEAN               SoftwareDisabled;
@@ -504,8 +504,8 @@ typedef UINT8 EFI_MEMORY_ERROR_OPERATION;
 ///@}
 
 ///
-/// This structure provides specific details about the memory error that was detected. It provides 
+/// This structure provides specific details about the memory error that was detected. It provides
-/// enough information so that consumers can identify the exact failure and provides enough 
+/// enough information so that consumers can identify the exact failure and provides enough
 /// information to enable corrective action if necessary.
 ///
 typedef struct {
@@ -513,7 +513,7 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_MEMORY_EXTENDED_ERROR_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA          DataHeader;
   ///
@@ -521,18 +521,18 @@ typedef struct {
   ///
   EFI_MEMORY_ERROR_GRANULARITY  Granularity;
   ///
-  /// The operation that resulted in the error being detected. 
+  /// The operation that resulted in the error being detected.
   ///
   EFI_MEMORY_ERROR_OPERATION    Operation;
   ///
-  /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with 
+  /// The error syndrome, vendor-specific ECC syndrome, or CRC data associated with
   /// the error.  If unknown, should be initialized to 0.
-  /// Inconsistent with specification here:  
+  /// Inconsistent with specification here:
   /// This field in StatusCodes spec0.9 is defined as UINT32, keep code unchanged.
   ///
   UINTN                         Syndrome;
   ///
-  /// The physical address of the error. 
+  /// The physical address of the error.
   ///
   EFI_PHYSICAL_ADDRESS          Address;
   ///
@@ -543,31 +543,31 @@ typedef struct {
 
 ///
 /// A definition to describe that the operation is performed on multiple devices within the array.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_MULTIPLE_MEMORY_DEVICE_OPERATION 0xfffe
 
 ///
 /// A definition to describe that the operation is performed on all devices within the array.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_ALL_MEMORY_DEVICE_OPERATION 0xffff
 
 ///
 /// A definition to describe that the operation is performed on multiple arrays.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_MULTIPLE_MEMORY_ARRAY_OPERATION 0xfffe
 
 ///
 /// A definition to describe that the operation is performed on all the arrays.
-/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device. 
+/// May be used for EFI_STATUS_CODE_DIMM_NUMBER.Array and EFI_STATUS_CODE_DIMM_NUMBER.Device.
 ///
 #define EFI_ALL_MEMORY_ARRAY_OPERATION 0xffff
 
 ///
-/// This extended data provides some context that consumers can use to locate a DIMM within the 
+/// This extended data provides some context that consumers can use to locate a DIMM within the
-/// overall memory scheme.  
+/// overall memory scheme.
 ///
 /// This extended data provides some context that consumers can use to locate a DIMM within the
 /// overall memory scheme. The Array and Device numbers may indicate a specific DIMM, or they
@@ -595,7 +595,7 @@ typedef struct {
 /// This structure defines extended data describing memory modules that do not match.
 ///
 /// This extended data may be used to convey the specifics of memory modules that do not match.
-/// 
+///
 typedef struct {
   ///
   /// The data header identifying the data. DataHeader.HeaderSize should be
@@ -606,7 +606,7 @@ typedef struct {
   ///
   EFI_STATUS_CODE_DATA         DataHeader;
   ///
-  /// The instance number of the memory module that does not match. 
+  /// The instance number of the memory module that does not match.
   ///
   EFI_STATUS_CODE_DIMM_NUMBER  Instance;
 } EFI_MEMORY_MODULE_MISMATCH_ERROR_DATA;
@@ -614,7 +614,7 @@ typedef struct {
 ///
 /// This structure defines extended data describing a memory range.
 ///
-/// This extended data may be used to convey the specifics of a memory range.  Ranges are specified 
+/// This extended data may be used to convey the specifics of a memory range.  Ranges are specified
 /// with a start address and a length.
 ///
 typedef struct {
@@ -622,11 +622,11 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_MEMORY_RANGE_EXTENDED_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
-  /// The starting address of the memory range. 
+  /// The starting address of the memory range.
   ///
   EFI_PHYSICAL_ADDRESS  Start;
   ///
@@ -647,7 +647,7 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_DEBUG_ASSERT_DATA) - HeaderSize , and
   /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
-  /// 
+  ///
   EFI_STATUS_CODE_DATA         DataHeader;
   ///
   /// The line number of the source file where the fault was generated.
@@ -658,7 +658,7 @@ typedef struct {
   ///
   UINT32                       FileNameSize;
   ///
-  /// A pointer to a NULL-terminated ASCII or Unicode string that represents 
+  /// A pointer to a NULL-terminated ASCII or Unicode string that represents
   /// the file name of the source file where the fault was generated.
   ///
   EFI_STATUS_CODE_STRING_DATA  *FileName;
@@ -691,7 +691,7 @@ typedef union {
   /// EFI_SYSTEM_CONTEXT_X64 is defined in the
   /// EFI_DEBUG_SUPPORT_PROTOCOL in the UEFI Specification.
   ///
-  EFI_SYSTEM_CONTEXT_X64  SystemContextX64; 
+  EFI_SYSTEM_CONTEXT_X64  SystemContextX64;
   ///
   /// The context of the ARM processor when the exception was generated. Type
   /// EFI_SYSTEM_CONTEXT_ARM is defined in the
@@ -713,11 +713,11 @@ typedef struct {
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_STATUS_CODE_EXCEP_EXTENDED_DATA) - HeaderSize,
   /// and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA                  DataHeader;
   ///
-  /// The system context. 
+  /// The system context.
   ///
   EFI_STATUS_CODE_EXCEP_SYSTEM_CONTEXT  Context;
 } EFI_STATUS_CODE_EXCEP_EXTENDED_DATA;
@@ -729,33 +729,33 @@ typedef struct {
 /// the UEFI Driver Binding Protocol.
 ///
 typedef struct {
-  /// 
+  ///
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_STATUS_CODE_START_EXTENDED_DATA) - HeaderSize,
   /// and DataHeader.Type should be
-  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA           DataHeader;
   ///
-  /// The controller handle. 
+  /// The controller handle.
   ///
   EFI_HANDLE                     ControllerHandle;
   ///
   /// The driver binding handle.
   ///
   EFI_HANDLE                     DriverBindingHandle;
-  /// 
+  ///
-  /// The size of the RemainingDevicePath. It is zero if the Start() function is 
+  /// The size of the RemainingDevicePath. It is zero if the Start() function is
   /// called with RemainingDevicePath = NULL.  The UEFI Specification allows
   /// that the Start() function of bus drivers can be called in this way.
   ///
   UINT16                         DevicePathSize;
   ///
-  /// Matches the RemainingDevicePath parameter being passed to the Start() function. 
+  /// Matches the RemainingDevicePath parameter being passed to the Start() function.
-  /// Note that this parameter is the variable-length device path and not a pointer 
+  /// Note that this parameter is the variable-length device path and not a pointer
   /// to the device path.
-  ///  
+  ///
   //  EFI_DEVICE_PATH_PROTOCOL   RemainingDevicePath;
 } EFI_STATUS_CODE_START_EXTENDED_DATA;
 
@@ -771,7 +771,7 @@ typedef struct {
   /// The data header identifying the data. DataHeader.HeaderSize should be
   /// sizeof (EFI_STATUS_CODE_DATA), DataHeader.Size should be
   /// sizeof (EFI_LEGACY_OPROM_EXTENDED_DATA) - HeaderSize, and
-  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.  
+  /// DataHeader.Type should be EFI_STATUS_CODE_SPECIFIC_DATA_GUID.
   ///
   EFI_STATUS_CODE_DATA  DataHeader;
   ///
@@ -779,7 +779,7 @@ typedef struct {
   ///
   EFI_HANDLE            DeviceHandle;
   ///
-  /// The base address of the shadowed legacy ROM image.  May or may not point to the shadow RAM area. 
+  /// The base address of the shadowed legacy ROM image.  May or may not point to the shadow RAM area.
   ///
   EFI_PHYSICAL_ADDRESS  RomImageBase;
 } EFI_LEGACY_OPROM_EXTENDED_DATA;

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Guid/VectorHandoffTable.h

@@ -1,15 +1,15 @@
 /** @file
   GUID for system configuration table entry that points to the table
-  in case an entity in DXE wishes to update/change the vector table contents. 
+  in case an entity in DXE wishes to update/change the vector table contents.
 
   Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
   @par Revision Reference:
   GUID defined in PI 1.2.1 spec.

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ia32/ProcessorBind.h

@@ -2,13 +2,13 @@
   Processor or Compiler specific defines and types for IA-32 architecture.
 
 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -100,17 +100,17 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 //
 
 //
-// This warning is for potentially uninitialized local variable, and it may cause false 
+// This warning is for potentially uninitialized local variable, and it may cause false
 // positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4701 )
-  
+
 //
-// This warning is for potentially uninitialized local pointer variable, and it may cause 
+// This warning is for potentially uninitialized local pointer variable, and it may cause
 // false positive issues in VS2013 and VS2015 build
 //
 #pragma warning ( disable : 4703 )
-  
+
 #endif
 
 #endif
@@ -168,7 +168,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   /// 1-byte signed value.
   ///
   typedef signed char         INT8;
-#else  
+#else
   ///
   /// 8-byte unsigned value.
   ///
@@ -275,17 +275,17 @@ typedef INT32   INTN;
 #elif defined(_MSC_EXTENSIONS)
   ///
   /// Microsoft* compiler specific method for EFIAPI calling convention.
-  /// 
+  ///
-  #define EFIAPI __cdecl  
+  #define EFIAPI __cdecl
 #elif defined(__GNUC__)
   ///
   /// GCC specific method for EFIAPI calling convention.
-  /// 
+  ///
-  #define EFIAPI __attribute__((cdecl))  
+  #define EFIAPI __attribute__((cdecl))
 #else
   ///
   /// The default for a non Microsoft* or GCC compiler is to assume the EFI ABI
-  /// is the standard. 
+  /// is the standard.
   ///
   #define EFIAPI
 #endif
@@ -300,13 +300,13 @@ typedef INT32   INTN;
 
 /**
   Return the pointer to the first instruction of a function given a function pointer.
-  On IA-32 CPU architectures, these two pointer values are the same, 
+  On IA-32 CPU architectures, these two pointer values are the same,
   so the implementation of this macro is very simple.
-  
+
   @param  FunctionPointer   A pointer to a function.
 
   @return The pointer to the first instruction of a function given a function pointer.
-  
+
 **/
 #define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi10.h

@@ -1,14 +1,14 @@
-/** @file   
+/** @file
   ACPI 1.0b definitions from the ACPI Specification, revision 1.0b
 
 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_1_0_H_
@@ -357,7 +357,7 @@ typedef struct {
 #define   EFI_ACPI_DMA_SPEED_TYPE_A                     0x20
 #define   EFI_ACPI_DMA_SPEED_TYPE_B                     0x40
 #define   EFI_ACPI_DMA_SPEED_TYPE_F                     0x60
-                                               
+
 #define EFI_ACPI_DMA_BUS_MASTER_MASK                    0x04
 #define   EFI_ACPI_DMA_BUS_MASTER                       0x04
 
@@ -403,7 +403,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi20.h

@@ -1,14 +1,14 @@
-/** @file   
+/** @file
   ACPI 2.0 definitions from the ACPI Specification, revision 2.0
 
   Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_2_0_H_
@@ -103,7 +103,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -114,7 +114,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi30.h

@@ -1,14 +1,14 @@
-/** @file   
+/** @file
   ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006
 
   Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_3_0_H_
@@ -128,7 +128,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -139,7 +139,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -597,7 +597,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi40.h

@@ -1,14 +1,14 @@
-/** @file   
+/** @file
   ACPI 4.0 definitions from the ACPI Specification Revision 4.0a April 5, 2010
 
   Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_4_0_H_
@@ -86,7 +86,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -97,7 +97,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1132,7 +1132,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_4_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi50.h

@@ -1,15 +1,15 @@
-/** @file   
+/** @file
   ACPI 5.0 definitions from the ACPI Specification Revision 5.0a November 13, 2013.
 
   Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
   Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_5_0_H_
@@ -208,7 +208,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -219,7 +219,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1876,7 +1876,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_5_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi51.h

@@ -1,16 +1,16 @@
-/** @file   
+/** @file
   ACPI 5.1 definitions from the ACPI Specification Revision 5.1 Errata B January, 2016.
 
   Copyright (c) 2014 Hewlett-Packard Development Company, L.P.<BR>
   Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2015 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_5_1_H_
@@ -89,7 +89,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -100,7 +100,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -1874,7 +1874,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_5_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -1892,7 +1892,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_5_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi60.h

@@ -1,15 +1,15 @@
-/** @file   
+/** @file
   ACPI 6.0 definitions from the ACPI Specification Revision 6.0 Errata A January, 2016.
 
   Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
   (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_6_0_H_
@@ -88,7 +88,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -99,7 +99,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -2063,7 +2063,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_6_0_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2125,7 +2125,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_6_0_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Acpi61.h

@@ -1,15 +1,15 @@
-/** @file   
+/** @file
   ACPI 6.1 definitions from the ACPI Specification Revision 6.1 January, 2016.
 
   Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ACPI_6_1_H_
@@ -88,7 +88,7 @@ typedef struct {
 
 //
 // Root System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT32 table pointers.
 //
 
@@ -99,7 +99,7 @@ typedef struct {
 
 //
 // Extended System Description Table
-// No definition needed as it is a common description table header, the same with 
+// No definition needed as it is a common description table header, the same with
 // EFI_ACPI_DESCRIPTION_HEADER, followed by a variable number of UINT64 table pointers.
 //
 
@@ -2095,7 +2095,7 @@ typedef struct {
   UINT8                                    CommandComplete:1;
   UINT8                                    SciDoorbell:1;
   UINT8                                    Error:1;
-  UINT8                                    PlatformNotification:1;  
+  UINT8                                    PlatformNotification:1;
   UINT8                                    Reserved:4;
   UINT8                                    Reserved1;
 } EFI_ACPI_6_1_PCCT_GENERIC_SHARED_MEMORY_REGION_STATUS;
@@ -2157,7 +2157,7 @@ typedef struct {
 ///
 /// "RSD PTR " Root System Description Pointer
 ///
-#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ') 
+#define EFI_ACPI_6_1_ROOT_SYSTEM_DESCRIPTION_POINTER_SIGNATURE  SIGNATURE_64('R', 'S', 'D', ' ', 'P', 'T', 'R', ' ')
 
 ///
 /// "APIC" Multiple APIC Description Table

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/AlertStandardFormatTable.h

@@ -1,14 +1,14 @@
-/** @file   
+/** @file
   ACPI Alert Standard Format Description Table ASF! as described in the ASF2.0 Specification
 
   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _ALERT_STANDARD_FORMAT_TABLE_H_
@@ -31,7 +31,7 @@ typedef struct {
 } EFI_ACPI_ASF_RECORD_HEADER;
 
 ///
-/// This structure contains information that identifies the system's type 
+/// This structure contains information that identifies the system's type
 /// and configuration
 ///
 typedef struct {
@@ -84,7 +84,7 @@ typedef struct {
   UINT8                                DeviceAddress;
   UINT8                                Command;
   UINT8                                DataValue;
-} EFI_ACPI_ASF_CONTROLDATA;       
+} EFI_ACPI_ASF_CONTROLDATA;
 
 ///
 /// Alert Remote Control System Actions

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Atapi.h

@@ -3,12 +3,12 @@
   that dealing with ATA/ATAPI interface.
 
 Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
@@ -21,59 +21,59 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 ///
 /// ATA5_IDENTIFY_DATA is defined in ATA-5.
 /// (This structure is provided mainly for backward-compatibility support.
-/// Old drivers may reference fields that are marked "obsolete" in 
+/// Old drivers may reference fields that are marked "obsolete" in
-/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.) 
+/// ATA_IDENTIFY_DATA, which currently conforms to ATA-8.)
 ///
-typedef struct {    
+typedef struct {
   UINT16  config;             ///< General Configuration.
   UINT16  cylinders;          ///< Number of Cylinders.
-  UINT16  reserved_2; 
+  UINT16  reserved_2;
-  UINT16  heads;              ///< Number of logical heads. 
+  UINT16  heads;              ///< Number of logical heads.
-  UINT16  vendor_data1; 
+  UINT16  vendor_data1;
-  UINT16  vendor_data2; 
+  UINT16  vendor_data2;
-  UINT16  sectors_per_track; 
+  UINT16  sectors_per_track;
-  UINT16  vendor_specific_7_9[3]; 
+  UINT16  vendor_specific_7_9[3];
-  CHAR8   SerialNo[20];       ///< ASCII  
+  CHAR8   SerialNo[20];       ///< ASCII
-  UINT16  vendor_specific_20_21[2];  
+  UINT16  vendor_specific_20_21[2];
-  UINT16  ecc_bytes_available;    
+  UINT16  ecc_bytes_available;
-  CHAR8   FirmwareVer[8];     ///< ASCII  
+  CHAR8   FirmwareVer[8];     ///< ASCII
-  CHAR8   ModelName[40];      ///< ASCII    
+  CHAR8   ModelName[40];      ///< ASCII
-  UINT16  multi_sector_cmd_max_sct_cnt; 
+  UINT16  multi_sector_cmd_max_sct_cnt;
-  UINT16  reserved_48; 
+  UINT16  reserved_48;
-  UINT16  capabilities; 
+  UINT16  capabilities;
-  UINT16  reserved_50;     
+  UINT16  reserved_50;
-  UINT16  pio_cycle_timing;    
+  UINT16  pio_cycle_timing;
-  UINT16  reserved_52;             
+  UINT16  reserved_52;
-  UINT16  field_validity;     
+  UINT16  field_validity;
-  UINT16  current_cylinders; 
+  UINT16  current_cylinders;
-  UINT16  current_heads; 
+  UINT16  current_heads;
-  UINT16  current_sectors;    
+  UINT16  current_sectors;
-  UINT16  CurrentCapacityLsb; 
+  UINT16  CurrentCapacityLsb;
-  UINT16  CurrentCapacityMsb;     
+  UINT16  CurrentCapacityMsb;
-  UINT16  reserved_59;     
+  UINT16  reserved_59;
-  UINT16  user_addressable_sectors_lo; 
+  UINT16  user_addressable_sectors_lo;
-  UINT16  user_addressable_sectors_hi; 
+  UINT16  user_addressable_sectors_hi;
-  UINT16  reserved_62;     
+  UINT16  reserved_62;
-  UINT16  multi_word_dma_mode;    
+  UINT16  multi_word_dma_mode;
-  UINT16  advanced_pio_modes; 
+  UINT16  advanced_pio_modes;
-  UINT16  min_multi_word_dma_cycle_time; 
+  UINT16  min_multi_word_dma_cycle_time;
-  UINT16  rec_multi_word_dma_cycle_time; 
+  UINT16  rec_multi_word_dma_cycle_time;
-  UINT16  min_pio_cycle_time_without_flow_control; 
+  UINT16  min_pio_cycle_time_without_flow_control;
-  UINT16  min_pio_cycle_time_with_flow_control; 
+  UINT16  min_pio_cycle_time_with_flow_control;
-  UINT16  reserved_69_79[11];     
+  UINT16  reserved_69_79[11];
-  UINT16  major_version_no; 
+  UINT16  major_version_no;
-  UINT16  minor_version_no; 
+  UINT16  minor_version_no;
-  UINT16  command_set_supported_82;    ///< word 82 
+  UINT16  command_set_supported_82;    ///< word 82
-  UINT16  command_set_supported_83;    ///< word 83 
+  UINT16  command_set_supported_83;    ///< word 83
-  UINT16  command_set_feature_extn;    ///< word 84 
+  UINT16  command_set_feature_extn;    ///< word 84
-  UINT16  command_set_feature_enb_85;  ///< word 85 
+  UINT16  command_set_feature_enb_85;  ///< word 85
-  UINT16  command_set_feature_enb_86;  ///< word 86 
+  UINT16  command_set_feature_enb_86;  ///< word 86
-  UINT16  command_set_feature_default; ///< word 87 
+  UINT16  command_set_feature_default; ///< word 87
-  UINT16  ultra_dma_mode;              ///< word 88 
+  UINT16  ultra_dma_mode;              ///< word 88
-  UINT16  reserved_89_127[39]; 
+  UINT16  reserved_89_127[39];
-  UINT16  security_status; 
+  UINT16  security_status;
-  UINT16  vendor_data_129_159[31]; 
+  UINT16  vendor_data_129_159[31];
-  UINT16  reserved_160_255[96]; 
+  UINT16  reserved_160_255[96];
 } ATA5_IDENTIFY_DATA;
 
 ///
@@ -86,50 +86,50 @@ typedef struct {
   UINT16  obsolete_1;
   UINT16  specific_config;                         ///< Specific Configuration.
   UINT16  obsolete_3;
-  UINT16  retired_4_5[2]; 
+  UINT16  retired_4_5[2];
   UINT16  obsolete_6;
   UINT16  cfa_reserved_7_8[2];
-  UINT16  retired_9; 
+  UINT16  retired_9;
   CHAR8   SerialNo[20];                            ///< word 10~19
-  UINT16  retired_20_21[2];  
+  UINT16  retired_20_21[2];
-  UINT16  obsolete_22;    
+  UINT16  obsolete_22;
   CHAR8   FirmwareVer[8];                          ///< word 23~26
   CHAR8   ModelName[40];                           ///< word 27~46
   UINT16  multi_sector_cmd_max_sct_cnt;
-  UINT16  trusted_computing_support; 
+  UINT16  trusted_computing_support;
   UINT16  capabilities_49;
   UINT16  capabilities_50;
-  UINT16  obsolete_51_52[2];           
+  UINT16  obsolete_51_52[2];
-  UINT16  field_validity;     
+  UINT16  field_validity;
-  UINT16  obsolete_54_58[5];     
+  UINT16  obsolete_54_58[5];
   UINT16  multi_sector_setting;
-  UINT16  user_addressable_sectors_lo; 
+  UINT16  user_addressable_sectors_lo;
-  UINT16  user_addressable_sectors_hi; 
+  UINT16  user_addressable_sectors_hi;
-  UINT16  obsolete_62;     
+  UINT16  obsolete_62;
-  UINT16  multi_word_dma_mode;    
+  UINT16  multi_word_dma_mode;
-  UINT16  advanced_pio_modes; 
+  UINT16  advanced_pio_modes;
-  UINT16  min_multi_word_dma_cycle_time; 
+  UINT16  min_multi_word_dma_cycle_time;
-  UINT16  rec_multi_word_dma_cycle_time; 
+  UINT16  rec_multi_word_dma_cycle_time;
-  UINT16  min_pio_cycle_time_without_flow_control; 
+  UINT16  min_pio_cycle_time_without_flow_control;
-  UINT16  min_pio_cycle_time_with_flow_control; 
+  UINT16  min_pio_cycle_time_with_flow_control;
   UINT16  additional_supported;                    ///< word 69
   UINT16  reserved_70;
   UINT16  reserved_71_74[4];                       ///< Reserved for IDENTIFY PACKET DEVICE cmd.
-  UINT16  queue_depth;     
+  UINT16  queue_depth;
   UINT16  serial_ata_capabilities;
   UINT16  reserved_77;                             ///< Reserved for Serial ATA
   UINT16  serial_ata_features_supported;
   UINT16  serial_ata_features_enabled;
-  UINT16  major_version_no; 
+  UINT16  major_version_no;
-  UINT16  minor_version_no; 
+  UINT16  minor_version_no;
   UINT16  command_set_supported_82;                ///< word 82
   UINT16  command_set_supported_83;                ///< word 83
   UINT16  command_set_feature_extn;                ///< word 84
   UINT16  command_set_feature_enb_85;              ///< word 85
   UINT16  command_set_feature_enb_86;              ///< word 86
   UINT16  command_set_feature_default;             ///< word 87
-  UINT16  ultra_dma_mode;                          ///< word 88 
+  UINT16  ultra_dma_mode;                          ///< word 88
-  UINT16  time_for_security_erase_unit; 
+  UINT16  time_for_security_erase_unit;
   UINT16  time_for_enhanced_security_erase_unit;
   UINT16  advanced_power_management_level;
   UINT16  master_password_identifier;
@@ -154,7 +154,7 @@ typedef struct {
   UINT16  reserved_121_126[6];
   UINT16  obsolete_127;
   UINT16  security_status;                         ///< word 128
-  UINT16  vendor_specific_129_159[31]; 
+  UINT16  vendor_specific_129_159[31];
   UINT16  cfa_power_mode;                          ///< word 160
   UINT16  reserved_for_compactflash_161_167[7];
   UINT16  device_nominal_form_factor;
@@ -239,7 +239,7 @@ typedef struct {
   UINT16  reserved_95_107[13];
   UINT16  world_wide_name[4];                      ///< word 108~111
   UINT16  reserved_for_128bit_wwn_112_115[4];
-  UINT16  reserved_116_118[3];  
+  UINT16  reserved_116_118[3];
   UINT16  command_and_feature_sets_supported;      ///< word 119
   UINT16  command_and_feature_sets_supported_enabled;
   UINT16  reserved_121_124[4];
@@ -458,7 +458,7 @@ typedef struct {
 
 ///
 /// ATAPI_PACKET_COMMAND is not defined in the ATA specification.
-/// We add it here for the convenience of ATA/ATAPI module writers. 
+/// We add it here for the convenience of ATA/ATAPI module writers.
 ///
 typedef union {
   UINT16                    Data16[6];
@@ -477,7 +477,7 @@ typedef union {
 #define ATAPI_MAX_DMA_CMD_SECTORS                       0x100
 
 //  ATA/ATAPI Signature equates
-#define ATA_SIGNATURE                                   0x0101       ///< defined in ACS-3  
+#define ATA_SIGNATURE                                   0x0101       ///< defined in ACS-3
 #define ATAPI_SIGNATURE                                 0xeb14       ///< defined in ACS-3
 #define ATAPI_SIGNATURE_32                              0xeb140101   ///< defined in ACS-3
 
@@ -521,11 +521,11 @@ typedef union {
 #define ATA_CMD_GET_CONFIGURATION                       0x46   ///< defined in ATAPI Multimedia Devices
    #define ATA_GCCD_RT_FIELD_VALUE_ALL                      0x00   ///< defined in ATAPI Multimedia Devices
    #define ATA_GCCD_RT_FIELD_VALUE_CURRENT                  0x01   ///< defined in ATAPI Multimedia Devices
-   #define ATA_GCCD_RT_FIELD_VALUE_SINGLE                   0x02   ///< defined in ATAPI Multimedia Devices 
+   #define ATA_GCCD_RT_FIELD_VALUE_SINGLE                   0x02   ///< defined in ATAPI Multimedia Devices
-   #define ATA_GCCD_RT_FIELD_VALUE_RESERVED                 0x03   ///< defined in ATAPI Multimedia Devices 
+   #define ATA_GCCD_RT_FIELD_VALUE_RESERVED                 0x03   ///< defined in ATAPI Multimedia Devices
-   
+
    #define ATA_FEATURE_LIST_PROFILE_LIST                    0x0000   ///< defined in ATAPI Multimedia Devices
-   #define ATA_FEATURE_LIST_CORE                            0x0001   ///< defined in ATAPI Multimedia Devices   
+   #define ATA_FEATURE_LIST_CORE                            0x0001   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_MORPHING                        0x0002   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_REMOVEABLE_MEDIUM               0x0003   ///< defined in ATAPI Multimedia Devices
    #define ATA_FEATURE_LIST_WRITE_PROTECT                   0x0004   ///< defined in ATAPI Multimedia Devices
@@ -549,33 +549,33 @@ typedef union {
 //
 #define ATA_CMD_IDENTIFY_DRIVE                          0xec   ///< defined from ATA-3
 #define ATA_CMD_READ_BUFFER                             0xe4   ///< defined from ATA-1
-#define ATA_CMD_READ_SECTORS                            0x20   ///< defined from ATA-1     
+#define ATA_CMD_READ_SECTORS                            0x20   ///< defined from ATA-1
 #define ATA_CMD_READ_SECTORS_WITH_RETRY                 0x21   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_LONG                               0x22   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_LONG_WITH_RETRY                    0x23   ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_READ_SECTORS_EXT                        0x24   ///< defined from ATA-6
-#define ATA_CMD_READ_MULTIPLE                           0xc4   ///< defined in ACS-3  
+#define ATA_CMD_READ_MULTIPLE                           0xc4   ///< defined in ACS-3
-#define ATA_CMD_READ_MULTIPLE_EXT                       0x29   ///< defined in ACS-3  
+#define ATA_CMD_READ_MULTIPLE_EXT                       0x29   ///< defined in ACS-3
-#define ATA_CMD_READ_LOG_EXT                            0x2f   ///< defined in ACS-3  
+#define ATA_CMD_READ_LOG_EXT                            0x2f   ///< defined in ACS-3
 
 //
 // Class 2: PIO Data-Out Commands
 //
 #define ATA_CMD_FORMAT_TRACK                            0x50  ///< defined from ATA-1, obsoleted from ATA-4
-#define ATA_CMD_WRITE_BUFFER                            0xe8  ///< defined from ATA-1  
+#define ATA_CMD_WRITE_BUFFER                            0xe8  ///< defined from ATA-1
 #define ATA_CMD_WRITE_SECTORS                           0x30  ///< defined from ATA-1
 #define ATA_CMD_WRITE_SECTORS_WITH_RETRY                0x31  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_LONG                              0x32  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_LONG_WITH_RETRY                   0x33  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_VERIFY                            0x3c  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_WRITE_SECTORS_EXT                       0x34  ///< defined from ATA-6
-#define ATA_CMD_WRITE_MULTIPLE                          0xc5  ///< defined in ACS-3  
+#define ATA_CMD_WRITE_MULTIPLE                          0xc5  ///< defined in ACS-3
-#define ATA_CMD_WRITE_MULTIPLE_EXT                      0x39  ///< defined in ACS-3  
+#define ATA_CMD_WRITE_MULTIPLE_EXT                      0x39  ///< defined in ACS-3
 
 //
 // Class 3 No Data Command
 //
-#define ATA_CMD_ACK_MEDIA_CHANGE                        0xdb  ///< defined from ATA-1, obsoleted from ATA-5 
+#define ATA_CMD_ACK_MEDIA_CHANGE                        0xdb  ///< defined from ATA-1, obsoleted from ATA-5
 #define ATA_CMD_BOOT_POST_BOOT                          0xdc  ///< defined from ATA-1, obsoleted from ATA-3
 #define ATA_CMD_BOOT_PRE_BOOT                           0xdd  ///< defined from ATA-1, obsoleted from ATA-3
 #define ATA_CMD_CHECK_POWER_MODE                        0x98  ///< defined from ATA-1, obsoleted from ATA-4
@@ -599,39 +599,39 @@ typedef union {
 #define ATA_CMD_STANDBY_ALIAS                           0xe2  ///< defined from ATA-1
 #define ATA_CMD_STANDBY_IMMEDIATE                       0x94  ///< defined from ATA-1, obsoleted from ATA-4
 #define ATA_CMD_STANDBY_IMMEDIATE_ALIAS                 0xe0  ///< defined from ATA-1
-#define ATA_CMD_SLEEP                                   0xe6  ///< defined in ACS-3  
+#define ATA_CMD_SLEEP                                   0xe6  ///< defined in ACS-3
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS                 0xf8  ///< defined in ATA-6  
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS                 0xf8  ///< defined in ATA-6
-#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT             0x27  ///< defined in ATA-6  
+#define ATA_CMD_READ_NATIVE_MAX_ADDRESS_EXT             0x27  ///< defined in ATA-6
 
 //
 // Set Features Sub Command
 //
-#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE             0x02   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_VOLATILE_WRITE_CACHE             0x02   ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_TRANSFER_MODE                       0x03   ///< defined in ACS-3 
+#define ATA_SUB_CMD_SET_TRANSFER_MODE                       0x03   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_APM                              0x05   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_APM                              0x05   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_PUIS                             0x06   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_PUIS                             0x06   ///< defined in ACS-3
-#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP                  0x07   ///< defined in ACS-3 
+#define ATA_SUB_CMD_PUIS_SET_DEVICE_SPINUP                  0x07   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY                0x0b   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_WRITE_READ_VERIFY                0x0b   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_SATA_FEATURE                     0x10   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_SATA_FEATURE                     0x10   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION       0x31   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_MEDIA_STATUS_NOTIFICATION       0x31   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL                0x41   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_FREE_FALL_CONTROL                0x41   ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE              0x42   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_ENABLE              0x42   ///< defined in ACS-3
-#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES     0x43   ///< defined in ACS-3 
+#define ATA_SUB_CMD_SET_MAX_HOST_INTERFACE_SECTOR_TIMES     0x43   ///< defined in ACS-3
-#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS               0x4a   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EXTENDED_POWER_CONDITIONS               0x4a   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD                 0x55   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_READ_LOOK_AHEAD                 0x55   ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE                      0x63   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EN_DIS_DSN_FEATURE                      0x63   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS     0x66   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_REVERT_TO_POWER_ON_DEFAULTS     0x66   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE            0x82   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_VOLATILE_WRITE_CACHE            0x82   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_APM                             0x85   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_APM                             0x85   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_PUIS                            0x86   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_PUIS                            0x86   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY               0x8b   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_WRITE_READ_VERIFY               0x8b   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_SATA_FEATURE                    0x90   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_SATA_FEATURE                    0x90   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION        0x95   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_MEDIA_STATUS_NOTIFICATION        0x95   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD                  0xaa   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_READ_LOOK_AHEAD                  0xaa   ///< defined in ACS-3
-#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL               0xc1   ///< defined in ACS-3 
+#define ATA_SUB_CMD_DISABLE_FREE_FALL_CONTROL               0xc1   ///< defined in ACS-3
-#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE             0xc2   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ACOUSTIC_MANAGEMENT_DISABLE             0xc2   ///< defined in ACS-3
-#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING             0xc3   ///< defined in ACS-3 
+#define ATA_SUB_CMD_EN_DIS_SENSE_DATA_REPORTING             0xc3   ///< defined in ACS-3
-#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS      0xcc   ///< defined in ACS-3 
+#define ATA_SUB_CMD_ENABLE_REVERT_TO_POWER_ON_DEFAULTS      0xcc   ///< defined in ACS-3
 
 //
 // S.M.A.R.T
@@ -640,13 +640,13 @@ typedef union {
 #define ATA_CONSTANT_C2                                 0xc2  ///< reserved
 #define ATA_CONSTANT_4F                                 0x4f  ///< reserved
 
-#define ATA_SMART_READ_DATA                             0xd0   ///< defined in ACS-3 
+#define ATA_SMART_READ_DATA                             0xd0   ///< defined in ACS-3
 
-#define ATA_SMART_AUTOSAVE                              0xd2  ///< defined in ACS-3 
+#define ATA_SMART_AUTOSAVE                              0xd2  ///< defined in ACS-3
     #define ATA_AUTOSAVE_DISABLE_ATTR                       0x00
     #define ATA_AUTOSAVE_ENABLE_ATTR                        0xf1
 
-#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE             0xd4  ///< defined in ACS-3 
+#define ATA_SMART_EXECUTE_OFFLINE_IMMEDIATE             0xd4  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_ROUTINE               0x00  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_SHORT_SELFTEST        0x01  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_OFFLINE_EXTENDED_SELFTEST     0x02  ///< defined in ACS-3
@@ -658,25 +658,25 @@ typedef union {
     #define ATA_EXECUTE_SMART_CAPTIVE_CONVEYANCE_SELFTEST   0x83  ///< defined in ACS-3
     #define ATA_EXECUTE_SMART_CAPTIVE_SELECTIVE_SELFTEST    0x84  ///< defined in ACS-3
 
-#define ATA_SMART_READLOG                               0xd5  ///< defined in ACS-3 
+#define ATA_SMART_READLOG                               0xd5  ///< defined in ACS-3
-#define ATA_SMART_WRITELOG                              0xd6  ///< defined in ACS-3 
+#define ATA_SMART_WRITELOG                              0xd6  ///< defined in ACS-3
 #define ATA_SMART_ENABLE_OPERATION                      0xd8  ///< reserved
-#define ATA_SMART_DISABLE_OPERATION                     0xd9  ///< defined in ACS-3 
+#define ATA_SMART_DISABLE_OPERATION                     0xd9  ///< defined in ACS-3
 #define ATA_SMART_RETURN_STATUS                         0xda  ///< defined from ATA-3
 
-#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE              0xc24f  ///< defined in ACS-3 
+#define ATA_SMART_THRESHOLD_NOT_EXCEEDED_VALUE              0xc24f  ///< defined in ACS-3
-#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE                  0x2cf4  ///< defined in ACS-3 
+#define ATA_SMART_THRESHOLD_EXCEEDED_VALUE                  0x2cf4  ///< defined in ACS-3
 
 // SMART Log Definitions
-#define ATA_SMART_LOG_DIRECTORY                             0x00  ///< defined in ACS-3 
+#define ATA_SMART_LOG_DIRECTORY                             0x00  ///< defined in ACS-3
-#define ATA_SMART_SUM_SMART_ERROR_LOG                       0x01  ///< defined in ACS-3 
+#define ATA_SMART_SUM_SMART_ERROR_LOG                       0x01  ///< defined in ACS-3
-#define ATA_SMART_COMP_SMART_ERROR_LOG                      0x02  ///< defined in ACS-3 
+#define ATA_SMART_COMP_SMART_ERROR_LOG                      0x02  ///< defined in ACS-3
-#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG                  0x03  ///< defined in ACS-3 
+#define ATA_SMART_EXT_COMP_SMART_ERROR_LOG                  0x03  ///< defined in ACS-3
-#define ATA_SMART_SMART_SELFTEST_LOG                        0x06  ///< defined in ACS-3 
+#define ATA_SMART_SMART_SELFTEST_LOG                        0x06  ///< defined in ACS-3
-#define ATA_SMART_EXT_SMART_SELFTEST_LOG                    0x07  ///< defined in ACS-3 
+#define ATA_SMART_EXT_SMART_SELFTEST_LOG                    0x07  ///< defined in ACS-3
-#define ATA_SMART_SELECTIVE_SELFTEST_LOG                    0x09  ///< defined in ACS-3 
+#define ATA_SMART_SELECTIVE_SELFTEST_LOG                    0x09  ///< defined in ACS-3
-#define ATA_SMART_HOST_VENDOR_SPECIFIC                      0x80  ///< defined in ACS-3 
+#define ATA_SMART_HOST_VENDOR_SPECIFIC                      0x80  ///< defined in ACS-3
-#define ATA_SMART_DEVICE_VENDOR_SPECIFIC                    0xa0  ///< defined in ACS-3 
+#define ATA_SMART_DEVICE_VENDOR_SPECIFIC                    0xa0  ///< defined in ACS-3
 
 //
 // Class 4: DMA Command
@@ -687,18 +687,18 @@ typedef union {
 #define ATA_CMD_WRITE_DMA                               0xca   ///< defined from ATA-1
 #define ATA_CMD_WRITE_DMA_WITH_RETRY                    0xcb   ///< defined from ATA-1, obsoleted from ATA-
 #define ATA_CMD_WRITE_DMA_EXT                           0x35   ///< defined from ATA-6
-  
+
 //
 //  ATA Security commands
 //
-#define ATA_CMD_SECURITY_SET_PASSWORD                   0xf1  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_SET_PASSWORD                   0xf1  ///< defined in ACS-3
-#define ATA_CMD_SECURITY_UNLOCK                         0xf2  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_UNLOCK                         0xf2  ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_PREPARE                  0xf3  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_ERASE_PREPARE                  0xf3  ///< defined in ACS-3
-#define ATA_CMD_SECURITY_ERASE_UNIT                     0xf4  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_ERASE_UNIT                     0xf4  ///< defined in ACS-3
-#define ATA_CMD_SECURITY_FREEZE_LOCK                    0xf5  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_FREEZE_LOCK                    0xf5  ///< defined in ACS-3
-#define ATA_CMD_SECURITY_DISABLE_PASSWORD               0xf6  ///< defined in ACS-3 
+#define ATA_CMD_SECURITY_DISABLE_PASSWORD               0xf6  ///< defined in ACS-3
 
-#define ATA_SECURITY_BUFFER_LENGTH                          512  ///< defined in ACS-3 
+#define ATA_SECURITY_BUFFER_LENGTH                          512  ///< defined in ACS-3
 
 //
 //  ATA Device Config Overlay
@@ -712,19 +712,19 @@ typedef union {
 //
 //  ATA Trusted Computing Feature Set Commands
 //
-#define ATA_CMD_TRUSTED_NON_DATA                        0x5b  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_NON_DATA                        0x5b  ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE                         0x5c  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_RECEIVE                         0x5c  ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_RECEIVE_DMA                     0x5d  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_RECEIVE_DMA                     0x5d  ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND                            0x5e  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_SEND                            0x5e  ///< defined in ACS-3
-#define ATA_CMD_TRUSTED_SEND_DMA                        0x5f  ///< defined in ACS-3 
+#define ATA_CMD_TRUSTED_SEND_DMA                        0x5f  ///< defined in ACS-3
 
 //
 //  ATA Trusted Receive Fields
 //
-#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION     0x00  ///< defined in ACS-3 
+#define ATA_TR_RETURN_SECURITY_PROTOCOL_INFORMATION     0x00  ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED         0xec  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_JEDEC_RESERVED         0xec  ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED        0xed  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_SDCARD_RESERVED        0xed  ///< defined in ACS-3
-#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED      0xee  ///< defined in ACS-3 
+#define ATA_TR_SECURITY_PROTOCOL_IEEE1667_RESERVED      0xee  ///< defined in ACS-3
 
 //
 //  Equates used for Acoustic Flags
@@ -732,18 +732,18 @@ typedef union {
 #define ATA_ACOUSTIC_LEVEL_BYPASS                       0xff   ///< defined from ATA-6
 #define ATA_ACOUSTIC_LEVEL_MAXIMUM_PERFORMANCE          0xfe   ///< defined from ATA-6
 #define ATA_ACOUSTIC_LEVEL_QUIET                        0x80   ///< defined from ATA-6
-    	
+
 //
 //  Equates used for DiPM Support
 //
-#define ATA_CMD_DIPM_SUB                                0x03   // defined in ACS-3 : Count value in SetFeature identification : 03h  Device-initiated interface power state transitions 
+#define ATA_CMD_DIPM_SUB                                0x03   // defined in ACS-3 : Count value in SetFeature identification : 03h  Device-initiated interface power state transitions
-    #define ATA_DIPM_ENABLE                                 0x10   // defined in ACS-3 
+    #define ATA_DIPM_ENABLE                                 0x10   // defined in ACS-3
-    #define ATA_DIPM_DISABLE                                0x90   // defined in ACS-3 
+    #define ATA_DIPM_DISABLE                                0x90   // defined in ACS-3
 
 //
 //  Equates used for DevSleep Support
 //
-#define ATA_CMD_DEVSLEEP_SUB                            0x09   // defined in SATA 3.2 Gold Spec :  Count value in SetFeature identification : 09h  Device Sleep 
+#define ATA_CMD_DEVSLEEP_SUB                            0x09   // defined in SATA 3.2 Gold Spec :  Count value in SetFeature identification : 09h  Device Sleep
     #define ATA_DEVSLEEP_ENABLE                             0x10   // defined in SATA 3.2 Gold Spec
     #define ATA_DEVSLEEP_DISABLE                            0x90   // defined in SATA 3.2 Gold Spec
 
@@ -765,7 +765,7 @@ typedef union {
 /// Default content of device control register, disable INT,
 /// Bit3 is set to 1 according ATA-1
 ///
-#define ATA_DEFAULT_CTL                                 (0x0a)  
+#define ATA_DEFAULT_CTL                                 (0x0a)
 ///
 /// Default context of Device/Head Register,
 /// Bit7 and Bit5 are set to 1 for back-compatibilities.
@@ -778,9 +778,9 @@ typedef union {
 
 //
 // Sense Key, Additional Sense Codes and Additional Sense Code Qualifier
-// defined in MultiMedia Commands (MMC, MMC-2) 
+// defined in MultiMedia Commands (MMC, MMC-2)
 //
-// Sense Key 
+// Sense Key
 //
 #define ATA_SK_NO_SENSE                                 (0x0)
 #define ATA_SK_RECOVERY_ERROR                           (0x1)
@@ -825,7 +825,7 @@ typedef union {
 
 //
 // Error Register
-//  
+//
 #define ATA_ERRREG_BBK                                  BIT7  ///< Bad block detected      defined from ATA-1, obsoleted from ATA-2
 #define ATA_ERRREG_UNC                                  BIT6  ///< Uncorrectable Data      defined from ATA-1, obsoleted from ATA-4
 #define ATA_ERRREG_MC                                   BIT5  ///< Media Change            defined from ATA-1, obsoleted from ATA-4

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPort2Table.h

@@ -1,5 +1,5 @@
-/** @file   
+/** @file
-  ACPI debug port 2 table definition, defined at 
+  ACPI debug port 2 table definition, defined at
   Microsoft DebugPort2Specification.
 
   Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/DebugPortTable.h

@@ -1,5 +1,5 @@
-/** @file   
+/** @file
-  ACPI debug port table definition, defined at 
+  ACPI debug port table definition, defined at
   Microsoft DebugPortSpecification.
 
   Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/ElTorito.h

@@ -1,18 +1,18 @@
 /** @file
-  ElTorito Partitions Format Definition. 
+  ElTorito Partitions Format Definition.
-  This file includes some defintions from 
+  This file includes some defintions from
   1. "El Torito" Bootable CD-ROM Format Specification, Version 1.0.
-  2. Volume and File Structure of CDROM for Information Interchange, 
+  2. Volume and File Structure of CDROM for Information Interchange,
      Standard ECMA-119. (IS0 9660)
 
 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
+This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License         
+are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at        
+which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php                                            
+http://opensource.org/licenses/bsd-license.php
-                                                                                          
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -57,13 +57,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 #pragma pack(1)
 
-/// 
+///
 /// CD-ROM Volume Descriptor
-/// 
+///
-typedef union { 
+typedef union {
   struct {
-    UINT8   Type;     
+    UINT8   Type;
-    CHAR8   Id[5];           ///< "CD001"    
+    CHAR8   Id[5];           ///< "CD001"
     CHAR8   Reserved[82];
   } Unknown;
 
@@ -72,29 +72,29 @@ typedef union {
   ///
   struct {
     UINT8   Type;            ///< Must be 0
-    CHAR8   Id[5];           ///< "CD001" 
+    CHAR8   Id[5];           ///< "CD001"
-    UINT8   Version;         ///< Must be 1 
+    UINT8   Version;         ///< Must be 1
-    CHAR8   SystemId[32];    ///< "EL TORITO SPECIFICATION" 
+    CHAR8   SystemId[32];    ///< "EL TORITO SPECIFICATION"
-    CHAR8   Unused[32];      ///< Must be 0 
+    CHAR8   Unused[32];      ///< Must be 0
     UINT8   EltCatalog[4];   ///< Absolute pointer to first sector of Boot Catalog
     CHAR8   Unused2[13];     ///< Must be 0
   } BootRecordVolume;
- 
+
   ///
   /// Primary Volumn Descriptor, defined in ISO 9660.
   ///
   struct {
-    UINT8   Type; 
+    UINT8   Type;
     CHAR8   Id[5];           ///< "CD001"
-    UINT8   Version; 
+    UINT8   Version;
     UINT8   Unused;          ///< Must be 0
-    CHAR8   SystemId[32];    
+    CHAR8   SystemId[32];
-    CHAR8   VolumeId[32];    
+    CHAR8   VolumeId[32];
-    UINT8   Unused2[8];      ///< Must be 0 
+    UINT8   Unused2[8];      ///< Must be 0
     UINT32  VolSpaceSize[2]; ///< the number of Logical Blocks
   } PrimaryVolume;
 
-} CDROM_VOLUME_DESCRIPTOR; 
+} CDROM_VOLUME_DESCRIPTOR;
 
 ///
 /// Catalog Entry

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/HighPrecisionEventTimerTable.h

@@ -1,15 +1,15 @@
 /** @file
   ACPI high precision event timer table definition, at www.intel.com
   Specification name is IA-PC HPET (High Precision Event Timers) Specification.
-    
-  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _HIGH_PRECISION_EVENT_TIMER_TABLE_H_

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Hsti.h

@@ -25,8 +25,8 @@
 
 #define PLATFORM_SECURITY_ROLE_PLATFORM_REFERENCE 0x00000001  // IHV
 #define PLATFORM_SECURITY_ROLE_PLATFORM_IBV       0x00000002
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM    0x00000003 
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_OEM    0x00000003
-#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM    0x00000004  
+#define PLATFORM_SECURITY_ROLE_IMPLEMENTOR_ODM    0x00000004
 
 typedef struct {
   //

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Http11.h

@@ -1,8 +1,8 @@
 /** @file
-  Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616    
+  Hypertext Transfer Protocol -- HTTP/1.1 Standard definitions, from RFC 2616
+
+  This file contains common HTTP 1.1 definitions from RFC 2616
 
-  This file contains common HTTP 1.1 definitions from RFC 2616 
-   
   (C) Copyright 2015-2016 Hewlett Packard Enterprise Development LP<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -20,7 +20,7 @@
 
 ///
 /// HTTP Version (currently HTTP 1.1)
-/// 
+///
 /// The version of an HTTP message is indicated by an HTTP-Version field
 /// in the first line of the message.
 ///
@@ -28,7 +28,7 @@
 
 ///
 /// HTTP Request Method definitions
-/// 
+///
 /// The Method  token indicates the method to be performed on the
 /// resource identified by the Request-URI. The method is case-sensitive.
 ///
@@ -50,27 +50,27 @@
 
 ///
 /// Accept Request Header
-/// The Accept request-header field can be used to specify certain media types which are 
+/// The Accept request-header field can be used to specify certain media types which are
-/// acceptable for the response. Accept headers can be used to indicate that the request 
+/// acceptable for the response. Accept headers can be used to indicate that the request
-/// is specifically limited to a small set of desired types, as in the case of a request 
+/// is specifically limited to a small set of desired types, as in the case of a request
 /// for an in-line image.
 ///
 #define HTTP_HEADER_ACCEPT             "Accept"
 
 
-/// 
+///
 /// Accept-Charset Request Header
-/// The Accept-Charset request-header field can be used to indicate what character sets 
+/// The Accept-Charset request-header field can be used to indicate what character sets
-/// are acceptable for the response. This field allows clients capable of understanding 
+/// are acceptable for the response. This field allows clients capable of understanding
-/// more comprehensive or special-purpose character sets to signal that capability to a 
+/// more comprehensive or special-purpose character sets to signal that capability to a
 /// server which is capable of representing documents in those character sets.
 ///
 #define HTTP_HEADER_ACCEPT_CHARSET     "Accept-Charset"
 
-/// 
+///
 /// Accept-Language Request Header
-/// The Accept-Language request-header field is similar to Accept, 
+/// The Accept-Language request-header field is similar to Accept,
-/// but restricts the set of natural languages that are preferred 
+/// but restricts the set of natural languages that are preferred
 /// as a response to the request.
 ///
 #define HTTP_HEADER_ACCEPT_LANGUAGE    "Accept-Language"
@@ -83,39 +83,39 @@
 #define HTTP_HEADER_ACCEPT_RANGES      "Accept-Ranges"
 
 
-/// 
+///
 /// Accept-Encoding Request Header
-/// The Accept-Encoding request-header field is similar to Accept, 
+/// The Accept-Encoding request-header field is similar to Accept,
 /// but restricts the content-codings that are acceptable in the response.
 ///
 #define HTTP_HEADER_ACCEPT_ENCODING    "Accept-Encoding"
 
 ///
 /// Content-Encoding Header
-/// The Content-Encoding entity-header field is used as a modifier to the media-type. 
+/// The Content-Encoding entity-header field is used as a modifier to the media-type.
-/// When present, its value indicates what additional content codings have been applied 
+/// When present, its value indicates what additional content codings have been applied
-/// to the entity-body, and thus what decoding mechanisms must be applied in order to 
+/// to the entity-body, and thus what decoding mechanisms must be applied in order to
-/// obtain the media-type referenced by the Content-Type header field. Content-Encoding 
+/// obtain the media-type referenced by the Content-Type header field. Content-Encoding
-/// is primarily used to allow a document to be compressed without losing the identity 
+/// is primarily used to allow a document to be compressed without losing the identity
 /// of its underlying media type.
 ///
 #define HTTP_HEADER_CONTENT_ENCODING   "Content-Encoding"
 
-/// 
+///
 /// HTTP Content-Encoding Compression types
 ///
 
 #define HTTP_CONTENT_ENCODING_IDENTITY "identity"  /// No transformation is used. This is the default value for content coding.
 #define HTTP_CONTENT_ENCODING_GZIP     "gzip"      /// Content-Encoding: GNU zip format (described in RFC 1952).
-#define HTTP_CONTENT_ENCODING_COMPRESS "compress"  /// encoding format produced by the common UNIX file compression program "compress". 
+#define HTTP_CONTENT_ENCODING_COMPRESS "compress"  /// encoding format produced by the common UNIX file compression program "compress".
-#define HTTP_CONTENT_ENCODING_DEFLATE  "deflate"   /// The "zlib" format defined in RFC 1950 in combination with the "deflate" 
+#define HTTP_CONTENT_ENCODING_DEFLATE  "deflate"   /// The "zlib" format defined in RFC 1950 in combination with the "deflate"
                                                    /// compression mechanism described in RFC 1951.
 
 
 ///
 /// Content-Type Header
-/// The Content-Type entity-header field indicates the media type of the entity-body sent to 
+/// The Content-Type entity-header field indicates the media type of the entity-body sent to
-/// the recipient or, in the case of the HEAD method, the media type that would have been sent 
+/// the recipient or, in the case of the HEAD method, the media type that would have been sent
 /// had the request been a GET.
 ///
 #define HTTP_HEADER_CONTENT_TYPE       "Content-Type"
@@ -124,12 +124,12 @@
 //
 #define HTTP_CONTENT_TYPE_APP_JSON          "application/json"
 #define HTTP_CONTENT_TYPE_APP_OCTET_STREAM  "application/octet-stream"
-                                           
+
 #define HTTP_CONTENT_TYPE_TEXT_HTML         "text/html"
 #define HTTP_CONTENT_TYPE_TEXT_PLAIN        "text/plain"
 #define HTTP_CONTENT_TYPE_TEXT_CSS          "text/css"
 #define HTTP_CONTENT_TYPE_TEXT_XML          "text/xml"
-                                           
+
 #define HTTP_CONTENT_TYPE_IMAGE_GIF         "image/gif"
 #define HTTP_CONTENT_TYPE_IMAGE_JPEG        "image/jpeg"
 #define HTTP_CONTENT_TYPE_IMAGE_PNG         "image/png"
@@ -138,17 +138,17 @@
 
 ///
 /// Content-Length Header
-/// The Content-Length entity-header field indicates the size of the entity-body, 
+/// The Content-Length entity-header field indicates the size of the entity-body,
-/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD 
+/// in decimal number of OCTETs, sent to the recipient or, in the case of the HEAD
 /// method, the size of the entity-body that would have been sent had the request been a GET.
 ///
 #define HTTP_HEADER_CONTENT_LENGTH     "Content-Length"
-                                                                                                              
+
 ///
 /// Transfer-Encoding Header
-/// The Transfer-Encoding general-header field indicates what (if any) type of transformation 
+/// The Transfer-Encoding general-header field indicates what (if any) type of transformation
-/// has been applied to the message body in order to safely transfer it between the sender 
+/// has been applied to the message body in order to safely transfer it between the sender
-/// and the recipient. This differs from the content-coding in that the transfer-coding 
+/// and the recipient. This differs from the content-coding in that the transfer-coding
 /// is a property of the message, not of the entity.
 ///
 #define HTTP_HEADER_TRANSFER_ENCODING  "Transfer-Encoding"
@@ -156,14 +156,14 @@
 
 ///
 /// User Agent Request Header
-/// 
+///
-/// The User-Agent request-header field contains information about the user agent originating 
+/// The User-Agent request-header field contains information about the user agent originating
-/// the request. This is for statistical purposes, the tracing of protocol violations, and 
+/// the request. This is for statistical purposes, the tracing of protocol violations, and
-/// automated recognition of user agents for the sake of tailoring responses to avoid 
+/// automated recognition of user agents for the sake of tailoring responses to avoid
-/// particular user agent limitations. User agents SHOULD include this field with requests. 
+/// particular user agent limitations. User agents SHOULD include this field with requests.
-/// The field can contain multiple product tokens and comments identifying the agent and any 
+/// The field can contain multiple product tokens and comments identifying the agent and any
-/// subproducts which form a significant part of the user agent. 
+/// subproducts which form a significant part of the user agent.
-/// By convention, the product tokens are listed in order of their significance for 
+/// By convention, the product tokens are listed in order of their significance for
 /// identifying the application.
 ///
 #define HTTP_HEADER_USER_AGENT         "User-Agent"
@@ -171,49 +171,49 @@
 ///
 /// Host Request Header
 ///
-/// The Host request-header field specifies the Internet host and port number of the resource 
+/// The Host request-header field specifies the Internet host and port number of the resource
-/// being requested, as obtained from the original URI given by the user or referring resource 
+/// being requested, as obtained from the original URI given by the user or referring resource
 ///
 #define HTTP_HEADER_HOST              "Host"
 
 ///
 /// Location Response Header
-/// 
+///
-/// The Location response-header field is used to redirect the recipient to a location other than 
+/// The Location response-header field is used to redirect the recipient to a location other than
-/// the Request-URI for completion of the request or identification of a new resource. 
+/// the Request-URI for completion of the request or identification of a new resource.
-/// For 201 (Created) responses, the Location is that of the new resource which was created by 
+/// For 201 (Created) responses, the Location is that of the new resource which was created by
-/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for 
+/// the request. For 3xx responses, the location SHOULD indicate the server's preferred URI for
 /// automatic redirection to the resource. The field value consists of a single absolute URI.
 ///
 #define HTTP_HEADER_LOCATION           "Location"
 
 ///
 /// The If-Match request-header field is used with a method to make it conditional.
-/// A client that has one or more entities previously obtained from the resource 
+/// A client that has one or more entities previously obtained from the resource
-/// can verify that one of those entities is current by including a list of their 
+/// can verify that one of those entities is current by including a list of their
-/// associated entity tags in the If-Match header field. 
+/// associated entity tags in the If-Match header field.
-/// The purpose of this feature is to allow efficient updates of cached information 
+/// The purpose of this feature is to allow efficient updates of cached information
-/// with a minimum amount of transaction overhead. It is also used, on updating requests, 
+/// with a minimum amount of transaction overhead. It is also used, on updating requests,
-/// to prevent inadvertent modification of the wrong version of a resource. 
+/// to prevent inadvertent modification of the wrong version of a resource.
 /// As a special case, the value "*" matches any current entity of the resource.
 ///
 #define HTTP_HEADER_IF_MATCH          "If-Match"
 
 
 ///
-/// The If-None-Match request-header field is used with a method to make it conditional. 
+/// The If-None-Match request-header field is used with a method to make it conditional.
-/// A client that has one or more entities previously obtained from the resource can verify 
+/// A client that has one or more entities previously obtained from the resource can verify
-/// that none of those entities is current by including a list of their associated entity 
+/// that none of those entities is current by including a list of their associated entity
-/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient 
+/// tags in the If-None-Match header field. The purpose of this feature is to allow efficient
-/// updates of cached information with a minimum amount of transaction overhead. It is also used 
+/// updates of cached information with a minimum amount of transaction overhead. It is also used
-/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the 
+/// to prevent a method (e.g. PUT) from inadvertently modifying an existing resource when the
 /// client believes that the resource does not exist.
 ///
 #define HTTP_HEADER_IF_NONE_MATCH     "If-None-Match"
 
 
 
-/// 
+///
 /// Authorization Request Header
 /// The Authorization field value consists of credentials
 /// containing the authentication information of the user agent for
@@ -223,8 +223,8 @@
 
 ///
 /// ETAG Response Header
-/// The ETag response-header field provides the current value of the entity tag 
+/// The ETag response-header field provides the current value of the entity tag
-/// for the requested variant. 
+/// for the requested variant.
 ///
 #define HTTP_HEADER_ETAG              "ETag"
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/IScsiBootFirmwareTable.h

@@ -1,15 +1,15 @@
 /** @file
   The definition for iSCSI Boot Firmware Table, it's defined in Microsoft's
-  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification. 
+  iSCSI Boot Firmware Table(iBFT) as Defined in ACPI 3.0b Specification.
-  
-  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -58,7 +58,7 @@ typedef struct {
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_HEADER;
 
 ///
-/// Common Header of Boot Firmware Table Structure 
+/// Common Header of Boot Firmware Table Structure
 ///
 typedef struct {
   UINT8   StructureId;
@@ -78,7 +78,7 @@ typedef struct {
   UINT16                                               NIC0Offset;
   UINT16                                               Target0Offset;
   UINT16                                               NIC1Offset;
-  UINT16                                               Target1Offset;  
+  UINT16                                               Target1Offset;
 } EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE;
 
 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_CONTROL_STRUCTURE_VERSION              0x1
@@ -100,8 +100,8 @@ typedef struct {
 
 #define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_VERSION             0x1
 
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0 
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BLOCK_VALID    BIT0
-#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1 
+#define EFI_ACPI_ISCSI_BOOT_FIRMWARE_TABLE_INITIATOR_STRUCTURE_FLAG_BOOT_SELECTED  BIT1
 
 ///
 /// NIC Structure

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/LegacyBiosMpTable.h

@@ -1,17 +1,17 @@
 /** @file
   Defives data structures per MultiProcessor Specification Ver 1.4.
-  
+
-  The MultiProcessor Specification defines an enhancement to the standard 
+  The MultiProcessor Specification defines an enhancement to the standard
   to which PC manufacturers design DOS-compatible systems.
 
 Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
+This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License         
+are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at        
+which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php                                            
+http://opensource.org/licenses/bsd-license.php
-                                                                                          
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Mbr.h

@@ -2,13 +2,13 @@
   Legacy Master Boot Record Format Definition.
 
 Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials                          
+This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License         
+are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at        
+which accompanies this distribution.  The full text of the license may be found at
 http://opensource.org/licenses/bsd-license.php
-                                                                                          
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h

@@ -1,16 +1,16 @@
 /** @file
-  ACPI memory mapped configuration space access table definition, defined at 
+  ACPI memory mapped configuration space access table definition, defined at
   in the PCI Firmware Specification, version 3.0.
   Specification is available at http://www.pcisig.com.
-    
-  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
-  are licensed and made available under the terms and conditions of the BSD License         
-  which accompanies this distribution.  The full text of the license may be found at        
-  http://opensource.org/licenses/bsd-license.php                                            
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 **/
 
 #ifndef _MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_H_
@@ -35,7 +35,7 @@ typedef struct {
 } EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE;
 
 ///
-/// MCFG Table header definition.  The rest of the table 
+/// MCFG Table header definition.  The rest of the table
 /// must be defined in a platform specific manner.
 ///
 typedef struct {

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/MemoryOverwriteRequestControlLock.h

@@ -1,5 +1,5 @@
 /** @file
-  Support for Microsoft Secure MOR implementation, defined at 
+  Support for Microsoft Secure MOR implementation, defined at
   Microsoft Secure MOR implementation.
   https://msdn.microsoft.com/en-us/library/windows/hardware/mt270973(v=vs.85).aspx
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pal.h

@@ -2,13 +2,13 @@
   Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -1152,7 +1152,7 @@ typedef struct {
                                                 ///< be enabled or disabled by
                                                 ///< PAL_PROC_SET_FEATURES. The
                                                 ///< corresponding argument is ignored.
-                                                
+
   UINT64  NoPresentPmi:1;                       ///< Bit37, No INIT, PMI, and LINT pins
                                                 ///< present. Denotes the absence of INIT,
                                                 ///< PMI, LINT0 and LINT1 pins on the
@@ -1163,7 +1163,7 @@ typedef struct {
                                                 ///< enabled or disabled by
                                                 ///< PAL_PROC_SET_FEATURES. The corresponding
                                                 ///< argument is ignored.
-                                                
+
   UINT64  NoSimpleImpInUndefinedIns:1;          ///< Bit38, No Simple
                                                 ///< implementation of
                                                 ///< unimplemented instruction
@@ -1432,7 +1432,7 @@ typedef struct {
                                                 ///<   bit has no effect if BERR
                                                 ///<   signalling is disabled. (See
                                                 ///<   PAL_BUS_GET/SET_FEATURES)
-                                                
+
   UINT64  EnableBerrPromotion:1;                ///< Bit63. Enable BERR promotion. When
                                                 ///<   1, the Bus Error (BERR) signal is
                                                 ///<   promoted to the Bus Initialization
@@ -1757,15 +1757,15 @@ typedef struct {
 
   UINT64  FailedInInsCache:1;           ///< Bit11, Failure located in the
                                         ///< instruction cache.
-                                        
+
   UINT64  Mesi:3;                       ///< Bit14:12,  0 - cache line is invalid. 1 - cache
                                         ///< line is held shared. 2 - cache line is held
                                         ///< exclusive. 3 - cache line is modified. All other
                                         ///< values are reserved.
-                                        
+
   UINT64  MesiIsValid:1;                ///< Bit15, The mesi field in the cache_check
                                         ///< parameter is valid.
-                                        
+
   UINT64  FailedWay:5;                  ///< Bit20:16, Failure located in the way of
                                         ///< the cache indicated by this value.
 
@@ -2288,7 +2288,7 @@ typedef struct {
                                 ///<   ignored or generate an illegal argument in
                                 ///<   procedure calls if the caller sets these
                                 ///<   bits.
-                                
+
   UINT64  ControlSupport:1;     ///< This bit defines if an implementation
                                 ///<  supports control of the PAL self-tests
                                 ///<  via the self-test control word. If

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci.h

@@ -2,13 +2,13 @@
   Support for the latest PCI standard.
 
 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.                                            
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci22.h

@@ -9,13 +9,13 @@
 
   Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
   Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -116,8 +116,8 @@ typedef union {
   PCI_TYPE01  Bridge;
 } PCI_TYPE_GENERIC;
 
-/// 
+///
-/// CardBus Conroller Configuration Space, 
+/// CardBus Conroller Configuration Space,
 /// Section 4.5.1, PC Card Standard. 8.0
 ///
 typedef struct {
@@ -158,7 +158,7 @@ typedef struct {
 #define   PCI_CLASS_MASS_STORAGE_OTHER  0x80
 
 #define PCI_CLASS_NETWORK             0x02
-#define   PCI_CLASS_NETWORK_ETHERNET    0x00  
+#define   PCI_CLASS_NETWORK_ETHERNET    0x00
 #define   PCI_CLASS_NETWORK_TOKENRING   0x01
 #define   PCI_CLASS_NETWORK_FDDI        0x02
 #define   PCI_CLASS_NETWORK_ATM         0x03
@@ -171,7 +171,7 @@ typedef struct {
 #define     PCI_IF_VGA_8514               0x01
 #define   PCI_CLASS_DISPLAY_XGA         0x01
 #define   PCI_CLASS_DISPLAY_3D          0x02
-#define   PCI_CLASS_DISPLAY_OTHER       0x80  
+#define   PCI_CLASS_DISPLAY_OTHER       0x80
 
 #define PCI_CLASS_MEDIA               0x04
 #define   PCI_CLASS_MEDIA_VIDEO         0x00
@@ -199,7 +199,7 @@ typedef struct {
 #define   PCI_CLASS_BRIDGE_OTHER        0x80
 #define   PCI_CLASS_BRIDGE_ISA_PDECODE  0x80
 
-#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers 
+#define PCI_CLASS_SCC                 0x07  ///< Simple communications controllers
 #define   PCI_SUBCLASS_SERIAL           0x00
 #define     PCI_IF_GENERIC_XT             0x00
 #define     PCI_IF_16450                  0x01
@@ -228,8 +228,8 @@ typedef struct {
 #define     PCI_IF_8259_PIC               0x00
 #define     PCI_IF_ISA_PIC                0x01
 #define     PCI_IF_EISA_PIC               0x02
-#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.  
+#define     PCI_IF_APIC_CONTROLLER        0x10  ///< I/O APIC interrupt controller , 32 bye none-prefectable memory.
-#define     PCI_IF_APIC_CONTROLLER2       0x20 
+#define     PCI_IF_APIC_CONTROLLER2       0x20
 #define   PCI_SUBCLASS_DMA              0x01
 #define     PCI_IF_8237_DMA               0x00
 #define     PCI_IF_ISA_DMA                0x01
@@ -297,25 +297,25 @@ typedef struct {
 
 #define PCI_SECURITY_CONTROLLER       0x10   ///< Encryption and decryption controller
 #define   PCI_SUBCLASS_NET_COMPUT       0x00
-#define   PCI_SUBCLASS_ENTERTAINMENT    0x10 
+#define   PCI_SUBCLASS_ENTERTAINMENT    0x10
 #define   PCI_SUBCLASS_SECURITY_OTHER   0x80
 
 #define PCI_CLASS_DPIO                0x11
 #define   PCI_SUBCLASS_DPIO             0x00
 #define   PCI_SUBCLASS_DPIO_OTHER       0x80
 
-/**  
+/**
   Macro that checks whether the Base Class code of device matched.
 
   @param  _p      Specified device.
   @param  c       Base Class code needs matching.
 
   @retval TRUE    Base Class code matches the specified device.
-  @retval FALSE   Base Class code doesn't match the specified device.         
+  @retval FALSE   Base Class code doesn't match the specified device.
 
 **/
 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))
-/**  
+/**
   Macro that checks whether the Base Class code and Sub-Class code of device matched.
 
   @param  _p      Specified device.
@@ -323,11 +323,11 @@ typedef struct {
   @param  s       Sub-Class code needs matching.
 
   @retval TRUE    Base Class code and Sub-Class code match the specified device.
-  @retval FALSE   Base Class code and Sub-Class code don't match the specified device.         
+  @retval FALSE   Base Class code and Sub-Class code don't match the specified device.
 
 **/
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))
-/**  
+/**
   Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.
 
   @param  _p      Specified device.
@@ -336,12 +336,12 @@ typedef struct {
   @param  p       Interface code needs matching.
 
   @retval TRUE    Base Class code, Sub-Class code and Interface code match the specified device.
-  @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.         
+  @retval FALSE   Base Class code, Sub-Class code and Interface code don't match the specified device.
 
 **/
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))
 
-/**  
+/**
   Macro that checks whether device is a display controller.
 
   @param  _p      Specified device.
@@ -351,7 +351,7 @@ typedef struct {
 
 **/
 #define IS_PCI_DISPLAY(_p)            IS_CLASS1 (_p, PCI_CLASS_DISPLAY)
-/**  
+/**
   Macro that checks whether device is a VGA-compatible controller.
 
   @param  _p      Specified device.
@@ -361,7 +361,7 @@ typedef struct {
 
 **/
 #define IS_PCI_VGA(_p)                IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)
-/**  
+/**
   Macro that checks whether device is an 8514-compatible controller.
 
   @param  _p      Specified device.
@@ -371,7 +371,7 @@ typedef struct {
 
 **/
 #define IS_PCI_8514(_p)               IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)
-/**  
+/**
   Macro that checks whether device is built before the Class Code field was defined.
 
   @param  _p      Specified device.
@@ -381,7 +381,7 @@ typedef struct {
 
 **/
 #define IS_PCI_OLD(_p)                IS_CLASS1 (_p, PCI_CLASS_OLD)
-/**  
+/**
   Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.
 
   @param  _p      Specified device.
@@ -391,7 +391,7 @@ typedef struct {
 
 **/
 #define IS_PCI_OLD_VGA(_p)            IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)
-/**  
+/**
   Macro that checks whether device is an IDE controller.
 
   @param  _p      Specified device.
@@ -401,7 +401,7 @@ typedef struct {
 
 **/
 #define IS_PCI_IDE(_p)                IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)
-/**  
+/**
   Macro that checks whether device is a SCSI bus controller.
 
   @param  _p      Specified device.
@@ -411,7 +411,7 @@ typedef struct {
 
 **/
 #define IS_PCI_SCSI(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)
-/**  
+/**
   Macro that checks whether device is a RAID controller.
 
   @param  _p      Specified device.
@@ -421,7 +421,7 @@ typedef struct {
 
 **/
 #define IS_PCI_RAID(_p)               IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)
-/**  
+/**
   Macro that checks whether device is an ISA bridge.
 
   @param  _p      Specified device.
@@ -431,7 +431,7 @@ typedef struct {
 
 **/
 #define IS_PCI_LPC(_p)                IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)
-/**  
+/**
   Macro that checks whether device is a PCI-to-PCI bridge.
 
   @param  _p      Specified device.
@@ -441,7 +441,7 @@ typedef struct {
 
 **/
 #define IS_PCI_P2P(_p)                IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)
-/**  
+/**
   Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.
 
   @param  _p      Specified device.
@@ -451,7 +451,7 @@ typedef struct {
 
 **/
 #define IS_PCI_P2P_SUB(_p)            IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)
-/**  
+/**
   Macro that checks whether device is a 16550-compatible serial controller.
 
   @param  _p      Specified device.
@@ -461,7 +461,7 @@ typedef struct {
 
 **/
 #define IS_PCI_16550_SERIAL(_p)       IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)
-/**  
+/**
   Macro that checks whether device is a Universal Serial Bus controller.
 
   @param  _p      Specified device.
@@ -473,7 +473,7 @@ typedef struct {
 #define IS_PCI_USB(_p)                IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)
 
 //
-// the definition of Header Type 
+// the definition of Header Type
 //
 #define HEADER_TYPE_DEVICE            0x00
 #define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
@@ -483,7 +483,7 @@ typedef struct {
 // Mask of Header type
 //
 #define HEADER_LAYOUT_CODE            0x7f
-/**  
+/**
   Macro that checks whether device is a PCI-PCI bridge.
 
   @param  _p      Specified device.
@@ -493,7 +493,7 @@ typedef struct {
 
 **/
 #define IS_PCI_BRIDGE(_p)             (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))
-/**  
+/**
   Macro that checks whether device is a CardBus bridge.
 
   @param  _p      Specified device.
@@ -503,7 +503,7 @@ typedef struct {
 
 **/
 #define IS_CARDBUS_BRIDGE(_p)         (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))
-/**  
+/**
   Macro that checks whether device is a multiple functions device.
 
   @param  _p      Specified device.
@@ -548,17 +548,17 @@ typedef struct {
 //
 // defined in PCI-to-PCI Bridge Architecture Specification
 //
-#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18   
+#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET      0x18
-#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19   
+#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET    0x19
-#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a   
+#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET  0x1a
 #define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET   0x1b
-#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E   
+#define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E
-#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E   
+#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E
 
 ///
 /// Interrupt Line "Unknown" or "No connection" value defined for x86 based system
 ///
-#define PCI_INT_LINE_UNKNOWN                        0xFF               
+#define PCI_INT_LINE_UNKNOWN                        0xFF
 
 ///
 /// PCI Access Data Format
@@ -770,7 +770,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_MSI64;
 
 ///
-/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG, 
+/// Capability EFI_PCI_CAPABILITY_ID_HOTPLUG,
 /// CompactPCI Hot Swap Specification PICMG 2.1, R1.0
 ///
 typedef struct {
@@ -789,8 +789,8 @@ typedef struct {
 
 ///
 /// EFI PCI Option ROM definitions
-/// 
+///
-#define EFI_ROOT_BRIDGE_LIST                            'eprb'  
+#define EFI_ROOT_BRIDGE_LIST                            'eprb'
 #define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE       0x0EF1  ///< defined in UEFI Spec.
 
 #define PCI_EXPANSION_ROM_HEADER_SIGNATURE              0xaa55

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci23.h

@@ -2,13 +2,13 @@
   Support for PCI 2.3 standard.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php.                                            
+  http://opensource.org/licenses/bsd-license.php.
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -96,7 +96,7 @@
 
 #pragma pack(1)
 ///
-/// PCI-X Capabilities List, 
+/// PCI-X Capabilities List,
 /// Section 7.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 ///
 typedef struct {
@@ -106,7 +106,7 @@ typedef struct {
 } EFI_PCI_CAPABILITY_PCIX;
 
 ///
-/// PCI-X Bridge Capabilities List, 
+/// PCI-X Bridge Capabilities List,
 /// Section 8.6.2, PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b.
 ///
 typedef struct {

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Pci30.h

@@ -2,13 +2,13 @@
   Support for PCI 3.0 standard.
 
   Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciCodeId.h

@@ -3,13 +3,13 @@
   revision 1.3.
 
   Copyright (c) 2012, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress21.h

@@ -2,14 +2,14 @@
   Support for the latest PCI standard.
 
   Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>  
+  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PciExpress30.h

@@ -4,13 +4,13 @@
   This header file may not define all structures.  Please extend as required.
 
   Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
-  This program and the accompanying materials                          
+  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License         
+  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at        
+  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php                                            
+  http://opensource.org/licenses/bsd-license.php
 
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/PeImage.h

@@ -1,21 +1,21 @@
 /** @file
-  EFI image format for PE32, PE32+ and TE. Please note some data structures are 
+  EFI image format for PE32, PE32+ and TE. Please note some data structures are
-  different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and 
+  different for PE32 and PE32+. EFI_IMAGE_NT_HEADERS32 is for PE32 and
-  EFI_IMAGE_NT_HEADERS64 is for PE32+. 
+  EFI_IMAGE_NT_HEADERS64 is for PE32+.
 
-  This file is coded to the Visual Studio, Microsoft Portable Executable and 
+  This file is coded to the Visual Studio, Microsoft Portable Executable and
   Common Object File Format Specification, Revision 8.3 - February 6, 2013.
   This file also includes some definitions in PI Specification, Revision 1.0.
 
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-This program and the accompanying materials                          
+This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License         
+are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution.  The full text of the license may be found at        
+which accompanies this distribution.  The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                           
+http://opensource.org/licenses/bsd-license.php.
 
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -134,12 +134,12 @@ typedef struct {
 
 ///
 /// @attention
-/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and 
+/// EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC means PE32 and
 /// EFI_IMAGE_OPTIONAL_HEADER32 must be used. The data structures only vary
 /// after NT additional fields.
 ///
 #define EFI_IMAGE_NT_OPTIONAL_HDR32_MAGIC 0x10b
-          
+
 ///
 /// Optional Header Standard Fields for PE32.
 ///
@@ -185,7 +185,7 @@ typedef struct {
 
 ///
 /// @attention
-/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and 
+/// EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC means PE32+ and
 /// EFI_IMAGE_OPTIONAL_HEADER64 must be used. The data structures only vary
 /// after NT additional fields.
 ///
@@ -296,7 +296,7 @@ typedef struct {
 /// Size of EFI_IMAGE_SECTION_HEADER.
 ///
 #define EFI_IMAGE_SIZEOF_SECTION_HEADER       40
-         
+
 //
 // Section Flags Values
 //
@@ -304,12 +304,12 @@ typedef struct {
 #define EFI_IMAGE_SCN_CNT_CODE                     BIT5   ///< 0x00000020
 #define EFI_IMAGE_SCN_CNT_INITIALIZED_DATA         BIT6   ///< 0x00000040
 #define EFI_IMAGE_SCN_CNT_UNINITIALIZED_DATA       BIT7   ///< 0x00000080
-                                                   
+
 #define EFI_IMAGE_SCN_LNK_OTHER                    BIT8   ///< 0x00000100  ///< Reserved.
 #define EFI_IMAGE_SCN_LNK_INFO                     BIT9   ///< 0x00000200  ///< Section contains comments or some other type of information.
 #define EFI_IMAGE_SCN_LNK_REMOVE                   BIT11  ///< 0x00000800  ///< Section contents will not become part of image.
 #define EFI_IMAGE_SCN_LNK_COMDAT                   BIT12  ///< 0x00001000
-                                                   
+
 #define EFI_IMAGE_SCN_ALIGN_1BYTES                 BIT20  ///< 0x00100000
 #define EFI_IMAGE_SCN_ALIGN_2BYTES                 BIT21  ///< 0x00200000
 #define EFI_IMAGE_SCN_ALIGN_4BYTES          (BIT20|BIT21) ///< 0x00300000
@@ -317,7 +317,7 @@ typedef struct {
 #define EFI_IMAGE_SCN_ALIGN_16BYTES         (BIT20|BIT22) ///< 0x00500000
 #define EFI_IMAGE_SCN_ALIGN_32BYTES         (BIT21|BIT22) ///< 0x00600000
 #define EFI_IMAGE_SCN_ALIGN_64BYTES   (BIT20|BIT21|BIT22) ///< 0x00700000
-                                              
+
 #define EFI_IMAGE_SCN_MEM_DISCARDABLE              BIT25  ///< 0x02000000
 #define EFI_IMAGE_SCN_MEM_NOT_CACHED               BIT26  ///< 0x04000000
 #define EFI_IMAGE_SCN_MEM_NOT_PAGED                BIT27  ///< 0x08000000
@@ -415,7 +415,7 @@ typedef struct {
 #define EFI_IMAGE_COMDAT_SELECT_SAME_SIZE       3
 #define EFI_IMAGE_COMDAT_SELECT_EXACT_MATCH     4
 #define EFI_IMAGE_COMDAT_SELECT_ASSOCIATIVE     5
-                                       
+
 //
 // the following values only be referred in PeCoff, not defined in PECOFF.
 //
@@ -450,9 +450,9 @@ typedef struct {
 #define EFI_IMAGE_REL_I386_SECREL   0x000B
 #define EFI_IMAGE_REL_I386_REL32    0x0014  ///< PC-relative 32-bit reference to the symbols virtual address.
 
-// 
+//
 // x64 processor relocation types.
-// 
+//
 #define IMAGE_REL_AMD64_ABSOLUTE  0x0000
 #define IMAGE_REL_AMD64_ADDR64    0x0001
 #define IMAGE_REL_AMD64_ADDR32    0x0002

src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Sal.h

@@ -3,13 +3,13 @@
   Layer Specification Revision 3.2 (December 2003)
 
 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available under 
+This program and the accompanying materials are licensed and made available under
-the terms and conditions of the BSD License that accompanies this distribution.  
+the terms and conditions of the BSD License that accompanies this distribution.
 The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.                                          
+http://opensource.org/licenses/bsd-license.php.
-    
+
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 
 **/
 
@@ -17,16 +17,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #define __SAL_API_H__
 
 ///
-/// SAL return status type 
+/// SAL return status type
 ///
 typedef INTN EFI_SAL_STATUS;
 
 ///
-/// Call completed without error. 
+/// Call completed without error.
 ///
 #define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)
 ///
-/// Call completed without error, but some information was lost due to overflow. 
+/// Call completed without error, but some information was lost due to overflow.
 ///
 #define EFI_SAL_OVERFLOW              ((EFI_SAL_STATUS) 1)
 ///
@@ -34,7 +34,7 @@ typedef INTN EFI_SAL_STATUS;
 ///
 #define EFI_SAL_WARM_BOOT_NEEDED      ((EFI_SAL_STATUS) 2)
 ///
-/// More information is available for retrieval. 
+/// More information is available for retrieval.
 ///
 #define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)
 ///
@@ -46,15 +46,15 @@ typedef INTN EFI_SAL_STATUS;
 ///
 #define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)
 ///
-/// Call completed without error. 
+/// Call completed without error.
 ///
 #define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)
 ///
-/// Virtual address not registered. 
+/// Virtual address not registered.
 ///
 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
 ///
-/// No information available. 
+/// No information available.
 ///
 #define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)
 ///
@@ -213,7 +213,7 @@ typedef struct {
 
 //
 // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
-// 
+//
 // Type of information
 //
 #define EFI_SAL_MCA_STATE_INFO  0x0
@@ -345,8 +345,8 @@ typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {
 #pragma pack(1)
 typedef struct {
   ///
-  /// The ASCII string representation of "SST_" that confirms the presence of the table. 
+  /// The ASCII string representation of "SST_" that confirms the presence of the table.
-  /// 
+  ///
   UINT32  Signature;
   ///
   /// The length of the entire table in bytes, starting from offset zero and including the
@@ -470,7 +470,7 @@ typedef struct {
   UINT64  NumberOfProcessors;
   UINT64  LocalIDRegister;
 } SAL_COHERENCE_DOMAIN_INFO;
-           
+
 ///
 /// Format of Purge Translation Cache Coherence Domain Entry.
 ///
@@ -504,7 +504,7 @@ typedef struct {
   UINT8   CheckSum;
 } EFI_SAL_FIT_ENTRY;
 //
-// FIT Types 
+// FIT Types
 //
 #define EFI_SAL_FIT_FIT_HEADER_TYPE                0x00
 #define EFI_SAL_FIT_PAL_B_TYPE                     0x01