AMD S3: Leverage the public SPI routine
Remove the old, unflexible code for storing S3 data in SPI flash. Refer to flashrom. Tested on Parmer. Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/1920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Zheng Bao
Marc Jones
@@ -16,203 +16,107 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <string.h>
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#include <arch/io.h>
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#include <spi.h>
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#include <device/device.h>
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#include "spi.h"
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#include <device/pci.h>
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#include <device/pci_ops.h>
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void execute_command(volatile u8 * spi_address)
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static u32 spibar;
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static void reset_internal_fifo_pointer(void)
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{
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*(spi_address + 2) |= 1;
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}
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void wait4command_complete(volatile u8 * spi_address)
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{
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// while (*(spi_address + 2) & 1)
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while ((*(spi_address + 2) & 1) && (*(spi_address + 3) & 0x80))
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printk(BIOS_DEBUG, "wait4CommandComplete\n");
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}
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void reset_internal_fifo_pointer(volatile u8 * spi_address)
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{
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u8 val;
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do {
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*(spi_address + 2) |= 0x10;
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val = *(spi_address + 0xd);
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} while (val & 0x7);
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write8(spibar + 2, read8(spibar + 2) | 0x10);
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} while (read8(spibar + 0xD) & 0x7);
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}
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u8 read_spi_status(volatile u8 * spi_address)
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static void execute_command(void)
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{
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u8 val;
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*spi_address = 0x05;
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*(spi_address + 1) = 0x21;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0x0; /* dummy */
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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val = *(spi_address + 0xC);
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val = *(spi_address + 0xC);
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val = *(spi_address + 0xC);
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return val;
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write8(spibar + 2, read8(spibar + 2) | 1);
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while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80));
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}
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void wait4flashpart_ready(volatile u8 * spi_address)
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void spi_init()
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{
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while (read_spi_status(spi_address) & 1) ;
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
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spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
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}
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void write_spi_status(volatile u8 * spi_address, u8 status)
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned int bitsout, void *din, unsigned int bitsin)
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{
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*spi_address = 0x50; /* EWSR */
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*(spi_address + 1) = 0; /* RxByte=TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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/* First byte is cmd which can not being sent through FIFO. */
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u8 cmd = *(u8 *)dout++;
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u8 readoffby1;
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u8 readwrite;
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u8 bytesout, bytesin;
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u8 count;
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*spi_address = 0x01; /* WRSR */
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*(spi_address + 1) = 0x01;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = status;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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bitsout -= 8;
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bytesout = bitsout / 8;
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bytesin = bitsin / 8;
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read_spi_status(spi_address);
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}
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readoffby1 = bytesout ? 0 : 1;
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void read_spi_id(volatile u8 * spi_address)
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{
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u8 mid = 0, did = 0;
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*spi_address = 0x90;
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*(spi_address + 1) = 0x23; /* RxByte=2, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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*(spi_address + 0xC) = 0;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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reset_internal_fifo_pointer(spi_address);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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mid = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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readwrite = (bytesin + readoffby1) << 4 | bytesout;
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write8(spibar + 1, readwrite);
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write8(spibar + 0, cmd);
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mid = *(spi_address + 0xC);
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did = *(spi_address + 0xC);
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printk(BIOS_DEBUG, "mid=%x, did=%x\n", mid, did);
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}
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void spi_write_enable(volatile u8 * spi_address)
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{
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*spi_address = 0x06; /* Write Enable */
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*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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}
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void spi_write_disable(volatile u8 * spi_address)
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{
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*spi_address = 0x04; /* Write Enable */
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*(spi_address + 1) = 0x0; /* RxByte=0, TxByte=0 */
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execute_command(spi_address);
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wait4command_complete(spi_address);
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}
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void sector_erase_spi(volatile u8 * spi_address, u32 address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x20;
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*(spi_address + 1) = 0x03; /* RxByte=0, TxByte=3 */
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void chip_erase_spi(volatile u8 * spi_address)
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{
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spi_write_enable(spi_address);
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*spi_address = 0xC7;
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*(spi_address + 1) = 0x00;
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void byte_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void dword_noneAAI_program(volatile u8 * spi_address, u32 address, u32 data)
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{
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u8 i;
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/*
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* printk(BIOS_SPEW, "%s: addr=%x, data=%x\n", __func__, address, data);
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*/
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for (i = 0; i < 4; i++) {
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 4;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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data >>= 8;
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address++;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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reset_internal_fifo_pointer();
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for (count = 0; count < bytesout; count++, dout++) {
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write8(spibar + 0x0C, *(u8 *)dout);
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}
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reset_internal_fifo_pointer();
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execute_command();
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reset_internal_fifo_pointer();
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/* Skip the bytes we sent. */
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for (count = 0; count < bytesout; count++) {
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cmd = read8(spibar + 0x0C);
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}
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reset_internal_fifo_pointer();
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for (count = 0; count < bytesin; count++, din++) {
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*(u8 *)din = read8(spibar + 0x0C);
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}
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return 0;
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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return 0;
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}
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void dword_program(volatile u8 * spi_address, u32 address, u32 data)
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void spi_release_bus(struct spi_slave *slave)
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{
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spi_write_enable(spi_address);
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*spi_address = 0x02;
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*(spi_address + 1) = 0x0 << 4 | 7;
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reset_internal_fifo_pointer(spi_address);
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*(spi_address + 0xC) = (address >> 16) & 0xFF;
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*(spi_address + 0xC) = (address >> 8) & 0xFF;
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*(spi_address + 0xC) = (address >> 0) & 0xFF;
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*(spi_address + 0xC) = data & 0xFF;
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*(spi_address + 0xC) = (data >> 8) & 0xFF;
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*(spi_address + 0xC) = (data >> 16) & 0xFF;
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*(spi_address + 0xC) = (data >> 24) & 0xFF;
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reset_internal_fifo_pointer(spi_address);
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execute_command(spi_address);
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wait4command_complete(spi_address);
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wait4flashpart_ready(spi_address);
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}
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void direct_byte_program(volatile u8 * spi_address, volatile u32 * address, u32 data)
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void spi_cs_activate(struct spi_slave *slave)
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{
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spi_write_enable(spi_address);
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*address = data;
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wait4flashpart_ready(spi_address);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct spi_slave *slave = malloc(sizeof(*slave));
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if (!slave) {
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return NULL;
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}
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memset(slave, 0, sizeof(*slave));
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return slave;
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}
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