Add RPP-S PCI ID definitions

Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
This commit is contained in:
Jeremy Soller
2023-02-10 11:57:04 -07:00
parent c93982f2f9
commit 7c0aa8288c
9 changed files with 59 additions and 0 deletions

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@@ -3671,6 +3671,13 @@
#define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5 #define PCI_DID_INTEL_ADP_M_N_I2C4 0x54c5
#define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6 #define PCI_DID_INTEL_ADP_M_N_I2C5 0x54c6
#define PCI_DID_INTEL_RPP_S_I2C0 0x7a4c
#define PCI_DID_INTEL_RPP_S_I2C1 0x7a4d
#define PCI_DID_INTEL_RPP_S_I2C2 0x7a4e
#define PCI_DID_INTEL_RPP_S_I2C3 0x7a4f
#define PCI_DID_INTEL_RPP_S_I2C4 0x7a7c
#define PCI_DID_INTEL_RPP_S_I2C5 0x7a7d
#define PCI_DID_INTEL_MTL_I2C0 0x7e78 #define PCI_DID_INTEL_MTL_I2C0 0x7e78
#define PCI_DID_INTEL_MTL_I2C1 0x7e79 #define PCI_DID_INTEL_MTL_I2C1 0x7e79
#define PCI_DID_INTEL_MTL_I2C2 0x7e7a #define PCI_DID_INTEL_MTL_I2C2 0x7e7a
@@ -3748,6 +3755,10 @@
#define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7 #define PCI_DID_INTEL_ADP_M_N_UART2 0x54c7
#define PCI_DID_INTEL_ADP_M_N_UART3 0x54da #define PCI_DID_INTEL_ADP_M_N_UART3 0x54da
#define PCI_DID_INTEL_RPP_S_UART0 0x7a28
#define PCI_DID_INTEL_RPP_S_UART1 0x7a29
#define PCI_DID_INTEL_RPP_S_UART2 0x7a7e
#define PCI_DID_INTEL_MTL_UART0 0x7e25 #define PCI_DID_INTEL_MTL_UART0 0x7e25
#define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART1 0x7e26
#define PCI_DID_INTEL_MTL_UART2 0x7e52 #define PCI_DID_INTEL_MTL_UART2 0x7e52
@@ -3833,6 +3844,12 @@
#define PCI_DID_INTEL_ADP_M_N_SPI1 0x54ab #define PCI_DID_INTEL_ADP_M_N_SPI1 0x54ab
#define PCI_DID_INTEL_ADP_M_SPI2 0x54fb #define PCI_DID_INTEL_ADP_M_SPI2 0x54fb
#define PCI_DID_INTEL_RPP_S_HWSEQ_SPI 0x7a24
#define PCI_DID_INTEL_RPP_S_SPI0 0x7a2a
#define PCI_DID_INTEL_RPP_S_SPI1 0x7a2b
#define PCI_DID_INTEL_RPP_S_SPI2 0x7a7b
#define PCI_DID_INTEL_RPP_S_SPI3 0x7a79
#define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca #define PCI_DID_INTEL_SPR_HWSEQ_SPI 0x1bca
#define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23 #define PCI_DID_INTEL_MTL_HWSEQ_SPI 0x7e23
@@ -4148,6 +4165,7 @@
#define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3 #define PCI_DID_INTEL_ADP_M_N_SMBUS 0x54a3
#define PCI_DID_INTEL_MTL_SMBUS 0x7e22 #define PCI_DID_INTEL_MTL_SMBUS 0x7e22
#define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3
#define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23
/* Intel EHCI device IDs */ /* Intel EHCI device IDs */
#define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26
@@ -4184,6 +4202,7 @@
#define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0
#define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0 #define PCI_DID_INTEL_MTL_P_TCSS_XHCI 0x7ec0
#define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e #define PCI_DID_INTEL_RPP_P_TCSS_XHCI 0xa71e
#define PCI_DID_INTEL_RPP_S_TCSS_XHCI 0x7a60
/* Intel P2SB device Ids */ /* Intel P2SB device Ids */
#define PCI_DID_INTEL_APL_P2SB 0x5a92 #define PCI_DID_INTEL_APL_P2SB 0x5a92
@@ -4252,6 +4271,14 @@
#define PCI_DID_INTEL_ADP_S_AUDIO_8 0x7ad7 #define PCI_DID_INTEL_ADP_S_AUDIO_8 0x7ad7
#define PCI_DID_INTEL_ADP_P_AUDIO 0x51c8 #define PCI_DID_INTEL_ADP_P_AUDIO 0x51c8
#define PCI_DID_INTEL_RPP_P_AUDIO 0x51ca #define PCI_DID_INTEL_RPP_P_AUDIO 0x51ca
#define PCI_DID_INTEL_RPP_S_AUDIO_1 0x7a50
#define PCI_DID_INTEL_RPP_S_AUDIO_2 0x7a51
#define PCI_DID_INTEL_RPP_S_AUDIO_3 0x7a52
#define PCI_DID_INTEL_RPP_S_AUDIO_4 0x7a53
#define PCI_DID_INTEL_RPP_S_AUDIO_5 0x7a54
#define PCI_DID_INTEL_RPP_S_AUDIO_6 0x7a55
#define PCI_DID_INTEL_RPP_S_AUDIO_7 0x7a56
#define PCI_DID_INTEL_RPP_S_AUDIO_8 0x7a57
#define PCI_DID_INTEL_ADP_M_N_AUDIO_1 0x54c8 #define PCI_DID_INTEL_ADP_M_N_AUDIO_1 0x54c8
#define PCI_DID_INTEL_ADP_M_N_AUDIO_2 0x54c9 #define PCI_DID_INTEL_ADP_M_N_AUDIO_2 0x54c9

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@@ -22,6 +22,14 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_7,
PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_MTL_AUDIO_8,
PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO,
PCI_DID_INTEL_RPP_S_AUDIO_1,
PCI_DID_INTEL_RPP_S_AUDIO_2,
PCI_DID_INTEL_RPP_S_AUDIO_3,
PCI_DID_INTEL_RPP_S_AUDIO_4,
PCI_DID_INTEL_RPP_S_AUDIO_5,
PCI_DID_INTEL_RPP_S_AUDIO_6,
PCI_DID_INTEL_RPP_S_AUDIO_7,
PCI_DID_INTEL_RPP_S_AUDIO_8,
PCI_DID_INTEL_APL_AUDIO, PCI_DID_INTEL_APL_AUDIO,
PCI_DID_INTEL_CNL_AUDIO, PCI_DID_INTEL_CNL_AUDIO,
PCI_DID_INTEL_GLK_AUDIO, PCI_DID_INTEL_GLK_AUDIO,

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@@ -561,6 +561,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LWB_SPI_SUPER, PCI_DID_INTEL_LWB_SPI_SUPER,
PCI_DID_INTEL_MCC_SPI0, PCI_DID_INTEL_MCC_SPI0,
PCI_DID_INTEL_MTL_HWSEQ_SPI, PCI_DID_INTEL_MTL_HWSEQ_SPI,
PCI_DID_INTEL_RPP_S_HWSEQ_SPI,
PCI_DID_INTEL_SPR_HWSEQ_SPI, PCI_DID_INTEL_SPR_HWSEQ_SPI,
PCI_DID_INTEL_TGP_SPI0, PCI_DID_INTEL_TGP_SPI0,
0 0

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@@ -30,6 +30,14 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_AUDIO_7, PCI_DID_INTEL_MTL_AUDIO_7,
PCI_DID_INTEL_MTL_AUDIO_8, PCI_DID_INTEL_MTL_AUDIO_8,
PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO,
PCI_DID_INTEL_RPP_S_AUDIO_1,
PCI_DID_INTEL_RPP_S_AUDIO_2,
PCI_DID_INTEL_RPP_S_AUDIO_3,
PCI_DID_INTEL_RPP_S_AUDIO_4,
PCI_DID_INTEL_RPP_S_AUDIO_5,
PCI_DID_INTEL_RPP_S_AUDIO_6,
PCI_DID_INTEL_RPP_S_AUDIO_7,
PCI_DID_INTEL_RPP_S_AUDIO_8,
PCI_DID_INTEL_APL_AUDIO, PCI_DID_INTEL_APL_AUDIO,
PCI_DID_INTEL_GLK_AUDIO, PCI_DID_INTEL_GLK_AUDIO,
PCI_DID_INTEL_LWB_AUDIO, PCI_DID_INTEL_LWB_AUDIO,

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@@ -272,6 +272,12 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_M_N_I2C3, PCI_DID_INTEL_ADP_M_N_I2C3,
PCI_DID_INTEL_ADP_M_N_I2C4, PCI_DID_INTEL_ADP_M_N_I2C4,
PCI_DID_INTEL_ADP_M_N_I2C5, PCI_DID_INTEL_ADP_M_N_I2C5,
PCI_DID_INTEL_RPP_S_I2C0,
PCI_DID_INTEL_RPP_S_I2C1,
PCI_DID_INTEL_RPP_S_I2C2,
PCI_DID_INTEL_RPP_S_I2C3,
PCI_DID_INTEL_RPP_S_I2C4,
PCI_DID_INTEL_RPP_S_I2C5,
0, 0,
}; };

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@@ -52,6 +52,7 @@ struct device_operations smbus_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_SMBUS, PCI_DID_INTEL_MTL_SMBUS,
PCI_DID_INTEL_RPP_P_SMBUS, PCI_DID_INTEL_RPP_P_SMBUS,
PCI_DID_INTEL_RPP_S_SMBUS,
PCI_DID_INTEL_APL_SMBUS, PCI_DID_INTEL_APL_SMBUS,
PCI_DID_INTEL_GLK_SMBUS, PCI_DID_INTEL_GLK_SMBUS,
PCI_DID_INTEL_CNL_SMBUS, PCI_DID_INTEL_CNL_SMBUS,

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@@ -184,6 +184,10 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_M_N_SPI0, PCI_DID_INTEL_ADP_M_N_SPI0,
PCI_DID_INTEL_ADP_M_N_SPI1, PCI_DID_INTEL_ADP_M_N_SPI1,
PCI_DID_INTEL_ADP_M_SPI2, PCI_DID_INTEL_ADP_M_SPI2,
PCI_DID_INTEL_RPP_S_SPI0,
PCI_DID_INTEL_RPP_S_SPI1,
PCI_DID_INTEL_RPP_S_SPI2,
PCI_DID_INTEL_RPP_S_SPI3,
PCI_DID_INTEL_DNV_SPI, PCI_DID_INTEL_DNV_SPI,
0 0
}; };

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@@ -407,6 +407,9 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_M_N_UART1, PCI_DID_INTEL_ADP_M_N_UART1,
PCI_DID_INTEL_ADP_M_N_UART2, PCI_DID_INTEL_ADP_M_N_UART2,
PCI_DID_INTEL_ADP_M_N_UART3, PCI_DID_INTEL_ADP_M_N_UART3,
PCI_DID_INTEL_RPP_S_UART0,
PCI_DID_INTEL_RPP_S_UART1,
PCI_DID_INTEL_RPP_S_UART2,
0, 0,
}; };

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@@ -27,6 +27,7 @@ static struct device_operations usb4_xhci_ops = {
static const unsigned short pci_device_ids[] = { static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_RPP_P_TCSS_XHCI, PCI_DID_INTEL_RPP_P_TCSS_XHCI,
PCI_DID_INTEL_RPP_S_TCSS_XHCI,
PCI_DID_INTEL_MTL_M_TCSS_XHCI, PCI_DID_INTEL_MTL_M_TCSS_XHCI,
PCI_DID_INTEL_MTL_P_TCSS_XHCI, PCI_DID_INTEL_MTL_P_TCSS_XHCI,
PCI_DID_INTEL_TGP_TCSS_XHCI, PCI_DID_INTEL_TGP_TCSS_XHCI,