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Addition of Family12/SB900 wrapper code

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This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
efdesign98
2011-06-20 19:56:06 -07:00
committed by Stefan Reinauer
parent 7c634ae8c1
commit 7c0c64e103
47 changed files with 4915 additions and 22 deletions
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53
src/include/cpu/amd/amdfam12.h Executable file
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@@ -0,0 +1,53 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef CPU_AMD_FAM12_H
#define CPU_AMD_FAM12_H
#include <cpu/x86/msr.h>
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
#define LS_CFG_MSR 0xC0011020
#define IC_CFG_MSR 0xC0011021
#define DC_CFG_MSR 0xC0011022
#define BU_CFG_MSR 0xC0011023
#define BU_CFG2_MSR 0xC001102A
#define CPU_ID_FEATURES_MSR 0xC0011004
#define CPU_ID_EXT_FEATURES_MSR 0xC0011005
msr_t rdmsr_amd(u32 index);
void wrmsr_amd(u32 index, msr_t msr);
//#if defined(__GNUC__)
//// it can be used to get unitid and coreid it running only
//struct node_core_id get_node_core_id(u32 nb_cfg_54);
//struct node_core_id get_node_core_id_x(void);
//#endif
#if defined(__PRE_RAM__)
void wait_all_core0_started(void);
void wait_all_other_cores_started(u32 bsp_apicid);
void wait_all_aps_started(u32 bsp_apicid);
void allow_all_aps_stop(u32 bsp_apicid);
#endif
u32 get_initial_apicid(void);
#endif /* CPU_AMD_FAM12_H */

23
src/include/device/pci_ids.h
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@@ -332,6 +332,29 @@
#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396
#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699
#define PCI_DEVICE_ID_ATI_SB900_LPC 0x780E
#define PCI_DEVICE_ID_ATI_SB900_SATA 0x7800
#define PCI_DEVICE_ID_ATI_SB900_SATA_AHCI 0x7801
#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID 0x7802
#define PCI_DEVICE_ID_ATI_SB900_SATA_RAID5 0x7803
#define PCI_DEVICE_ID_ATI_SB900_SATA_AMDAHCI 0x7804
#define PCI_DEVICE_ID_ATI_SB900_IDE 0x780C
#define PCI_DEVICE_ID_ATI_SB900_HDA 0x780D
#define PCI_DEVICE_ID_ATI_SB900_PCI 0x780F
#define PCI_DEVICE_ID_ATI_SB900_PCIEA 0x43A0
#define PCI_DEVICE_ID_ATI_SB900_PCIEB 0x43A1
#define PCI_DEVICE_ID_ATI_SB900_PCIEC 0x43A2
#define PCI_DEVICE_ID_ATI_SB900_PCIED 0x43A3
#define PCI_DEVICE_ID_ATI_SB900_SM 0x780B
#define PCI_DEVICE_ID_ATI_SB900_USB_16_0 0x7812
#define PCI_DEVICE_ID_ATI_SB900_USB_16_1 0x7812
#define PCI_DEVICE_ID_ATI_SB900_USB_18_0 0x7807
#define PCI_DEVICE_ID_ATI_SB900_USB_18_2 0x7808
#define PCI_DEVICE_ID_ATI_SB900_USB_19_0 0x7807
#define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808
#define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809
#define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910
#define PCI_DEVICE_ID_ATI_RS740_HT 0x7911
#define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912