nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code - Move MCHBAR registers and documentation into a separate file - Add a few missing macros - Rename some registers - Rewrite several comments - Use C-style comments for consistency - Rewrite some hex constants - Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0) With BUILD_TIMELESS=1, this commit does not change the result of: - Asus P8Z77-V LX2 with native raminit. - Asus P8Z77-M PRO with MRC raminit. Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
committed by
Matt DeVillier
Matt DeVillier
parent
1cd7d3e664
commit
7c49cb8f9c
@ -35,47 +35,48 @@
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#define MRC_CACHE_VERSION 1
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/* FIXME: no ECC support. */
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/* FIXME: no support for 3-channel chipsets. */
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/* FIXME: no ECC support */
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/* FIXME: no support for 3-channel chipsets */
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static const char *ecc_decoder[] = {
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"inactive",
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"active on IO",
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"disabled on IO",
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"active"
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"active",
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};
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static void wait_txt_clear(void)
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{
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struct cpuid_result cp;
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struct cpuid_result cp = cpuid_ext(1, 0);
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cp = cpuid_ext(0x1, 0x0);
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/* Check if TXT is supported? */
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if (!(cp.ecx & 0x40))
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/* Check if TXT is supported */
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if (!(cp.ecx & (1 << 6)))
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return;
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/* Some TXT public bit. */
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/* Some TXT public bit */
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if (!(read32((void *)0xfed30010) & 1))
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return;
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/* Wait for TXT clear. */
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while (!(read8((void *)0xfed40000) & (1 << 7)));
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/* Wait for TXT clear */
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while (!(read8((void *)0xfed40000) & (1 << 7)))
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;
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}
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/*
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* Disable a channel in ramctr_timing.
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*/
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static void disable_channel(ramctr_timing *ctrl, int channel) {
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/* Disable a channel in ramctr_timing */
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static void disable_channel(ramctr_timing *ctrl, int channel)
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{
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ctrl->rankmap[channel] = 0;
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memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0]));
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ctrl->channel_size_mb[channel] = 0;
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ctrl->cmd_stretch[channel] = 0;
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ctrl->mad_dimm[channel] = 0;
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memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));
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ctrl->cmd_stretch[channel] = 0;
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ctrl->mad_dimm[channel] = 0;
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memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));
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memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));
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}
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/*
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* Fill cbmem with information for SMBIOS type 17.
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*/
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/* Fill cbmem with information for SMBIOS type 17 */
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static void fill_smbios17(ramctr_timing *ctrl)
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{
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int channel, slot;
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@ -89,54 +90,50 @@ static void fill_smbios17(ramctr_timing *ctrl)
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}
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}
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/*
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* Dump in the log memory controller configuration as read from the memory
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* controller registers.
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*/
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#define ON_OFF(val) (((val) & 1) ? "on" : "off")
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/* Print the memory controller configuration as read from the memory controller registers. */
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static void report_memory_config(void)
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{
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u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
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int i, refclk;
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int i;
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addr_decoder_common = MCHBAR32(MAD_CHNL);
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addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
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addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
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addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
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addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
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refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
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const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
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printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
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printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
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(MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
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printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
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addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 0) & 3,
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(addr_decoder_common >> 2) & 3,
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(addr_decoder_common >> 4) & 3);
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for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
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u32 ch_conf = addr_decode_ch[i];
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i,
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ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n",
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ecc_decoder[(ch_conf >> 24) & 3]);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
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((ch_conf >> 22) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, " rank interleave %s\n",
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((ch_conf >> 21) & 1) ? "on" : "off");
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printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
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printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
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printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
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printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
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printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 0) & 0xff) * 256,
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((ch_conf >> 19) & 1) ? 16 : 8,
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((ch_conf >> 17) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? "" : ", selected");
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printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 8) & 0xff) * 256,
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((ch_conf >> 20) & 1) ? 16 : 8,
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((ch_conf >> 18) & 1) ? "dual" : "single",
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((ch_conf >> 16) & 1) ? ", selected" : "");
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}
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}
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#undef ON_OFF
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/*
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* Return CRC16 match for all SPDs.
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*/
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/* Return CRC16 match for all SPDs */
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static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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{
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int channel, slot, spd_slot;
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@ -146,7 +143,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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for (slot = 0; slot < NUM_SLOTS; slot++) {
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spd_slot = 2 * channel + slot;
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match &= ctrl->spd_crc[channel][slot] ==
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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}
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}
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return match;
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@ -166,7 +163,7 @@ void read_spd(spd_raw_data * spd, u8 addr, bool id_only)
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static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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{
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int dimms = 0, dimms_on_channel;
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int dimms = 0, ch_dimms;
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int channel, slot, spd_slot;
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dimm_info *dimm = &ctrl->info;
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@ -178,53 +175,55 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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FOR_ALL_CHANNELS {
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ctrl->channel_size_mb[channel] = 0;
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dimms_on_channel = 0;
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/* count dimms on channel */
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ch_dimms = 0;
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/* Count dimms on channel */
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for (slot = 0; slot < NUM_SLOTS; slot++) {
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spd_slot = 2 * channel + slot;
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printk(BIOS_DEBUG,
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"SPD probe channel%d, slot%d\n", channel, slot);
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printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
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spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
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if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3)
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dimms_on_channel++;
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ch_dimms++;
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}
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for (slot = 0; slot < NUM_SLOTS; slot++) {
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spd_slot = 2 * channel + slot;
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printk(BIOS_DEBUG,
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"SPD probe channel%d, slot%d\n", channel, slot);
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printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
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/* search for XMP profile */
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spd_xmp_decode_ddr3(&dimm->dimm[channel][slot],
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spd[spd_slot],
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/* Search for XMP profile */
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spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot],
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DDR3_XMP_PROFILE_1);
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if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
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printram("No valid XMP profile found.\n");
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spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
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} else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) {
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printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
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dimm->dimm[channel][slot].dimms_per_channel,
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dimms_on_channel);
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} else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) {
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printram(
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"XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
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dimm->dimm[channel][slot].dimms_per_channel, ch_dimms);
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if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
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printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n");
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printk(BIOS_WARNING,
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"XMP maximum DIMMs will be ignored.\n");
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else
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spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
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spd_decode_ddr3(&dimm->dimm[channel][slot],
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spd[spd_slot]);
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} else if (dimm->dimm[channel][slot].voltage != 1500) {
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/* TODO: support other DDR3 voltage than 1500mV */
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/* TODO: Support DDR3 voltages other than 1500mV */
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printram("XMP profile's requested %u mV is unsupported.\n",
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dimm->dimm[channel][slot].voltage);
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spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
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}
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/* fill in CRC16 for MRC cache */
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/* Fill in CRC16 for MRC cache */
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ctrl->spd_crc[channel][slot] =
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
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if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
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// set dimm invalid
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dimm->dimm[channel][slot].ranks = 0;
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/* Mark DIMM as invalid */
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dimm->dimm[channel][slot].ranks = 0;
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dimm->dimm[channel][slot].size_mb = 0;
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continue;
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}
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@ -232,30 +231,40 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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dram_print_spd_ddr3(&dimm->dimm[channel][slot]);
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dimms++;
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ctrl->rank_mirror[channel][slot * 2] = 0;
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ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored;
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ctrl->rank_mirror[channel][slot * 2 + 1] =
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dimm->dimm[channel][slot].flags.pins_mirrored;
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ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb;
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ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr;
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ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh;
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ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot);
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printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n",
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channel, ctrl->rankmap[channel]);
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ctrl->extended_temperature_range &=
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dimm->dimm[channel][slot].flags.ext_temp_refresh;
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ctrl->rankmap[channel] |=
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((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot);
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printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel,
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ctrl->rankmap[channel]);
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}
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if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)
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&& dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) {
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if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c)
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&& dimm->dimm[channel][0].reference_card <= 5
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&& dimm->dimm[channel][1].reference_card <= 5) {
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const int ref_card_offset_table[6][6] = {
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{ 0, 0, 0, 0, 2, 2, },
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{ 0, 0, 0, 0, 2, 2, },
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{ 0, 0, 0, 0, 2, 2, },
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{ 0, 0, 0, 0, 1, 1, },
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{ 2, 2, 2, 1, 0, 0, },
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{ 2, 2, 2, 1, 0, 0, },
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{ 0, 0, 0, 0, 2, 2 },
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{ 0, 0, 0, 0, 2, 2 },
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{ 0, 0, 0, 0, 2, 2 },
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{ 0, 0, 0, 0, 1, 1 },
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{ 2, 2, 2, 1, 0, 0 },
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{ 2, 2, 2, 1, 0, 0 },
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};
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ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card]
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[dimm->dimm[channel][1].reference_card];
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} else
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ctrl->ref_card_offset[channel] = ref_card_offset_table
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[dimm->dimm[channel][0].reference_card]
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[dimm->dimm[channel][1].reference_card];
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} else {
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ctrl->ref_card_offset[channel] = 0;
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}
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}
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if (!dimms)
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@ -265,29 +274,24 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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static void save_timings(ramctr_timing *ctrl)
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{
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/* Save the MRC S3 restore data to cbmem */
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl,
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sizeof(*ctrl));
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mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl));
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}
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static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
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int s3_resume, int me_uma_size)
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static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
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{
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if (ctrl->sandybridge)
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return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size);
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return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size);
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else
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return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);
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return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size);
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}
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static void init_dram_ddr3(int min_tck, int s3resume)
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{
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int me_uma_size;
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int cbmem_was_inited;
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int me_uma_size, cbmem_was_inited, fast_boot, err;
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ramctr_timing ctrl;
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int fast_boot;
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spd_raw_data spds[4];
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struct region_device rdev;
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ramctr_timing *ctrl_cached;
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int err;
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u32 cpu;
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MCHBAR32(SAPMCTL) |= 1;
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@ -298,17 +302,14 @@ static void init_dram_ddr3(int min_tck, int s3resume)
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printk(BIOS_DEBUG, "Starting native Platform init\n");
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u32 reg_5d10;
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wait_txt_clear();
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wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
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reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000
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if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
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&& reg_5d10 && !s3resume) {
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MCHBAR32(0x5d10) = 0;
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/* Need reset. */
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const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000
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if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) {
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MCHBAR32(SSKPD) = 0;
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/* Need reset */
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system_reset();
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}
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@ -316,10 +317,9 @@ static void init_dram_ddr3(int min_tck, int s3resume)
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early_init_dmi();
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early_thermal_init();
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/* try to find timings in MRC cache */
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int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
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MRC_CACHE_VERSION, &rdev);
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if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) {
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/* Try to find timings in MRC cache */
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err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
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if (err || (region_device_sz(&rdev) < sizeof(ctrl))) {
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if (s3resume) {
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/* Failed S3 resume, reset to come up cleanly */
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system_reset();
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@ -329,7 +329,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
|
||||
ctrl_cached = rdev_mmap_full(&rdev);
|
||||
}
|
||||
|
||||
/* verify MRC cache for fast boot */
|
||||
/* Verify MRC cache for fast boot */
|
||||
if (!s3resume && ctrl_cached) {
|
||||
/* Load SPD unique information data. */
|
||||
memset(spds, 0, sizeof(spds));
|
||||
@ -353,8 +353,8 @@ static void init_dram_ddr3(int min_tck, int s3resume)
|
||||
/* Failed S3 resume, reset to come up cleanly */
|
||||
system_reset();
|
||||
}
|
||||
/* no need to erase bad mrc cache here, it gets overwritten on
|
||||
* successful boot. */
|
||||
/* No need to erase bad MRC cache here, it gets overwritten on a
|
||||
successful boot */
|
||||
printk(BIOS_ERR, "Stored timings are invalid !\n");
|
||||
fast_boot = 0;
|
||||
}
|
||||
@ -377,7 +377,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
|
||||
}
|
||||
|
||||
if (err) {
|
||||
/* fallback: disable failing channel */
|
||||
/* Fallback: disable failing channel */
|
||||
printk(BIOS_ERR, "RAM training failed, trying fallback.\n");
|
||||
printram("Disable failing channel.\n");
|
||||
|
||||
@ -392,7 +392,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
|
||||
/* Reset DDR3 frequency */
|
||||
dram_find_spds_ddr3(spds, &ctrl);
|
||||
|
||||
/* disable failing channel */
|
||||
/* Disable failing channel */
|
||||
disable_channel(&ctrl, GET_ERR_CHANNEL(err));
|
||||
|
||||
err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);
|
||||
|
||||
Reference in New Issue
Block a user