nb/intel/sandybridge: Tidy up code and comments

- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)

With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.

Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-03-16 23:17:32 +01:00
committed by Matt DeVillier
parent 1cd7d3e664
commit 7c49cb8f9c
22 changed files with 2029 additions and 1998 deletions

View File

@ -35,47 +35,48 @@
#define MRC_CACHE_VERSION 1
/* FIXME: no ECC support. */
/* FIXME: no support for 3-channel chipsets. */
/* FIXME: no ECC support */
/* FIXME: no support for 3-channel chipsets */
static const char *ecc_decoder[] = {
"inactive",
"active on IO",
"disabled on IO",
"active"
"active",
};
static void wait_txt_clear(void)
{
struct cpuid_result cp;
struct cpuid_result cp = cpuid_ext(1, 0);
cp = cpuid_ext(0x1, 0x0);
/* Check if TXT is supported? */
if (!(cp.ecx & 0x40))
/* Check if TXT is supported */
if (!(cp.ecx & (1 << 6)))
return;
/* Some TXT public bit. */
/* Some TXT public bit */
if (!(read32((void *)0xfed30010) & 1))
return;
/* Wait for TXT clear. */
while (!(read8((void *)0xfed40000) & (1 << 7)));
/* Wait for TXT clear */
while (!(read8((void *)0xfed40000) & (1 << 7)))
;
}
/*
* Disable a channel in ramctr_timing.
*/
static void disable_channel(ramctr_timing *ctrl, int channel) {
/* Disable a channel in ramctr_timing */
static void disable_channel(ramctr_timing *ctrl, int channel)
{
ctrl->rankmap[channel] = 0;
memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0]));
ctrl->channel_size_mb[channel] = 0;
ctrl->cmd_stretch[channel] = 0;
ctrl->mad_dimm[channel] = 0;
memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));
ctrl->cmd_stretch[channel] = 0;
ctrl->mad_dimm[channel] = 0;
memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0]));
memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0]));
}
/*
* Fill cbmem with information for SMBIOS type 17.
*/
/* Fill cbmem with information for SMBIOS type 17 */
static void fill_smbios17(ramctr_timing *ctrl)
{
int channel, slot;
@ -89,54 +90,50 @@ static void fill_smbios17(ramctr_timing *ctrl)
}
}
/*
* Dump in the log memory controller configuration as read from the memory
* controller registers.
*/
#define ON_OFF(val) (((val) & 1) ? "on" : "off")
/* Print the memory controller configuration as read from the memory controller registers. */
static void report_memory_config(void)
{
u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
int i, refclk;
int i;
addr_decoder_common = MCHBAR32(MAD_CHNL);
addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0);
addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1);
refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
const int refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 0) & 3,
(addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3);
for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
u32 ch_conf = addr_decode_ch[i];
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i,
ch_conf);
printk(BIOS_DEBUG, " ECC %s\n",
ecc_decoder[(ch_conf >> 24) & 3]);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n",
((ch_conf >> 22) & 1) ? "on" : "off");
printk(BIOS_DEBUG, " rank interleave %s\n",
((ch_conf >> 21) & 1) ? "on" : "off");
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ON_OFF(ch_conf >> 22));
printk(BIOS_DEBUG, " rank interleave %s\n", ON_OFF(ch_conf >> 21));
printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n",
((ch_conf >> 0) & 0xff) * 256,
((ch_conf >> 0) & 0xff) * 256,
((ch_conf >> 19) & 1) ? 16 : 8,
((ch_conf >> 17) & 1) ? "dual" : "single",
((ch_conf >> 16) & 1) ? "" : ", selected");
printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n",
((ch_conf >> 8) & 0xff) * 256,
((ch_conf >> 8) & 0xff) * 256,
((ch_conf >> 20) & 1) ? 16 : 8,
((ch_conf >> 18) & 1) ? "dual" : "single",
((ch_conf >> 16) & 1) ? ", selected" : "");
}
}
#undef ON_OFF
/*
* Return CRC16 match for all SPDs.
*/
/* Return CRC16 match for all SPDs */
static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
{
int channel, slot, spd_slot;
@ -146,7 +143,7 @@ static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
match &= ctrl->spd_crc[channel][slot] ==
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
}
}
return match;
@ -166,7 +163,7 @@ void read_spd(spd_raw_data * spd, u8 addr, bool id_only)
static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
{
int dimms = 0, dimms_on_channel;
int dimms = 0, ch_dimms;
int channel, slot, spd_slot;
dimm_info *dimm = &ctrl->info;
@ -178,53 +175,55 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
FOR_ALL_CHANNELS {
ctrl->channel_size_mb[channel] = 0;
dimms_on_channel = 0;
/* count dimms on channel */
ch_dimms = 0;
/* Count dimms on channel */
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
printk(BIOS_DEBUG,
"SPD probe channel%d, slot%d\n", channel, slot);
printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3)
dimms_on_channel++;
ch_dimms++;
}
for (slot = 0; slot < NUM_SLOTS; slot++) {
spd_slot = 2 * channel + slot;
printk(BIOS_DEBUG,
"SPD probe channel%d, slot%d\n", channel, slot);
printk(BIOS_DEBUG, "SPD probe channel%d, slot%d\n", channel, slot);
/* search for XMP profile */
spd_xmp_decode_ddr3(&dimm->dimm[channel][slot],
spd[spd_slot],
/* Search for XMP profile */
spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot],
DDR3_XMP_PROFILE_1);
if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
printram("No valid XMP profile found.\n");
spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
} else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) {
printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
dimm->dimm[channel][slot].dimms_per_channel,
dimms_on_channel);
} else if (ch_dimms > dimm->dimm[channel][slot].dimms_per_channel) {
printram(
"XMP profile supports %u DIMMs, but %u DIMMs are installed.\n",
dimm->dimm[channel][slot].dimms_per_channel, ch_dimms);
if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS))
printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n");
printk(BIOS_WARNING,
"XMP maximum DIMMs will be ignored.\n");
else
spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
spd_decode_ddr3(&dimm->dimm[channel][slot],
spd[spd_slot]);
} else if (dimm->dimm[channel][slot].voltage != 1500) {
/* TODO: support other DDR3 voltage than 1500mV */
/* TODO: Support DDR3 voltages other than 1500mV */
printram("XMP profile's requested %u mV is unsupported.\n",
dimm->dimm[channel][slot].voltage);
spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]);
}
/* fill in CRC16 for MRC cache */
/* Fill in CRC16 for MRC cache */
ctrl->spd_crc[channel][slot] =
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data));
if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
// set dimm invalid
dimm->dimm[channel][slot].ranks = 0;
/* Mark DIMM as invalid */
dimm->dimm[channel][slot].ranks = 0;
dimm->dimm[channel][slot].size_mb = 0;
continue;
}
@ -232,30 +231,40 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
dram_print_spd_ddr3(&dimm->dimm[channel][slot]);
dimms++;
ctrl->rank_mirror[channel][slot * 2] = 0;
ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored;
ctrl->rank_mirror[channel][slot * 2 + 1] =
dimm->dimm[channel][slot].flags.pins_mirrored;
ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb;
ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr;
ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh;
ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot);
printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n",
channel, ctrl->rankmap[channel]);
ctrl->extended_temperature_range &=
dimm->dimm[channel][slot].flags.ext_temp_refresh;
ctrl->rankmap[channel] |=
((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot);
printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel,
ctrl->rankmap[channel]);
}
if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc)
&& dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) {
if ((ctrl->rankmap[channel] & 0x03) && (ctrl->rankmap[channel] & 0x0c)
&& dimm->dimm[channel][0].reference_card <= 5
&& dimm->dimm[channel][1].reference_card <= 5) {
const int ref_card_offset_table[6][6] = {
{ 0, 0, 0, 0, 2, 2, },
{ 0, 0, 0, 0, 2, 2, },
{ 0, 0, 0, 0, 2, 2, },
{ 0, 0, 0, 0, 1, 1, },
{ 2, 2, 2, 1, 0, 0, },
{ 2, 2, 2, 1, 0, 0, },
{ 0, 0, 0, 0, 2, 2 },
{ 0, 0, 0, 0, 2, 2 },
{ 0, 0, 0, 0, 2, 2 },
{ 0, 0, 0, 0, 1, 1 },
{ 2, 2, 2, 1, 0, 0 },
{ 2, 2, 2, 1, 0, 0 },
};
ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card]
[dimm->dimm[channel][1].reference_card];
} else
ctrl->ref_card_offset[channel] = ref_card_offset_table
[dimm->dimm[channel][0].reference_card]
[dimm->dimm[channel][1].reference_card];
} else {
ctrl->ref_card_offset[channel] = 0;
}
}
if (!dimms)
@ -265,29 +274,24 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
static void save_timings(ramctr_timing *ctrl)
{
/* Save the MRC S3 restore data to cbmem */
mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl,
sizeof(*ctrl));
mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl));
}
static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot,
int s3_resume, int me_uma_size)
static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
{
if (ctrl->sandybridge)
return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size);
return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size);
else
return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size);
return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size);
}
static void init_dram_ddr3(int min_tck, int s3resume)
{
int me_uma_size;
int cbmem_was_inited;
int me_uma_size, cbmem_was_inited, fast_boot, err;
ramctr_timing ctrl;
int fast_boot;
spd_raw_data spds[4];
struct region_device rdev;
ramctr_timing *ctrl_cached;
int err;
u32 cpu;
MCHBAR32(SAPMCTL) |= 1;
@ -298,17 +302,14 @@ static void init_dram_ddr3(int min_tck, int s3resume)
printk(BIOS_DEBUG, "Starting native Platform init\n");
u32 reg_5d10;
wait_txt_clear();
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
MCHBAR32(0x5d10) = 0;
/* Need reset. */
const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000
if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) {
MCHBAR32(SSKPD) = 0;
/* Need reset */
system_reset();
}
@ -316,10 +317,9 @@ static void init_dram_ddr3(int min_tck, int s3resume)
early_init_dmi();
early_thermal_init();
/* try to find timings in MRC cache */
int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA,
MRC_CACHE_VERSION, &rdev);
if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) {
/* Try to find timings in MRC cache */
err = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev);
if (err || (region_device_sz(&rdev) < sizeof(ctrl))) {
if (s3resume) {
/* Failed S3 resume, reset to come up cleanly */
system_reset();
@ -329,7 +329,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
ctrl_cached = rdev_mmap_full(&rdev);
}
/* verify MRC cache for fast boot */
/* Verify MRC cache for fast boot */
if (!s3resume && ctrl_cached) {
/* Load SPD unique information data. */
memset(spds, 0, sizeof(spds));
@ -353,8 +353,8 @@ static void init_dram_ddr3(int min_tck, int s3resume)
/* Failed S3 resume, reset to come up cleanly */
system_reset();
}
/* no need to erase bad mrc cache here, it gets overwritten on
* successful boot. */
/* No need to erase bad MRC cache here, it gets overwritten on a
successful boot */
printk(BIOS_ERR, "Stored timings are invalid !\n");
fast_boot = 0;
}
@ -377,7 +377,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
}
if (err) {
/* fallback: disable failing channel */
/* Fallback: disable failing channel */
printk(BIOS_ERR, "RAM training failed, trying fallback.\n");
printram("Disable failing channel.\n");
@ -392,7 +392,7 @@ static void init_dram_ddr3(int min_tck, int s3resume)
/* Reset DDR3 frequency */
dram_find_spds_ddr3(spds, &ctrl);
/* disable failing channel */
/* Disable failing channel */
disable_channel(&ctrl, GET_ERR_CHANNEL(err));
err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size);