haswell: use tsc for udelay()
Instead of using the local apic timer for udelay() use the tsc. That way SMM, romstage, and ramstage all use the same delay functionality. Change-Id: I024de5af01eb5de09318e13d0428ee98c132f594 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/3169 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -8,7 +8,8 @@ config CPU_SPECIFIC_OPTIONS
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def_bool y
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def_bool y
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select SMP
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select SMP
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select SSE2
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select SSE2
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select UDELAY_LAPIC
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select UDELAY_TSC
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select TSC_CONSTANT_RATE
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select SMM_TSEG
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select SMM_TSEG
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select SMM_MODULES
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select SMM_MODULES
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select RELOCATABLE_MODULES
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select RELOCATABLE_MODULES
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@ -1,7 +1,9 @@
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ramstage-y += haswell_init.c
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ramstage-y += haswell_init.c
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subdirs-y += ../../x86/name
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subdirs-y += ../../x86/name
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ramstage-y += mp_init.c
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ramstage-y += mp_init.c
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ramstage-y += tsc_freq.c
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romstage-y += romstage.c
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romstage-y += romstage.c
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romstage-y += tsc_freq.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
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@ -10,6 +12,7 @@ ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
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cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
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cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc
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31
src/cpu/intel/haswell/tsc_freq.c
Normal file
31
src/cpu/intel/haswell/tsc_freq.c
Normal file
@ -0,0 +1,31 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/tsc.h>
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#include "cpu/intel/haswell/haswell.h"
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unsigned long tsc_freq_mhz(void)
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{
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msr_t platform_info;
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platform_info = rdmsr(MSR_PLATFORM_INFO);
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return HASWELL_BCLK * ((platform_info.lo >> 8) & 0xff);
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}
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@ -29,7 +29,6 @@ romstage-y += early_init.c
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romstage-y += report_platform.c
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romstage-y += report_platform.c
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romstage-y += ../../../arch/x86/lib/walkcbfs.S
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romstage-y += ../../../arch/x86/lib/walkcbfs.S
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smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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# We don't ship that, but booting without it is bound to fail
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# We don't ship that, but booting without it is bound to fail
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@ -1,63 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <delay.h>
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#include <stdint.h>
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#include <cpu/x86/tsc.h>
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#include <cpu/x86/msr.h>
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#include "cpu/intel/haswell/haswell.h"
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/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
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static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
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{
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tsc->lo = (a & 0xffff) * (b & 0xffff);
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tsc->hi = ((tsc->lo >> 16)
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+ ((a & 0xffff) * (b >> 16))
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+ ((b & 0xffff) * (a >> 16)));
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tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
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tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
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}
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void udelay(u32 us)
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{
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u32 dword;
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tsc_t tsc, tsc1, tscd;
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msr_t msr;
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u32 divisor;
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u32 d; /* ticks per us */
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msr = rdmsr(MSR_PLATFORM_INFO);
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divisor = (msr.lo >> 8) & 0xff;
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d = HASWELL_BCLK * divisor;
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multiply_to_tsc(&tscd, us, d);
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tsc1 = rdtsc();
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dword = tsc1.lo + tscd.lo;
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if ((dword < tsc1.lo) || (dword < tscd.lo)) {
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tsc1.hi++;
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}
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tsc1.lo = dword;
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tsc1.hi += tscd.hi;
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do {
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tsc = rdtsc();
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} while ((tsc.hi < tsc1.hi)
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|| ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
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}
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