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1201_ht_bus0_dev0_fidvid_core.diff

Browse Source 
https://openbios.org/roundup/linuxbios/issue41
Lord have mercy upon us.




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2118 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2005-12-02 21:52:30 +00:00
parent c2455dc0ce
commit 7ce8c54e2b
41 changed files with 1315 additions and 342 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/amd/car/clear_1m_ram.c
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@@ -1,5 +1,7 @@
/* by yhlu 6.2005 */
/* be warned, this file will be used core 0/node 0 only */
static inline __attribute__((always_inline)) void clear_1m_ram(void)
{
__asm__ volatile (
/* disable cache */
@@ -51,3 +53,4 @@
"invd\n\t"
);
}

33
src/cpu/amd/car/copy_and_run.c
View File

@@ -28,10 +28,18 @@
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
#endif
static inline void print_debug_cp_run(const char *strval, uint32_t val)
{
#if CONFIG_USE_INIT
printk_debug("%s%08x\r\n", strval, val);
#else
print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
#endif
}
static void copy_and_run(unsigned cpu_reset)
{
uint8_t *src, *dst;
unsigned long dst_len;
unsigned long ilen = 0, olen = 0, last_m_off = 1;
uint32_t bb = 0;
unsigned bc = 0;
@@ -44,9 +52,9 @@ static void copy_and_run(unsigned cpu_reset)
"leal _iseg, %1\n\t"
"leal _eiseg, %2\n\t"
"subl %1, %2\n\t"
: "=a" (src), "=b" (dst), "=c" (dst_len)
: "=a" (src), "=b" (dst), "=c" (olen)
);
memcpy(src, dst, dst_len);
memcpy(src, dst, olen);
#else
__asm__ volatile (
@@ -55,13 +63,10 @@ static void copy_and_run(unsigned cpu_reset)
: "=a" (src) , "=b" (dst)
);
#if CONFIG_USE_INIT
printk_debug("src=%08x\r\n",src);
printk_debug("dst=%08x\r\n",dst);
#else
print_debug("src="); print_debug_hex32(src); print_debug("\r\n");
print_debug("dst="); print_debug_hex32(dst); print_debug("\r\n");
#endif
print_debug_cp_run("src=",(uint32_t)src);
print_debug_cp_run("dst=",(uint32_t)dst);
// dump_mem(src, src+0x100);
for(;;) {
unsigned int m_off, m_len;
@@ -105,11 +110,9 @@ static void copy_and_run(unsigned cpu_reset)
}
#endif
// dump_mem(dst, dst+0x100);
#if CONFIG_USE_INIT
printk_debug("linxbios_ram.bin length = %08x\r\n", olen);
#else
print_debug("linxbios_ram.bin length = "); print_debug_hex32(olen); print_debug("\r\n");
#endif
print_debug_cp_run("linxbios_ram.bin length = ", olen);
print_debug("Jumping to LinuxBIOS.\r\n");
if(cpu_reset == 1 ) {

5
src/cpu/amd/car/disable_cache_as_ram.c
View File

@@ -1,11 +1,12 @@
/* by yhlu 6.2005 */
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
__asm__ volatile (
/*
FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
It is only needed if we want to go back
*/
/* We don't need cache as ram for now on */
/* disable cache */
"movl %cr0, %eax\n\t"
@@ -42,5 +43,5 @@
"movl %cr0, %eax\n\t"
"andl $0x9fffffff,%eax\n\t"
"movl %eax, %cr0\n\t"
);
}

6
src/cpu/amd/dualcore/Config.lb
View File

@@ -1,5 +1 @@
uses CONFIG_LOGICAL_CPUS
if CONFIG_LOGICAL_CPUS
object amd_sibling.o
end
object amd_sibling.o

78
src/cpu/amd/dualcore/dualcore.c
View File

@@ -1,31 +1,72 @@
/* 2004.12 yhlu add dual core support */
#ifndef SET_NB_CFG_54
#define SET_NB_CFG_54 1
#endif
#include "cpu/amd/dualcore/dualcore_id.c"
static inline unsigned get_core_num_in_bsp(unsigned nodeid)
{
return ((pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8)>>12) & 3);
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0xe8);
dword >>= 12;
dword &= 3;
return dword;
}
static inline uint8_t set_apicid_cpuid_lo(void)
#if SET_NB_CFG_54 == 1
static inline uint8_t set_apicid_cpuid_lo(void)
{
if(is_cpu_pre_e0()) return 0; // pre_e0 can not be set
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
return 0;
}
// set the NB_CFG[54]=1; why the OS will be happy with that ???
// set the NB_CFG[54]=1; why the OS will be happy with that ???
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
wrmsr(NB_CFG_MSR, msr);
return 1;
}
#else
static inline void set_apicid_cpuid_lo(void) { }
#endif
static inline void real_start_other_core(unsigned nodeid)
{
uint32_t dword;
// set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4 accesses and error logging to core0
dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44);
dword |= 1<<27; // NbMcaToMstCpuEn bit
pci_write_config32(PCI_DEV(0, 0x18+nodeid, 3), 0x44, dword);
// set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
dword = pci_read_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68);
dword |= 1<<5;
pci_write_config32(PCI_DEV(0, 0x18+nodeid, 0), 0x68, dword);
}
//it is running on core0 of node0
static inline void start_other_cores(void)
{
unsigned nodes;
unsigned nodeid;
if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // disable dual_core
return;
}
nodes = get_nodes();
for(nodeid=0; nodeid<nodes; nodeid++) {
if( get_core_num_in_bsp(nodeid) > 0) {
real_start_other_core(nodeid);
}
}
}
#if USE_DCACHE_RAM == 0
static void do_k8_init_and_stop_secondaries(void)
{
@@ -62,7 +103,26 @@ static void do_k8_init_and_stop_secondaries(void)
pci_write_config32(dev_f0, 0x68, val);
/* Set the lapicid */
lapic_write(LAPIC_ID,(0x10 + id.coreid*0x10 + id.nodeid) << 24);
#if (ENABLE_APIC_EXT_ID == 1)
unsigned initial_apicid = get_initial_apicid();
#if LIFT_BSP_APIC_ID == 0
if( initial_apicid != 0 ) // other than bsp
#endif
{
/* use initial apic id to lift it */
uint32_t dword = lapic_read(LAPIC_ID);
dword &= ~(0xff<<24);
dword |= (((initial_apicid + APIC_ID_OFFSET) & 0xff)<<24);
lapic_write(LAPIC_ID, dword);
}
#if LIFT_BSP_APIC_ID == 1
bsp_apicid += APIC_ID_OFFSET;
#endif
#endif
/* Remember the cpuid */
if (id.coreid == 0) {

20
src/cpu/amd/dualcore/dualcore_id.c
View File

@@ -1,26 +1,27 @@
/* 2004.12 yhlu add dual core support */
#include <arch/cpu.h>
#include <cpu/amd/dualcore.h>
#ifdef __ROMCC__
#include <cpu/amd/model_fxx_msr.h>
#endif
static inline unsigned int read_nb_cfg_54(void)
//called by bus_cpu_scan too
unsigned int read_nb_cfg_54(void)
{
msr_t msr;
msr = rdmsr(NB_CFG_MSR);
return ( ( msr.hi >> (54-32)) & 1);
}
struct node_core_id {
unsigned nodeid:8;
unsigned coreid:8;
};
static inline unsigned get_initial_apicid(void)
static inline unsigned get_initial_apicid(void)
{
return ((cpuid_ebx(1) >> 24) & 0xf);
}
static inline struct node_core_id get_node_core_id(unsigned nb_cfg_54) {
//called by amd_siblings too
struct node_core_id get_node_core_id(unsigned nb_cfg_54)
{
struct node_core_id id;
// get the apicid via cpuid(1) ebx[27:24]
if( nb_cfg_54) {
@@ -45,6 +46,7 @@ static inline unsigned get_core_num(void)
}
static inline struct node_core_id get_node_core_id_x(void) {
return get_node_core_id( read_nb_cfg_54() );
return get_node_core_id( read_nb_cfg_54() ); // for pre_e0() nb_cfg_54 always be 0
}

3
src/cpu/amd/model_fxx/apic_timer.c
View File

@@ -7,10 +7,13 @@ void init_timer(void)
{
/* Set the apic timer to no interrupts and periodic mode */
lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
/* Set the divider to 1, no divider */
lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
/* Set the initial counter to 0xffffffff */
lapic_write(LAPIC_TMICT, 0xffffffff);
}
void udelay(unsigned usecs)

396
src/cpu/amd/model_fxx/fidvid.c Normal file
View File

@@ -0,0 +1,396 @@
#if K8_SET_FIDVID == 1
#define K8_SET_FIDVID_DEBUG 0
#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
#if CONFIG_USE_INIT==1
printk_debug("%s%x\r\n", str, val);
#else
print_debug(str); print_debug_hex32(val); print_debug("\r\n");
#endif
#endif
}
static inline void print_debug_fv_8(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
#if CONFIG_USE_INIT==1
printk_debug("%s%02x\r\n", str, val);
#else
print_debug(str); print_debug_hex8(val); print_debug("\r\n");
#endif
#endif
}
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
{
#if K8_SET_FIDVID_DEBUG == 1
#if CONFIG_USE_INIT==1
printk_debug("%s%x%x\r\n", str, val, val2);
#else
print_debug(str); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
#endif
#endif
}
static void enable_fid_change(void)
{
uint32_t dword;
unsigned nodes;
int i;
nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
for(i=0; i<nodes; i++) {
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xd8);
dword &= 0x8ff00000;
dword |= (2<<28) | (0x02710);
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd8, dword);
dword = 0x04e2a707;
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd4, dword);
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 2), 0x94);
dword |= (1<<14);// disable the DRAM interface at first, it will be enabled by raminit again
pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword);
dword = 0x23070000; //enable FID/VID change
// dword = 0x00070000; //enable FID/VID change
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword);
dword = 0x00132113;
pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword);
}
}
static unsigned set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
{
//for (cur, new) there is one <1600MHz x8 to find out next_fid
const static uint8_t next_fid_a[] = {
/* x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 */ // 0:x4, 2:x5....BASE=4, MIN=4, MAX=25, INC=2 result = (xX-BASE)*INC
/* x4 */ 0, 9, 9, 8, 9, 9, 9, 9, 9, 9, 9, 9,
/* x5 */ 9, 0, 11, 11, 9, 9, 10, 11, 11, 11, 11, 11,
/* x6 */ 11, 11, 0, 13, 11, 11, 11, 11, 12, 13, 13, 13,
/* x7 */ 13, 13, 13, 0, 13, 13, 13, 13, 13, 13, 14, 15,
/* x8 */ 4, 9, 9, 9, 0, 9, 9, 9, 9, 9, 9, 9,
/* x9 */ 4, 5, 10, 10, 8, 0, 0, 0, 0, 0, 0, 0,
/*x10 */ 9, 5, 11, 11, 9, 0, 0, 0, 0, 0, 0, 0,
/*x11 */ 10, 5, 6, 12, 10, 0, 0, 0, 0, 0, 0, 0,
/*x12 */ 11, 11, 6, 13, 11, 0, 0, 0, 0, 0, 0, 0,
/*x13 */ 12, 12, 6, 7, 12, 0, 0, 0, 0, 0, 0, 0,
/*x14 */ 13, 13, 13, 7, 13, 0, 0, 0, 0, 0, 0, 0,
/*x15 */ 14, 14, 14, 7, 14, 0, 0, 0, 0, 0, 0, 0,
};
msr_t msr;
uint32_t vid;
uint32_t fid;
uint32_t vid_max;
uint32_t fid_max;
uint32_t vid_cur;
uint32_t fid_cur;
unsigned apicidx;
int steps;
int loop;
apicidx = lapicid();
if(apicid!=apicidx) {
#if CONFIG_USE_INIT == 1
printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
#else
print_err("wrong apicid, we want change "); print_err_hex8(apicid); print_err(" but it is "); print_err_hex8(apicidx); print_err("\r\n");
#endif
return fidvid;
}
fid = (fidvid >> 8) & 0x3f;
vid = (fidvid >> 16) & 0x3f;
msr = rdmsr(0xc0010042);
vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f;
if((vid_cur==vid) && (fid_cur==fid)) return fidvid;
vid_max = (msr.hi>>(48-32)) & 0x3f;
fid_max = (msr.lo>>16) & 0x3f;
//set vid to max
msr.hi = 1;
msr.lo = (vid_max<<8) | (fid_cur);
msr.lo |= (1<<16); // init changes
wrmsr(0xc0010041, msr);
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
if(!(msr.lo & (1<<31))) break;
}
vid_cur = msr.hi & 0x3f;
steps = 8; //??
while((fid_cur!=fid) && (steps-->0)) {
uint32_t fid_temp;
if((fid_cur > (8-4)*2) && (fid> (8-4)*2)) {
if(fid_cur<fid) {
fid_temp = fid_cur + 2;
} else {
fid_temp = fid_cur - 2;
}
}
else { //there is one < 8, So we need to lookup the table to find the fid_cur
int temp;
temp = next_fid_a[(fid_cur/2)*12+(fid/2)];
if(temp <= 0) break;
fid_temp = (temp-4) * 2;
}
if(fid_temp>fid_max) break;
fid_cur = fid_temp;
//set target fid
msr.hi = (100000/5);
msr.lo = (vid_cur<<8) | fid_cur;
msr.lo |= (1<<16); // init changes
wrmsr(0xc0010041, msr);
#if K8_SET_FIDVID_DEBUG == 1
if(showmessage) {
print_debug_fv_8("\tapicid in set_fidvid = ", apicid);
print_debug_fv_64("ctrl msr fid, vid ", msr.hi, msr.lo);
}
#endif
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
if(!(msr.lo & (1<<31))) break;
}
fid_cur = msr.lo & 0x3f;
#if K8_SET_FIDVID_DEBUG == 1
if(showmessage) {
print_debug_fv_64("status msr fid, vid ", msr.hi, msr.lo);
}
#endif
}
//set vid to final
msr.hi = 1;
msr.lo = (vid<<8) | (fid_cur);
msr.lo |= (1<<16); // init changes
wrmsr(0xc0010041, msr);
for(loop=0;loop<100000;loop++){
msr = rdmsr(0xc0010042);
if(!(msr.lo & (1<<31))) break;
}
vid_cur = msr.hi & 0x3f;
fidvid = (vid_cur<< 16) | (fid_cur<<8);
if(showmessage) {
if((fid!=fid_cur) || (vid!=vid_cur)) {
print_err("set fidvid failed\r\n");
}
}
return fidvid;
}
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid)
{
uint32_t send;
uint32_t readback;
msr_t msr;
uint32_t vid_cur;
uint32_t fid_cur;
int loop;
msr = rdmsr(0xc0010042);
send = ((msr.lo>>16) & 0x3f) << 8; //max fid
send |= ((msr.hi>>(48-32)) & 0x3f) << 16; //max vid
send |= (apicid<<24); // ap apicid
vid_cur = msr.hi & 0x3f;
fid_cur = msr.lo & 0x3f;
// set to current
msr.hi = 1;
msr.lo = (vid_cur<<8) | (fid_cur);
wrmsr(0xc0010041, msr);
wait_cpu_state(bsp_apicid, 1);
//send signal to BSP about this AP max fid and vid
lapic_write(LAPIC_MSG_REG, send | 1); //AP at state 1 that sent our fid and vid
// wait_cpu_state(bsp_apicid, 2);// don't need we can use apicid directly
loop = 100000;
while(--loop>0) {
//remote read BSP signal that include vid and fid that need to set
if(lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
if(((readback>>24) & 0xff) == apicid) break; // it is this cpu turn
}
if(loop>0) {
readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP
//send signal to BSP that this AP fid/vid is set // allow to change state2 is together with apicid
send = (apicid<<24) | (readback & 0x00ffff00); // AP at state that We set the requested fid/vid
}
lapic_write(LAPIC_MSG_REG, send | 2);
wait_cpu_state(bsp_apicid, 3);
}
static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx)
{
/* FIXME: need to check the change path to verify if it is reachable when common fid is small than 1.6G */
if((fidvid & 0xff00)<=(fidvidx & 0xff00)) {
return fidvid;
}
else {
return fidvidx;
}
}
struct fidvid_st {
unsigned common_fidvid;
};
static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp )
{
unsigned readback;
struct fidvid_st *fvp = gp;
int loop;
print_debug_fv("state 1: ap_apicid=", ap_apicid);
loop = 100000;
while(--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
if((readback & 0xff) == 1) break; //target ap is in stage 1
}
print_debug_fv("\treadback=", readback);
fvp->common_fidvid = calc_common_fidvid(fvp->common_fidvid, readback & 0xffff00);
print_debug_fv("\tcommon_fidvid=", fvp->common_fidvid);
}
static void init_fidvid_bsp_stage2(unsigned ap_apicid, void *gp)
{
unsigned readback;
struct fidvid_st *fvp = gp;
int loop;
print_debug_fv("state 2: ap_apicid=", ap_apicid);
lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2); // all set to state2
loop = 100000;
while(--loop > 0) {
if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) continue;
if((readback & 0xff) == 2) break; // target ap is stage 2, and it'd FID has beed set
}
print_debug_fv("\treadback=", readback);
}
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st {
unsigned num;
unsigned apicid[16]; // 8 way dual core need 16
/* FIXME: 32 node quad core, may need 128 */
};
static void store_ap_apicid(unsigned ap_apicid, void *gp)
{
struct ap_apicid_st *p = gp;
p->apicid[p->num++] = ap_apicid;
}
#endif
static void init_fidvid_bsp(unsigned bsp_apicid)
{
uint32_t vid_max;
uint32_t fid_max;
struct fidvid_st fv;
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
struct ap_apicid_st ap_apicidx;
unsigned i;
#endif
msr_t msr;
msr = rdmsr(0xc0010042);
fid_max = ((msr.lo>>16) & 0x3f); //max fid
vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid
fv.common_fidvid = (fid_max<<8)|(vid_max<<16);
// for all APs (We know the APIC ID of all APs even the APIC ID is lifted)
// remote read from AP about max fid/vid
//let all ap trains to state 1
lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 1);
// calculate the common max fid/vid that could be used for all APs and BSP
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
ap_apicidx.num = 0;
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx);
for(i=0;i<ap_apicidx.num;i++) {
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv);
#endif
// set BSP fid and vid
print_debug_fv("bsp apicid=", bsp_apicid);
fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1);
print_debug_fv("common_fidvid=", fv.common_fidvid);
//for all APs ( We know the APIC ID of all AP even the APIC ID is lifted)
// send signal to the AP it could change it's fid/vid
// remote read singnal from AP that AP is done
fv.common_fidvid &= 0xffff00;
//set state 2 allow is in init_fidvid_bsp_stage2
#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1
for(i=0;i<ap_apicidx.num;i++) {
init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv);
#endif
lapic_write(LAPIC_MSG_REG, fv.common_fidvid | (bsp_apicid<<24) | 3); // clear the state
//here wait a while, so last ap could read pack, and stop it, don't call init_timer too early or just don't use init_timer
}
#endif

35
src/cpu/amd/model_fxx/init_cpus.c
View File

@@ -1,4 +1,13 @@
//it takes the ENABLE_APIC_EXT_ID and APIC_ID_OFFSET and LIFT_BSP_APIC_ID
#ifndef K8_SET_FIDVID
#define K8_SET_FIDVID 0
#endif
#ifndef K8_SET_FIDVID_CORE0_ONLY
/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/
#define K8_SET_FIDVID_CORE0_ONLY 1
#endif
typedef void (*process_ap_t)(unsigned apicid, void *gp);
@@ -100,6 +109,10 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue)
#define LAPIC_MSG_REG 0x380
#if K8_SET_FIDVID == 1
static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
#endif
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
{
#if CONFIG_USE_INIT == 0
@@ -139,7 +152,11 @@ static void allow_all_aps_stop(unsigned bsp_apicid)
}
#if RAMINIT_SYSINFO == 1
static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo)
#else
static unsigned init_cpus(unsigned cpu_init_detectedx)
#endif
{
unsigned bsp_apicid = 0;
unsigned apicid;
@@ -193,7 +210,7 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
if (id.nodeid!=0) //all core0 except bsp
print_apicid_nodeid_coreid(apicid, id, " core0: ");
}
#if 1
#if 0
else { //all core1
print_apicid_nodeid_coreid(apicid, id, " core1: ");
}
@@ -202,11 +219,20 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
#endif
if (cpu_init_detectedx) {
#if RAMINIT_SYSINFO == 1
//We need to init sblnk and sbbusn, because it is called before ht_setup_chains_x
sysinfo->sblnk = get_sblnk();
sysinfo->sbbusn = node_link_to_bus(0, sysinfo->sblnk);
#endif
print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detect from ");
print_debug("\r\nIssuing SOFT_RESET...\r\n");
#if RAMINIT_SYSINFO == 1
soft_reset(sysinfo);
#else
soft_reset();
#endif
}
@@ -219,6 +245,13 @@ static unsigned init_cpus(unsigned cpu_init_detectedx)
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x33); // mark the cpu is started
if(apicid != bsp_apicid) {
#if K8_SET_FIDVID == 1
#if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1)
if(id.coreid == 0 ) // only need set fid for core0
#endif
init_fidvid_ap(bsp_apicid, apicid);
#endif
// We need to stop the CACHE as RAM for this CPU, really?
wait_cpu_state(bsp_apicid, 0x44);
lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu

3
src/cpu/x86/16bit/reset16.lds
View File

@@ -5,7 +5,8 @@
SECTIONS {
/* Trigger an error if I have an unuseable start address */
_ROMTOP = (_start >= 0xffff0000) ? 0xfffffff0 : 0xfffffff8;
_bogus = ASSERT(_start >= 0xffff0000, "_start to low please decrease ROM_IMAGE_SIZE");
_ROMTOP = 0xfffffff0;
. = _ROMTOP;
.reset . : {
*(.reset)

14
src/cpu/x86/32bit/entry32.lds
View File

@@ -1,14 +0,0 @@
/*
_cache_ram_seg_base = DEFINED(CACHE_RAM_BASE)? CACHE_RAM_BASE - _rodata : 0;
_cache_ram_seg_base_low = (_cache_ram_seg_base) & 0xffff;
_cache_ram_seg_base_middle = (_cache_ram_seg_base >> 16) & 0xff;
_cache_ram_seg_base_high = (_cache_ram_seg_base >> 24) & 0xff;
_rom_code_seg_base = _ltext - _text;
_rom_code_seg_base_low = (_rom_code_seg_base) & 0xffff;
_rom_code_seg_base_middle = (_rom_code_seg_base >> 16) & 0xff;
_rom_code_seg_base_high = (_rom_code_seg_base >> 24) & 0xff;
*/

20
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -227,24 +227,19 @@ int start_cpu(device_t cpu)
}
/* C entry point of secondary cpus */
// secondary_cpu_lock is used to serialize initialization of secondary CPUs
// This can be used to avoid interleaved debugging messages.
static spinlock_t secondary_cpu_lock = SPIN_LOCK_UNLOCKED;
void secondary_cpu_init(void)
{
atomic_inc(&active_cpus);
#if SERIAL_CPU_INIT == 1
spin_lock(&secondary_cpu_lock);
#if CONFIG_MAX_CPUS>2
spin_lock(&start_cpu_lock);
#endif
#endif
cpu_initialize();
#if SERIAL_CPU_INIT == 1
spin_unlock(&secondary_cpu_lock);
#if CONFIG_MAX_CPUS>2
spin_unlock(&start_cpu_lock);
#endif
#endif
atomic_dec(&active_cpus);
@@ -260,12 +255,15 @@ static void initialize_other_cpus(struct bus *cpu_bus)
if (cpu->path.type != DEVICE_PATH_APIC) {
continue;
}
if (!cpu->enabled) {
continue;
}
if (cpu->initialized) {
continue;
}
if (!start_cpu(cpu)) {
/* Record the error in cpu? */
printk_err("CPU %u would not start!\n",