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Fintek and Intel i3100 Super I/O cleanups.

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- Drop commented out "config chip.h" and a duplicate link to a datasheet.

 - F71805F -> F71805F/FG, to mention all variants.
 
 - Use u8/u16/ etc. everywhere.
 
 - Add a missing (C) line.
 
 - Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
 
 - Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
   pair on this Super I/O.
   
 - Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
   respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
   
 - i3100: Add some more comments and datasheet infos.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
2010-11-05 00:07:13 +00:00
parent e4870474b9
commit 7d3418849d
16 changed files with 72 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/superio/intel/i3100/Makefile.inc
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@@ -18,5 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
#config chip.h
ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c

21
src/superio/intel/i3100/i3100.h
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@@ -18,11 +18,30 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* Datasheet: http://www.intel.com/design/intarch/datashts/313458.htm */
/*
* Datasheet:
* - Name: Intel 3100 Chipset
* - URL: http://www.intel.com/design/intarch/datashts/313458.htm
* - PDF: http://download.intel.com/design/intarch/datashts/31345803.pdf
* - Revision / Date: 007, October 2008
* - Order number: 313458-007US
*/
#ifndef SUPERIO_INTEL_I3100_I3100_H
#define SUPERIO_INTEL_I3100_I3100_H
/*
* The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is
* very similar to a Super I/O, both in functionality and config mechanism.
*
* The SIW contains:
* - UART(s)
* - Serial interrupt controller
* - Watchdog timer (WDT)
* - LPC interface
*/
/* Logical device numbers (LDNs). */
#define I3100_SP1 0x04 /* Com1 */
#define I3100_SP2 0x05 /* Com2 */
#define I3100_WDT 0x06 /* Watchdog timer */

13
src/superio/intel/i3100/i3100_early_serial.c
View File

@@ -21,8 +21,7 @@
#include <arch/romcc_io.h>
#include "i3100.h"
static void i3100_sio_write(u8 port, u8 ldn, u8 index,
u8 value)
static void i3100_sio_write(u8 port, u8 ldn, u8 index, u8 value)
{
outb(0x07, port);
outb(ldn, port + 1);
@@ -32,21 +31,21 @@ static void i3100_sio_write(u8 port, u8 ldn, u8 index,
static void i3100_enable_serial(u8 port, u8 ldn, u16 iobase)
{
/* Enter configuration state */
/* Enter configuration state. */
outb(0x80, port);
outb(0x86, port);
/* Enable serial port */
/* Enable serial port. */
i3100_sio_write(port, ldn, 0x30, 0x01);
/* Set serial port IO region */
/* Set serial port I/O region. */
i3100_sio_write(port, ldn, 0x60, (iobase >> 8) & 0xff);
i3100_sio_write(port, ldn, 0x61, iobase & 0xff);
/* Enable device interrupts, set UART_CLK predivide to 26 */
/* Enable device interrupts, set UART_CLK predivide to 26. */
i3100_sio_write(port, 0x00, 0x29, 0x0b);
/* Exit configuration state */
/* Exit configuration state. */
outb(0x68, port);
outb(0x08, port);
}

3
src/superio/intel/i3100/superio.c
View File

@@ -43,9 +43,8 @@ static void i3100_init(device_t dev)
struct superio_intel_i3100_config *conf;
struct resource *res0;
if (!dev->enabled) {
if (!dev->enabled)
return;
}
conf = dev->chip_info;