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mb/google/brya/var/omnigul: Add fingerprint SPI

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Add fingerprint SPI, and power off FPMCU during romstage.

BUG=b:305860604, b:306320063
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot, measure evtest can detect and check device probed in kernel log

Change-Id: Ic7b9e29ca3cb9352fe098156924fde2719399a79
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit is contained in:
Jamie Chen
2023-10-17 10:55:58 +08:00
committed by Matt DeVillier
parent 312a277bf9
commit 7d3ababd71
2 changed files with 25 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/google/brya/variants/omnigul/gpio.c
View File

@@ -316,12 +316,15 @@ static const struct pad_config romstage_gpio_table[] = {
* B4 is programmed here so that it is sequenced after EN_PP3300_SSD. * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
*/ */
PAD_CFG_GPO(GPP_B4, 1, DEEP), PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* Enable touchscreen, hold in reset */ /* Enable touchscreen, hold in reset */
/* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */
PAD_CFG_GPO(GPP_C0, 1, DEEP), PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> USI_RST_L */ /* C1 : SMBDATA ==> USI_RST_L */
PAD_CFG_GPO(GPP_C1, 0, DEEP), PAD_CFG_GPO(GPP_C1, 0, DEEP),
// D1 : ISH_GP1 ==> FP_RST_ODL /
PAD_CFG_GPO(GPP_D1, 0, DEEP),
// D2 : ISH_GP2 ==> EN_FP_PWR /
PAD_CFG_GPO(GPP_D2, 0, DEEP),
}; };
const struct pad_config *variant_gpio_override_table(size_t *num) const struct pad_config *variant_gpio_override_table(size_t *num)

21
src/mainboard/google/brya/variants/omnigul/overridetree.cb
View File

@@ -4,6 +4,10 @@ fw_config
option STORAGE_UFS 1 option STORAGE_UFS 1
option STORAGE_NVME 2 option STORAGE_NVME 2
end end
field FINGERPRINT 9
option DISABLE_FP 0
option ENABLE_FP 1
end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
@@ -318,6 +322,23 @@ chip soc/intel/alderlake
device i2c 2c on end device i2c 2c on end
end end
end #I2C5 end #I2C5
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
device spi 0 hidden
probe FINGERPRINT ENABLE_FP
end
end # FPMCU
end
device ref pcie_rp8 off end device ref pcie_rp8 off end
device ref pcie_rp9 on device ref pcie_rp9 on
# Enable NVMe PCIE 9 using clk 1 # Enable NVMe PCIE 9 using clk 1