device/Kconfig: Declare MMCONF symbols' type once

Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once. Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 12:51:11 +01:00
parent 7830af3c8d
commit 7d638784a2
27 changed files with 8 additions and 35 deletions
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -513,6 +513,14 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 config MMCONF_BASE_ADDRESS
 	hex
 	depends on MMCONF_SUPPORT
 config MMCONF_BUS_NUMBER
 	int
 	depends on MMCONF_SUPPORT
 config PCI_ALLOW_BUS_MASTER
 	bool "Allow coreboot to set optional PCI bus master bits"
 	default y
--- a/src/mainboard/emulation/qemu-q35/Kconfig
+++ b/src/mainboard/emulation/qemu-q35/Kconfig
@@ -61,7 +61,6 @@ config MAINBOARD_PART_NUMBER
 	default "QEMU x86 q35/ich9"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xb0000000
 # fw_cfg tables can be larger than the default when TPM is enabled
--- a/src/northbridge/amd/agesa/family14/Kconfig
+++ b/src/northbridge/amd/agesa/family14/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
 	default 0x100000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 endif # NORTHBRIDGE_AMD_AGESA_FAMILY14
--- a/src/northbridge/amd/agesa/family15tn/Kconfig
+++ b/src/northbridge/amd/agesa/family15tn/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
 	default 0x100000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
--- a/src/northbridge/amd/agesa/family16kb/Kconfig
+++ b/src/northbridge/amd/agesa/family16kb/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
 	default 0x100000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config VGA_BIOS_ID
--- a/src/northbridge/amd/pi/00630F01/Kconfig
+++ b/src/northbridge/amd/pi/00630F01/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
 	default 0x100000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config VGA_BIOS_ID
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -11,11 +11,9 @@ config HW_MEM_HOLE_SIZEK
 	default 0x100000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config VGA_BIOS_ID
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -27,7 +27,6 @@ config VGA_BIOS_ID
 	default "8086,2a42"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
 config SMM_RESERVED_SIZE
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -34,7 +34,6 @@ config VGA_BIOS_ID
 	default "8086,0166"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
 config DCACHE_RAM_BASE
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -39,7 +39,6 @@ config I945_LVDS
 	  LVDS.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
 config OVERRIDE_CLOCK_DISABLE
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -19,7 +19,6 @@ config VBOOT
 	select TPM_STARTUP_IGNORE_POSTINIT
 config MMCONF_BUS_NUMBER
 	int
 	default 256
 config CBFS_SIZE
@@ -46,7 +45,6 @@ config DCACHE_BSP_STACK_SIZE
 	  other stages.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config INTEL_GMA_BCLV_OFFSET
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -21,7 +21,6 @@ config VGA_BIOS_ID
 	default "8086,a001"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config SMM_RESERVED_SIZE
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -86,7 +86,6 @@ config VGA_BIOS_ID
 	default "8086,0106"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xf0000000
 	help
 	  The MRC blob requires it to be at 0xf0000000.
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -23,7 +23,6 @@ config VGA_BIOS_ID
 	default "8086,2e32"
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config SMM_RESERVED_SIZE
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -114,11 +114,9 @@ config CPU_ADDR_BITS
 	default 48
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config MAX_CPUS
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -180,11 +180,9 @@ config CPU_ADDR_BITS
 	default 48
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config VERSTAGE_ADDR
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -125,11 +125,9 @@ config BOTTOMIO_POSITION
 	  ranges are present.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xF8000000
 config MMCONF_BUS_NUMBER
 	int
 	default 64
 config VGA_BIOS_ID
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -159,7 +159,6 @@ config PCR_BASE_ADDRESS
 	  This option allows you to select MMIO Base Address of sideband bus.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xc0000000
 config CPU_BCLK_MHZ
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -42,7 +42,6 @@ config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config MAX_CPUS
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -57,7 +57,6 @@ config VBOOT
 	select VBOOT_STARTS_IN_ROMSTAGE
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config MAX_CPUS
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -6,7 +6,6 @@ config SOC_INTEL_COMMON_BLOCK_SA
 if SOC_INTEL_COMMON_BLOCK_SA
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config SA_PCIEX_LENGTH
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -44,7 +44,6 @@ config CPU_SPECIFIC_OPTIONS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xe0000000
 config FSP_T_ADDR
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -127,7 +127,6 @@ config PCR_BASE_ADDRESS
 	  This option allows you to select MMIO Base Address of sideband bus.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xc0000000
 config CPU_BCLK_MHZ
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -123,7 +123,6 @@ config PCR_BASE_ADDRESS
 	  This option allows you to select MMIO Base Address of sideband bus.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xc0000000
 config CPU_BCLK_MHZ
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -127,7 +127,6 @@ config PCR_BASE_ADDRESS
 	  This option allows you to select MMIO Base Address of sideband bus.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xc0000000
 config CPU_BCLK_MHZ
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -146,7 +146,6 @@ config PCR_BASE_ADDRESS
 	  This option allows you to select MMIO Base Address of sideband bus.
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0xc0000000
 config CPU_BCLK_MHZ
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -100,7 +100,6 @@ config DCACHE_BSP_STACK_SIZE
 	default 0x10000
 config MMCONF_BASE_ADDRESS
 	hex
 	default 0x80000000
 config HEAP_SIZE