edid: Use edid_mode struct to reduce redundancy
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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committed by
Patrick Georgi
parent
a3b898aaf0
commit
7dbf9c6747
@@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid)
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/* set up hdmi_fc_invidconf */
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inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
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inv_val |= ((edid->pvsync == '+') ?
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inv_val |= ((edid->mode.pvsync == '+') ?
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HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
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HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
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inv_val |= ((edid->phsync == '+') ?
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inv_val |= ((edid->mode.phsync == '+') ?
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HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
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HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
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@@ -517,33 +517,33 @@ static void hdmi_av_composer(const struct edid *edid)
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write32(&hdmi_regs->fc_invidconf, inv_val);
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/* set up horizontal active pixel width */
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write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8);
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write32(&hdmi_regs->fc_inhactv0, edid->ha);
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write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
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write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
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/* set up vertical active lines */
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write32(&hdmi_regs->fc_invactv1, edid->va >> 8);
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write32(&hdmi_regs->fc_invactv0, edid->va);
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write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
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write32(&hdmi_regs->fc_invactv0, edid->mode.va);
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/* set up horizontal blanking pixel region width */
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write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8);
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write32(&hdmi_regs->fc_inhblank0, edid->hbl);
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write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
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write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
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/* set up vertical blanking pixel region width */
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write32(&hdmi_regs->fc_invblank, edid->vbl);
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write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
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/* set up hsync active edge delay width (in pixel clks) */
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write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8);
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write32(&hdmi_regs->fc_hsyncindelay0, edid->hso);
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write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
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write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
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/* set up vsync active edge delay (in lines) */
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write32(&hdmi_regs->fc_vsyncindelay, edid->vso);
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write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
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/* set up hsync active pulse width (in pixel clks) */
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write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8);
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write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw);
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write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
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write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
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/* set up vsync active edge delay (in lines) */
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write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw);
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write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
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}
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/* hdmi initialization step b.4 */
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@@ -613,11 +613,11 @@ static int hdmi_setup(const struct edid *edid)
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int ret;
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hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
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edid->pixel_clock, edid->ha, edid->va);
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edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
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hdmi_av_composer(edid);
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ret = hdmi_phy_init(edid->pixel_clock);
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ret = hdmi_phy_init(edid->mode.pixel_clock);
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if (ret)
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return ret;
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@@ -625,7 +625,7 @@ static int hdmi_setup(const struct edid *edid)
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hdmi_audio_fifo_reset();
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hdmi_audio_set_format();
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hdmi_audio_set_samplerate(edid->pixel_clock);
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hdmi_audio_set_samplerate(edid->mode.pixel_clock);
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hdmi_video_packetize();
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hdmi_video_csc();
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