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mb/clevo/kbl-u: Move memory init config to variant level

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Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.

Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Felix Singer
2021-01-06 03:54:47 +00:00
committed by Michael Niewöhner
parent 8434d92c30
commit 7dc57159fe
4 changed files with 50 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/clevo/kbl-u/Makefile.inc
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@@ -5,6 +5,8 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c

8
src/mainboard/clevo/kbl-u/include/variant/romstage.h Normal file
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@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_ROMSTAGE_H
#define VARIANT_ROMSTAGE_H
void variant_configure_fspm(FSPM_UPD *memupd);
#endif

32
src/mainboard/clevo/kbl-u/romstage.c
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@@ -1,37 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/romstage.h>
#include <spd_bin.h>
#include <string.h>
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
{
const u16 RcompResistor[3] = {121, 81, 100};
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
}
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
{
const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
}
#include <variant/romstage.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
struct spd_block blk = {
.addr_map = {0x50, 0x52},
};
get_spd_smbus(&blk);
dump_spd_info(&blk);
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mem_cfg->DqPinsInterleaved = TRUE;
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
variant_configure_fspm(mupd);
}

38
src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c Normal file
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@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <fsp/api.h>
#include <spd_bin.h>
#include <string.h>
#include <variant/romstage.h>
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
{
const u16 RcompResistor[3] = {121, 81, 100};
memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
}
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
{
const u16 RcompTarget[5] = {100, 40, 20, 20, 26};
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
}
void variant_configure_fspm(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
struct spd_block blk = {
.addr_map = {0x50, 0x52},
};
get_spd_smbus(&blk);
dump_spd_info(&blk);
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
mem_cfg->DqPinsInterleaved = TRUE;
mem_cfg->MemorySpdDataLen = blk.len;
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
}