Documentation: Add the x86 FSP Binary
Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13442 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@@ -70,9 +70,62 @@
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<li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
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<li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
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<li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
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<li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
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</ol>
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<hr>
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<table border="1">
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<tr bgcolor="#c0ffc0">
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<th colspan=3><h1>Features</h1></th>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>SoC</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>Cache-as-RAM</td>
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<td>
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<a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
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FSP binary:
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
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Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
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called from
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
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Disable: FSP 1.1 TempRamExit called from
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
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</td>
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<td>FindFSP: POST code 0x90
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(<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
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is displayed<br>
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Enable: POST code
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
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is displayed<br>
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Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
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</td>
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</tr>
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<tr bgcolor="#c0ffc0">
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<th>FSP</th>
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>TempRamInit</td>
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<td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
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<td>FSP binary found: POST code 0x90
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(<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
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is displayed<br>
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TempRamInit successful: POST code
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
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is displayed<br>
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</td>
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</tr>
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</table>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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