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mb/hp: Add EliteBook 820 G2

Browse Source 
Most of the components of this laptop are tested to work,
which is listed in the documentation.

Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Iru Cai
2021-04-24 21:22:10 +08:00
committed by Felix Singer
parent 9f59d2a906
commit 7e28c846c3
17 changed files with 571 additions and 0 deletions
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31
src/mainboard/hp/elitebook_820_g2/Kconfig Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
if BOARD_HP_ELITEBOOK_820_G2
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_12288
select EC_HP_KBC1126
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_GMA_HAVE_VBT
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_TPM1
select MAINBOARD_USES_IFD_GBE_REGION
select MEMORY_MAPPED_TPM
select SOC_INTEL_BROADWELL
select SYSTEM_TYPE_LAPTOP
config MAINBOARD_DIR
default "hp/elitebook_820_g2"
config MAINBOARD_PART_NUMBER
default "EliteBook 820 G2"
config EC_HP_KBC1126_ECFW_IN_CBFS
default n
config EC_HP_KBC1126_GPE
default 0x6
endif

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src/mainboard/hp/elitebook_820_g2/Kconfig.name Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
config BOARD_HP_ELITEBOOK_820_G2
bool "EliteBook 820 G2"

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src/mainboard/hp/elitebook_820_g2/Makefile.inc Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
romstage-y += gpio.c
romstage-y += pei_data.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
ramstage-y += pei_data.c

3
src/mainboard/hp/elitebook_820_g2/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <ec/hp/kbc1126/acpi/ec.asl>

14
src/mainboard/hp/elitebook_820_g2/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
Method(_WAK,1)
{
\_SB.PCI0.LPCB.EC0.ACPI = 1
\_SB.PCI0.LPCB.EC0.SLPT = 0
Return(Package(){0,0})
}
Method(_PTS,1)
{
\_SB.PCI0.LPCB.EC0.SLPT = Arg0
}

3
src/mainboard/hp/elitebook_820_g2/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/pc80/pc/ps2_controller.asl>

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src/mainboard/hp/elitebook_820_g2/board_info.txt Normal file
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Category: laptop
Board URL: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
ROM protocol: SPI
ROM package: SOIC-8
ROM socketed: n
Flashrom support: y
Release year: 2015

BIN
src/mainboard/hp/elitebook_820_g2/data.vbt Normal file
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src/mainboard/hp/elitebook_820_g2/devicetree.cb Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
chip soc/intel/broadwell
chip cpu/intel/haswell
device cpu_cluster 0 on ops broadwell_cpu_bus_ops end
end
device domain 0 on
ops broadwell_pci_domain_ops
subsystemid 0x103c 0x225a inherit
device pci 00.0 on end # Broadwell Host bridge
device pci 02.0 on # Internal graphics VGA controller
register "gfx" = "GMA_STATIC_DISPLAYS(0)"
register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4"
register "panel_cfg" = "{
.up_delay_ms = 200,
.down_delay_ms = 50,
.cycle_delay_ms = 500,
.backlight_on_delay_ms = 1,
.backlight_off_delay_ms = 1,
.backlight_pwm_hz = 200,
}"
end
device pci 03.0 on end # Mini-HD audio
chip soc/intel/broadwell/pch # Wildcat Point PCH
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # xHCI Controller
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 on end # Intel Gigabit Ethernet
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2, Card Reader
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 on # PCIe Port #4, WLAN
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther"
"M.2/E 2230" "SlotDataBusWidth1X"
end
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 on # PCIe Port #6, PCIe SSD
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther"
"M.2/M 2242/2260" "SlotDataBusWidth2X"
end
device pci 1d.0 on end # USB2 EHCI #1
device pci 1f.0 on # LPC bridge
register "gen1_dec" = "0x007c0201"
register "gen2_dec" = "0x000c0101"
register "gen4_dec" = "0x000402e9"
register "gpe0_en_1" = "0x40"
register "gpe0_en_2" = "0x600"
register "gpe0_en_4" = "0x46"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
# This laptop uses MEC1324, but it has the same interface
# as the KBC1126 laptops
chip ec/hp/kbc1126
register "ec_data_port" = "0x62"
register "ec_cmd_port" = "0x66"
register "ec_ctrl_reg" = "0x81"
register "ec_fan_ctrl_value" = "0x6b"
device pnp ff.1 off end
end
end
device pci 1f.2 on # SATA Controller (AHCI)
register "sata_port1_gen3_dtle" = "0x2"
register "sata_port1_gen3_tx" = "0x80"
register "sata_port3_gen3_dtle" = "0x4"
register "sata_port3_gen3_tx" = "0x80"
# SATA (1), M.2 (3)
register "sata_port_map" = "0xa"
end
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
end
end
end

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src/mainboard/hp/elitebook_820_g2/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018 /* OEM revision */
)
{
#include <acpi/dsdt_top.asl>
#include <southbridge/intel/common/acpi/platform.asl>
#include "acpi/platform.asl"
#include <soc/intel/common/acpi/acpi_wake_source.asl>
#include <soc/intel/broadwell/pch/acpi/globalnvs.asl>
#include <soc/intel/broadwell/acpi/device_nvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Device (\_SB.PCI0)
{
#include <northbridge/intel/haswell/acpi/hostbridge.asl>
#include <soc/intel/broadwell/pch/acpi/pch.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}
}

18
src/mainboard/hp/elitebook_820_g2/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-or-later
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(DP1, -- All DisplayPorts
HDMI1,
DP2, -- VGA
eDP,
others => Disabled);
end GMA.Mainboard;

110
src/mainboard/hp/elitebook_820_g2/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/lynxpoint/lp_gpio.h>
const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = {
[0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[2] = LP_GPIO_OUT_LOW,
[3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[7] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[8] = LP_GPIO_OUT_HIGH,
[9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[12] = LP_GPIO_NATIVE,
[13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[18] = LP_GPIO_OUT_HIGH,
[19] = LP_GPIO_NATIVE,
[20] = LP_GPIO_NATIVE,
[21] = LP_GPIO_NATIVE,
[22] = LP_GPIO_NATIVE,
[23] = LP_GPIO_NATIVE,
[24] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.reset = GPIO_RESET_RSMRST },
[25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[28] = LP_GPIO_OUT_HIGH,
[29] = LP_GPIO_OUT_LOW,
[30] = LP_GPIO_NATIVE,
[31] = LP_GPIO_NATIVE,
[32] = LP_GPIO_NATIVE,
[33] = LP_GPIO_NATIVE,
[34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[35] = LP_GPIO_NATIVE,
[36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[37] = LP_GPIO_NATIVE,
[38] = LP_GPIO_NATIVE,
[39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[40] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[41] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[42] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[43] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[45] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[48] = LP_GPIO_OUT_HIGH,
[49] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[50] = LP_GPIO_OUT_HIGH,
[51] = LP_GPIO_OUT_HIGH,
[52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[53] = LP_GPIO_OUT_HIGH,
[54] = LP_GPIO_OUT_HIGH,
[55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.owner = GPIO_OWNER_GPIO, .irqen = GPIO_IRQ_ENABLE,
.pirq = GPIO_PIRQ_APIC_ROUTE },
[56] = LP_GPIO_OUT_HIGH,
[57] = LP_GPIO_OUT_LOW,
[58] = LP_GPIO_OUT_HIGH,
[59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[60] = LP_GPIO_OUT_HIGH,
[61] = LP_GPIO_OUT_LOW,
[62] = LP_GPIO_NATIVE,
[63] = LP_GPIO_NATIVE,
[64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[65] = LP_GPIO_OUT_LOW,
[66] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT | GPIO_IRQ_LEVEL },
[70] = LP_GPIO_OUT_LOW,
[71] = LP_GPIO_NATIVE,
[72] = LP_GPIO_NATIVE,
[73] = LP_GPIO_NATIVE,
[74] = LP_GPIO_NATIVE,
[75] = LP_GPIO_NATIVE,
[76] = LP_GPIO_NATIVE,
[77] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[78] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL,
.route = GPIO_ROUTE_SMI },
[79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[80] = LP_GPIO_OUT_LOW,
[81] = LP_GPIO_NATIVE,
[82] = LP_GPIO_OUT_HIGH,
[83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[85] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[89] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[92] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[93] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
[94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_IRQ_LEVEL },
LP_GPIO_END
};

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src/mainboard/hp/elitebook_820_g2/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x10ec0280, /* Codec Vendor / Device ID: Realtek */
0x103c225a, /* Subsystem ID */
57, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(0, 0x103c198f),
AZALIA_RESET(1),
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
AZALIA_PIN_CFG(0, 0x15, 0x0421101f),
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1a, 0x04a11020),
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
AZALIA_PIN_CFG(0, 0x1d, 0x40748605),
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
0x02050007, 0x0204c200, 0x02050063, 0x02044800,
0x02050066, 0x02040809, 0x02050015, 0x02048842,
0x0205000f, 0x0204cccc, 0x02050010, 0x0204ccdd,
0x02050065, 0x02042000, 0x0205001c, 0x0204c900,
0x02050018, 0x02043788, 0x02050008, 0x02048210,
0x02050068, 0x02043022, 0x02050006, 0x02040800,
0x02050061, 0x02040403, 0x02050061, 0x02040403,
0x0205005f, 0x02040800, 0x02050060, 0x02040800,
0x0205002c, 0x02044002, 0x0205002e, 0x02041ec4,
0x0205002f, 0x02040000, 0x02050033, 0x0204c5e8,
0x02050034, 0x02041a98, 0x02050035, 0x0204f5ad,
0x02050036, 0x0204cbd2, 0x02050037, 0x02041605,
0x02050038, 0x0204f5ad, 0x02050039, 0x0204ea5f,
0x0205003a, 0x02040b42, 0x0205003b, 0x0204fb54,
0x0205003c, 0x0204fcd9, 0x0205003d, 0x02040000,
0x02050030, 0x02041f5c, 0x02050031, 0x02040111,
0x02050032, 0x02041f5f, 0x0205003e, 0x02041ea9,
0x0205002f, 0x02040000, 0x02050042, 0x0204c66e,
0x02050043, 0x02041a29, 0x02050035, 0x0204f5ad,
0x02050044, 0x0204ccdd, 0x02050045, 0x02041549,
0x02050038, 0x0204f5ad, 0x02050046, 0x0204ee79,
0x02050047, 0x020409f4, 0x0205003b, 0x0204fb54,
0x02050048, 0x0204fa4c, 0x0205003d, 0x02040000,
0x0205003f, 0x02041f4d, 0x02050040, 0x02040129,
0x02050041, 0x02041f51, 0x02050049, 0x02041f61,
0x0205002f, 0x02040000, 0x0205004d, 0x0204c2f4,
0x0205004e, 0x02041d2e, 0x02050035, 0x0204f5ad,
0x0205004f, 0x0204c5e8, 0x02050050, 0x02041a98,
0x02050038, 0x0204f5ad, 0x02050051, 0x0204d30e,
0x02050052, 0x020413e6, 0x0205003b, 0x0204fb54,
0x02050053, 0x02040b73, 0x0205003d, 0x02040000,
0x0205004a, 0x02041faf, 0x0205004b, 0x0204008a,
0x0205004c, 0x02041fb0, 0x02050054, 0x02041fb0,
0x0205002f, 0x02040000, 0x02050058, 0x0204c17a,
0x02050059, 0x02041e8f, 0x02050035, 0x0204f5ad,
0x0205005a, 0x0204c2f4, 0x0205005b, 0x02041d2e,
0x02050038, 0x0204f5ad, 0x0205005c, 0x0204c899,
0x0205005d, 0x0204195b, 0x0205003b, 0x0204fb54,
0x0205005e, 0x02041444, 0x0205003d, 0x02040000,
0x02050055, 0x02041fd8, 0x02050056, 0x02040045,
0x02050057, 0x02041fd8, 0x0205002c, 0x0204ffc2,
0x02050026, 0x02042828, 0x02050029, 0x02040250,
0x02050004, 0x0204c09e, 0x0205000e, 0x02045001,
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/hp/elitebook_820_g2/pei_data.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
void mb_get_spd_map(struct spd_info *spdi)
{
spdi->addresses[0] = 0x50;
spdi->addresses[2] = 0x52;
}
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
pei_data->ec_present = 1;
/* P1 */
pei_data_usb2_port(pei_data, 0, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P2: left side port, USB debug */
pei_data_usb2_port(pei_data, 1, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P3: digitizer and right side ports (Microchip hub) */
pei_data_usb2_port(pei_data, 2, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P4: WLAN */
pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P5: fingerprint reader */
pei_data_usb2_port(pei_data, 4, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P6: WWAN */
pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P7: webcam */
pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P8 */
pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL);
/* P1 */
pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
/* P2: left side, USB debug */
pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
/* P3: right side (Microchip hub) */
pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
/* P4 */
pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
}