diff --git a/src/mainboard/system76/gaze17/devicetree.cb b/src/mainboard/system76/gaze17/devicetree.cb
index 6c41321d91..b5d9f16f64 100644
--- a/src/mainboard/system76/gaze17/devicetree.cb
+++ b/src/mainboard/system76/gaze17/devicetree.cb
@@ -142,6 +142,7 @@ chip soc/intel/alderlake
 		device ref heci1 on end
 		device ref sata on
 			register "sata_ports_enable[1]" = "1" # SSD2 (SATA1A)
+			register "sata_ports_dev_slp[1]" = "1" # GPP_H13 (DEVSLP1B)
 		end
 		device ref pcie_rp5 on
 			# PCIe root port #5 x1, Clock 2 (WLAN)
diff --git a/src/mainboard/system76/gaze17/ramstage.c b/src/mainboard/system76/gaze17/ramstage.c
index fd98df91ab..2297490cad 100644
--- a/src/mainboard/system76/gaze17/ramstage.c
+++ b/src/mainboard/system76/gaze17/ramstage.c
@@ -11,5 +11,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5
 	params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4
 
+	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 (DEVSLP1B)
+
 	variant_configure_gpios();
 }