cpu/intel/model_206ax: Remove the notion of sockets

With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.

UNTESTED: This also updates autoport.

Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/model_206ax/Kconfig

@@ -13,6 +13,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
+	select MMX
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE

src/cpu/intel/model_206ax/Makefile.inc

@@ -3,6 +3,14 @@ subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 subdirs-y += ../common
 
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo
+
 ramstage-y += acpi.c
 
 ramstage-y += common.c