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util/inteltool: Add support for Alder Lake-N

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Reference: Intel Processor and Intel Core i3 N-Series Datasheet,
Volume 1 of 2 (#759603)

Change-Id: Ib3225088fa08fb7e5a60c87d0f1f6b3001f5b562
Signed-off-by: Brandon Weeks <me@brandonweeks.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This commit is contained in:
Brandon Weeks
2023-12-26 15:55:03 -08:00
committed by Felix Held
parent 30bd24fd26
commit 7ee7b137a7
11 changed files with 734 additions and 2 deletions
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23
util/inteltool/spi.c
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@@ -26,6 +26,22 @@ static const io_register_t pch_bios_cntl_registers[] = {
{ 0x6, 2, "reserved" },
};
static const io_register_t adl_pch_bios_cntl_registers[] = {
{ 0x0, 1, "WPD - Write Protect Disable" },
{ 0x1, 1, "LE - Lock Enable" },
{ 0x2, 1, "ESPI - eSPI Enable Pin Strap" },
{ 0x3, 1, "Reserved" },
{ 0x4, 1, "TS - Top Swap" },
{ 0x5, 1, "EISS - Enable InSMM.STS" },
{ 0x6, 1, "BBS - Boot BIOS Strap" },
{ 0x7, 1, "BILD - BIOS Interface Lock-Down" },
{ 0x8, 1, "BWPDS - BIOS Write Protect Disable Status" },
{ 0x9, 1, "Reserved" },
{ 0x10, 1, "BWRS - BIOS Write Status" },
{ 0x11, 1, "BWRE - BIOS Write Reporting (Async-SMI)" },
{ 0x12, 19, "Reserved" },
};
#define ICH9_SPIBAR 0x3800
#define ICH78_SPIBAR 0x3020
@@ -79,6 +95,7 @@ static const io_register_t ich7_spi_bar_registers[] = {
{ 0x68, 4, "PBR2 Protected BIOS Range 2" },
};
static int print_bioscntl(struct pci_dev *sb)
{
int i, size = 0;
@@ -210,6 +227,11 @@ static int print_bioscntl(struct pci_dev *sb)
bios_cntl_register = pch_bios_cntl_registers;
size = ARRAY_SIZE(pch_bios_cntl_registers);
break;
case PCI_DEVICE_ID_INTEL_ADL_N:
bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = adl_pch_bios_cntl_registers;
size = ARRAY_SIZE(adl_pch_bios_cntl_registers);
break;
default:
printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
return 1;
@@ -362,6 +384,7 @@ static int print_spibar(struct pci_dev *sb) {
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
case PCI_DEVICE_ID_INTEL_ICH5:
case PCI_DEVICE_ID_INTEL_ADL_N:
printf("This southbridge does not have RCBA.\n");
return 1;
default: