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vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSP

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Sync the MemInfoHob.h with current FSP code.

BUG=b:190339677
TEST=dmidecode -t 17 can show the memory information.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I80d1252b1f12b164d4f6d3a01221507cdfbe4d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This commit is contained in:
Eric Lai
2021-07-29 12:08:45 +08:00
committed by Tim Wawrzynczak
parent 4a198b578a
commit 7ef6357924
1 changed files with 17 additions and 14 deletions
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31
src/vendorcode/intel/fsp/fsp2_0/alderlake/MemInfoHob.h
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@@ -132,27 +132,21 @@ typedef enum {
// //
// Matches MrcDdrType enum in MRC // Matches MrcDdrType enum in MRC
// //
#ifndef MRC_DDR_TYPE_DDR4 #ifndef MRC_DDR_TYPE_DDR5
#define MRC_DDR_TYPE_DDR4 0 #define MRC_DDR_TYPE_DDR5 1
#endif #endif
#ifndef MRC_DDR_TYPE_DDR3 #ifndef MRC_DDR_TYPE_LPDDR5
#define MRC_DDR_TYPE_DDR3 1 #define MRC_DDR_TYPE_LPDDR5 2
#endif
#ifndef MRC_DDR_TYPE_LPDDR3
#define MRC_DDR_TYPE_LPDDR3 2
#endif #endif
#ifndef MRC_DDR_TYPE_LPDDR4 #ifndef MRC_DDR_TYPE_LPDDR4
#define MRC_DDR_TYPE_LPDDR4 3 #define MRC_DDR_TYPE_LPDDR4 3
#endif #endif
#ifndef MRC_DDR_TYPE_WIO2
#define MRC_DDR_TYPE_WIO2 4
#endif
#ifndef MRC_DDR_TYPE_UNKNOWN #ifndef MRC_DDR_TYPE_UNKNOWN
#define MRC_DDR_TYPE_UNKNOWN 5 #define MRC_DDR_TYPE_UNKNOWN 4
#endif #endif
#define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_PROFILE_NUM 7 // number of memory profiles supported
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported #define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
#define MAX_TRACE_REGION 5 #define MAX_TRACE_REGION 5
#define MAX_TRACE_CACHE_TYPE 2 #define MAX_TRACE_CACHE_TYPE 2
@@ -262,9 +256,18 @@ typedef struct {
SiMrcVersion Version; SiMrcVersion Version;
BOOLEAN EccSupport; BOOLEAN EccSupport;
UINT8 MemoryProfile; UINT8 MemoryProfile;
UINT8 IsDMBRunning; ///< Memory Trained with Dynamic Memory Boost (DMB)
UINT32 TotalPhysicalMemorySize; UINT32 TotalPhysicalMemorySize;
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. ///
/// Set of bit flags showing XMP and User Profile capability status for the DIMMs detected in system. For each bit, 1 is supported, 0 is unsupported.
/// Bit 0: XMP Profile 1 capability status
/// Bit 1: XMP Profile 2 capability status
/// Bit 2: XMP Profile 3 capability status
/// Bit 3: User Profile 4 capability status
/// Bit 4: User Profile 5 capability status
///
UINT8 XmpProfileEnable;
UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255 UINT8 Ratio; ///< DDR Frequency Ratio, Max Value 255
UINT8 RefClk; UINT8 RefClk;