drivers/elog: Add elog_boot_notify()

Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kyösti Mälkki
2019-09-11 17:12:26 +03:00
committed by Patrick Georgi
parent 2cce24dd4b
commit 7f50afb0c7
10 changed files with 16 additions and 25 deletions

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@@ -48,8 +48,7 @@ static void raminit_common(struct romstage_params *params)
s3wake = params->power_state->prev_sleep_state == ACPI_S3; s3wake = params->power_state->prev_sleep_state == ACPI_S3;
if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) elog_boot_notify(s3wake);
boot_count_increment();
/* Perform remaining SOC initialization */ /* Perform remaining SOC initialization */
soc_pre_ram_init(params); soc_pre_ram_init(params);

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@@ -392,8 +392,7 @@ void fsp_memory_init(bool s3wake)
struct memranges memmap; struct memranges memmap;
struct range_entry freeranges[2]; struct range_entry freeranges[2];
if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) elog_boot_notify(s3wake);
boot_count_increment();
if (cbfs_boot_locate(&file_desc, name, NULL)) { if (cbfs_boot_locate(&file_desc, name, NULL)) {
printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name);

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@@ -274,6 +274,12 @@ static inline u32 boot_count_read(void)
#endif #endif
u32 boot_count_increment(void); u32 boot_count_increment(void);
static inline void elog_boot_notify(int s3_resume)
{
if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume)
boot_count_increment();
}
/* /*
* Callback from GSMI handler to allow platform to log any wake source * Callback from GSMI handler to allow platform to log any wake source
* information. * information.

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@@ -139,8 +139,7 @@ void nehalem_early_initialization(int chipset_type)
s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
(((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3);
if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) elog_boot_notify(s3_resume);
boot_count_increment();
/* Device Enable */ /* Device Enable */
pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN,

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@@ -74,8 +74,7 @@ void mainboard_romstage_entry(void)
s3resume = southbridge_detect_s3_resume(); s3resume = southbridge_detect_s3_resume();
if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) elog_boot_notify(s3resume);
boot_count_increment();
post_code(0x38); post_code(0x38);

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@@ -49,12 +49,10 @@ asmlinkage void car_stage_entry(void)
console_init(); console_init();
mainboard_romstage_entry_s3(s3_resume); mainboard_romstage_entry_s3(s3_resume);
elog_boot_notify(s3_resume);
if (!s3_resume) { if (!s3_resume) {
post_code(0x40); post_code(0x40);
if (CONFIG(ELOG_BOOT_COUNT))
boot_count_increment();
} else { } else {
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);

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@@ -97,6 +97,7 @@ asmlinkage void car_stage_entry(void)
load_smu_fw1(); load_smu_fw1();
mainboard_romstage_entry_s3(s3_resume); mainboard_romstage_entry_s3(s3_resume);
elog_boot_notify(s3_resume);
bsp_agesa_call(); bsp_agesa_call();
@@ -132,8 +133,6 @@ asmlinkage void car_stage_entry(void)
msr_t sys_cfg = rdmsr(SYSCFG_MSR); msr_t sys_cfg = rdmsr(SYSCFG_MSR);
sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB;
wrmsr(SYSCFG_MSR, sys_cfg); wrmsr(SYSCFG_MSR, sys_cfg);
if (CONFIG(ELOG_BOOT_COUNT))
boot_count_increment();
} else { } else {
printk(BIOS_INFO, "S3 detected\n"); printk(BIOS_INFO, "S3 detected\n");
post_code(0x60); post_code(0x60);

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@@ -185,10 +185,7 @@ void mainboard_romstage_entry(void)
printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
#if CONFIG(ELOG_BOOT_COUNT) elog_boot_notify(prev_sleep_state == ACPI_S3);
if (prev_sleep_state != ACPI_S3)
boot_count_increment();
#endif
/* Initialize RAM */ /* Initialize RAM */
raminit(&mp, prev_sleep_state); raminit(&mp, prev_sleep_state);

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@@ -62,6 +62,8 @@ void mainboard_romstage_entry(void)
/* Get power state */ /* Get power state */
rp.power_state = fill_power_state(); rp.power_state = fill_power_state();
elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3);
/* Print useful platform information */ /* Print useful platform information */
report_platform_info(); report_platform_info();
@@ -80,10 +82,6 @@ void mainboard_romstage_entry(void)
rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; rp.pei_data.boot_mode = rp.power_state->prev_sleep_state;
if (CONFIG(ELOG_BOOT_COUNT)
&& rp.power_state->prev_sleep_state != ACPI_S3)
boot_count_increment();
/* Print ME state before MRC */ /* Print ME state before MRC */
intel_me_status(); intel_me_status();

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@@ -124,10 +124,7 @@ int early_pch_init(const void *gpio_map,
wake_from_s3 = southbridge_detect_s3_resume(); wake_from_s3 = southbridge_detect_s3_resume();
#if CONFIG(ELOG_BOOT_COUNT) elog_boot_notify(wake_from_s3);
if (!wake_from_s3)
boot_count_increment();
#endif
/* Report if we are waking from s3. */ /* Report if we are waking from s3. */
return wake_from_s3; return wake_from_s3;