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sb/amd/sb600: Get rid of device_t

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Use of device_t has been abandoned in ramstage.

Change-Id: I587b32e33af72a37be8299b9db2ce26ba825a689
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Elyes HAOUAS
2018-05-19 14:09:33 +02:00
committed by Kyösti Mälkki
parent 7a4d41aa2d
commit 7f55810cf0
7 changed files with 28 additions and 27 deletions
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4
src/southbridge/amd/sb600/hda.c
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@@ -150,7 +150,7 @@ static u32 cim_verb_data[] = {
static u32 find_verb(u32 viddid, u32 ** verb) static u32 find_verb(u32 viddid, u32 ** verb)
{ {
device_t azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2)); struct device *azalia_dev = dev_find_slot(0, PCI_DEVFN(0x14, 2));
struct southbridge_amd_sb600_config *cfg = struct southbridge_amd_sb600_config *cfg =
(struct southbridge_amd_sb600_config *)azalia_dev->chip_info; (struct southbridge_amd_sb600_config *)azalia_dev->chip_info;
if (!cfg) if (!cfg)
@@ -265,7 +265,7 @@ static void hda_init(struct device *dev)
void *base; void *base;
struct resource *res; struct resource *res;
u32 codec_mask; u32 codec_mask;
device_t sm_dev; struct device *sm_dev;
/* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */ /* Enable azalia - PM_io 0x59[4], disable ac97 - PM_io 0x59[1..0] */
pm_iowrite(0x59, 0xB); pm_iowrite(0x59, 0xB);

14
src/southbridge/amd/sb600/lpc.c
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@@ -31,11 +31,11 @@
#include <cpu/amd/powernow.h> #include <cpu/amd/powernow.h>
#include "sb600.h" #include "sb600.h"
static void lpc_init(device_t dev) static void lpc_init(struct device *dev)
{ {
u8 byte; u8 byte;
u32 dword; u32 dword;
device_t sm_dev; struct device *sm_dev;
/* Enable the LPC Controller */ /* Enable the LPC Controller */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
@@ -67,7 +67,7 @@ static void lpc_init(device_t dev)
setup_i8254(); /* Initialize i8254 timers */ setup_i8254(); /* Initialize i8254 timers */
} }
static void sb600_lpc_read_resources(device_t dev) static void sb600_lpc_read_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;
@@ -103,7 +103,7 @@ static void sb600_lpc_read_resources(device_t dev)
* @param dev the device whose children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
static void sb600_lpc_enable_childrens_resources(device_t dev) static void sb600_lpc_enable_childrens_resources(struct device *dev)
{ {
struct bus *link; struct bus *link;
u32 reg, reg_x; u32 reg, reg_x;
@@ -115,7 +115,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev)
reg_x = pci_read_config32(dev, 0x48); reg_x = pci_read_config32(dev, 0x48);
for (link = dev->link_list; link; link = link->next) { for (link = dev->link_list; link; link = link->next) {
device_t child; struct device *child;
for (child = link->children; child; for (child = link->children; child;
child = child->sibling) { child = child->sibling) {
if (child->enabled if (child->enabled
@@ -214,7 +214,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev)
pci_write_config8(dev, 0x74, wiosize); pci_write_config8(dev, 0x74, wiosize);
} }
static void sb600_lpc_enable_resources(device_t dev) static void sb600_lpc_enable_resources(struct device *dev)
{ {
pci_dev_enable_resources(dev); pci_dev_enable_resources(dev);
sb600_lpc_enable_childrens_resources(dev); sb600_lpc_enable_childrens_resources(dev);
@@ -224,7 +224,7 @@ static void sb600_lpc_enable_resources(device_t dev)
extern u16 pm_base; extern u16 pm_base;
static void southbridge_acpi_fill_ssdt_generator(device_t device) { static void southbridge_acpi_fill_ssdt_generator(struct device *device) {
amd_generate_powernow(pm_base + 8, 6, 1); amd_generate_powernow(pm_base + 8, 6, 1);
} }

2
src/southbridge/amd/sb600/sata.c
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@@ -66,7 +66,7 @@ static void sata_init(struct device *dev)
struct southbridge_ati_sb600_config *conf; struct southbridge_ati_sb600_config *conf;
conf = dev->chip_info; conf = dev->chip_info;
device_t sm_dev; struct device *sm_dev;
/* SATA SMBus Disable */ /* SATA SMBus Disable */
/* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */ /* sm_dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));

16
src/southbridge/amd/sb600/sb600.c
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@@ -23,9 +23,9 @@
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include "sb600.h" #include "sb600.h"
static device_t find_sm_dev(device_t dev, u32 devfn) static struct device *find_sm_dev(struct device *dev, u32 devfn)
{ {
device_t sm_dev; struct device *sm_dev;
sm_dev = dev_find_slot(dev->bus->secondary, devfn); sm_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!sm_dev) if (!sm_dev)
@@ -45,7 +45,7 @@ static device_t find_sm_dev(device_t dev, u32 devfn)
return sm_dev; return sm_dev;
} }
void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask, u32 val)
{ {
u32 reg_old, reg; u32 reg_old, reg;
reg = reg_old = pci_read_config32(sm_dev, reg_pos); reg = reg_old = pci_read_config32(sm_dev, reg_pos);
@@ -88,8 +88,8 @@ u8 pm2_ioread(u8 reg)
return pmio_read_index(PM2_INDEX, reg); return pmio_read_index(PM2_INDEX, reg);
} }
static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos, static void set_pmio_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
u32 mask, u32 val) u32 val)
{ {
u8 reg_old, reg; u8 reg_old, reg;
reg = reg_old = pm_ioread(reg_pos); reg = reg_old = pm_ioread(reg_pos);
@@ -100,10 +100,10 @@ static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,
} }
} }
void sb600_enable(device_t dev) void sb600_enable(struct device *dev)
{ {
device_t sm_dev = 0; struct device *sm_dev = NULL;
device_t bus_dev = 0; struct device *bus_dev = NULL;
int index = -1; int index = -1;
u32 deviceid; u32 deviceid;
u32 vendorid; u32 vendorid;

5
src/southbridge/amd/sb600/sb600.h
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@@ -36,8 +36,9 @@ extern void pm2_iowrite(u8 reg, u8 value);
extern u8 pm2_ioread(u8 reg); extern u8 pm2_ioread(u8 reg);
#ifndef __SIMPLE_DEVICE__ #ifndef __SIMPLE_DEVICE__
extern void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); extern void set_sm_enable_bits(struct device *sm_dev, u32 reg_pos, u32 mask,
void sb600_enable(device_t dev); u32 val);
void sb600_enable(struct device *dev);
#endif #endif
void sb600_lpc_port80(void); void sb600_lpc_port80(void);

12
src/southbridge/amd/sb600/sm.c
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@@ -40,7 +40,7 @@
* SB600 enables all USB controllers by default in SMBUS Control. * SB600 enables all USB controllers by default in SMBUS Control.
* SB600 enables SATA by default in SMBUS Control. * SB600 enables SATA by default in SMBUS Control.
*/ */
static void sm_init(device_t dev) static void sm_init(struct device *dev)
{ {
u8 byte; u8 byte;
u8 byte_old; u8 byte_old;
@@ -216,7 +216,7 @@ static void sm_init(device_t dev)
abcfg_reg(0x50, 1 << 3, 1 << 3); abcfg_reg(0x50, 1 << 3, 1 << 3);
} }
static int lsmbus_recv_byte(device_t dev) static int lsmbus_recv_byte(struct device *dev)
{ {
u32 device; u32 device;
struct resource *res; struct resource *res;
@@ -230,7 +230,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device); return do_smbus_recv_byte(res->base, device);
} }
static int lsmbus_send_byte(device_t dev, u8 val) static int lsmbus_send_byte(struct device *dev, u8 val)
{ {
u32 device; u32 device;
struct resource *res; struct resource *res;
@@ -244,7 +244,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
return do_smbus_send_byte(res->base, device, val); return do_smbus_send_byte(res->base, device, val);
} }
static int lsmbus_read_byte(device_t dev, u8 address) static int lsmbus_read_byte(struct device *dev, u8 address)
{ {
u32 device; u32 device;
struct resource *res; struct resource *res;
@@ -258,7 +258,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address); return do_smbus_read_byte(res->base, device, address);
} }
static int lsmbus_write_byte(device_t dev, u8 address, u8 val) static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
{ {
u32 device; u32 device;
struct resource *res; struct resource *res;
@@ -278,7 +278,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte, .write_byte = lsmbus_write_byte,
}; };
static void sb600_sm_read_resources(device_t dev) static void sb600_sm_read_resources(struct device *dev)
{ {
struct resource *res; struct resource *res;
u8 byte; u8 byte;

2
src/southbridge/amd/sb600/usb.c
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@@ -33,7 +33,7 @@ static void usb_init(struct device *dev)
u32 dword; u32 dword;
/* Enable OHCI0-4 and EHCI Controllers */ /* Enable OHCI0-4 and EHCI Controllers */
device_t sm_dev; struct device *sm_dev;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
byte = pci_read_config8(sm_dev, 0x68); byte = pci_read_config8(sm_dev, 0x68);
byte |= 0x3F; byte |= 0x3F;