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src/southbridge: Remove unnecessary whitespace before "\n" and "\t"

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Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16281
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Omar Pakker
This commit is contained in:
Elyes HAOUAS
2016-08-21 12:06:54 +02:00
committed by Martin Roth
parent d6e96864c9
commit 7f9df96825
11 changed files with 47 additions and 47 deletions
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2
src/southbridge/amd/amd8132/bridge.c
View File

@@ -151,7 +151,7 @@ static void amd8132_scan_bus(struct bus *bus,
info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
/* Print the PCI-X bus speed */
printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x\n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
/* Examine the bus and find out how loaded it is */

66
src/southbridge/amd/rs780/gfx.c
View File

@@ -197,7 +197,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
{
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x \n", Value);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
//Found Creative SB
@@ -228,7 +228,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
}
}
}
printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x\n", MMIOStart, MMIOLimit);
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
@@ -570,44 +570,44 @@ static void internal_gfx_pci_dev_init(struct device *dev)
poweron_ddi_lanes(nb_dev);
printk(BIOS_DEBUG,"vgainfo:\n"
" ulBootUpEngineClock:%lu \n"
" ulBootUpUMAClock:%lu \n"
" ulBootUpSidePortClock:%lu \n"
" ulMinSidePortClock:%lu \n"
" ulSystemConfig:%lu \n"
" ulBootUpReqDisplayVector:%lu \n"
" ulOtherDisplayMisc:%lu \n"
" ulDDISlot1Config:%lu \n"
" ulDDISlot2Config:%lu \n"
" ulBootUpEngineClock:%lu\n"
" ulBootUpUMAClock:%lu\n"
" ulBootUpSidePortClock:%lu\n"
" ulMinSidePortClock:%lu\n"
" ulSystemConfig:%lu\n"
" ulBootUpReqDisplayVector:%lu\n"
" ulOtherDisplayMisc:%lu\n"
" ulDDISlot1Config:%lu\n"
" ulDDISlot2Config:%lu\n"
" ucMemoryType:%u \n"
" ucUMAChannelNumber:%u \n"
" ucDockingPinBit:%u \n"
" ucDockingPinPolarity:%u \n"
" ucMemoryType:%u\n"
" ucUMAChannelNumber:%u\n"
" ucDockingPinBit:%u\n"
" ucDockingPinPolarity:%u\n"
" ulDockingPinCFGInfo:%lu \n"
" ulCPUCapInfo: %lu \n"
" ulDockingPinCFGInfo:%lu\n"
" ulCPUCapInfo: %lu\n"
" usNumberOfCyclesInPeriod:%hu \n"
" usMaxNBVoltage:%hu \n"
" usMinNBVoltage:%hu \n"
" usBootUpNBVoltage:%hu \n"
" usNumberOfCyclesInPeriod:%hu\n"
" usMaxNBVoltage:%hu\n"
" usMinNBVoltage:%hu\n"
" usBootUpNBVoltage:%hu\n"
" ulHTLinkFreq:%lu \n"
" ulHTLinkFreq:%lu\n"
" usMinHTLinkWidth:%hu \n"
" usMaxHTLinkWidth:%hu \n"
" usUMASyncStartDelay:%hu \n"
" usUMADataReturnTime:%hu \n"
" usLinkStatusZeroTime:%hu \n"
" usMinHTLinkWidth:%hu\n"
" usMaxHTLinkWidth:%hu\n"
" usUMASyncStartDelay:%hu\n"
" usUMADataReturnTime:%hu\n"
" usLinkStatusZeroTime:%hu\n"
" ulHighVoltageHTLinkFreq:%lu \n"
" ulLowVoltageHTLinkFreq:%lu \n"
" ulHighVoltageHTLinkFreq:%lu\n"
" ulLowVoltageHTLinkFreq:%lu\n"
" usMaxUpStreamHTLinkWidth:%hu \n"
" usMaxDownStreamHTLinkWidth:%hu \n"
" usMinUpStreamHTLinkWidth:%hu \n"
" usMinDownStreamHTLinkWidth:%hu \n",
" usMaxUpStreamHTLinkWidth:%hu\n"
" usMaxDownStreamHTLinkWidth:%hu\n"
" usMinUpStreamHTLinkWidth:%hu\n"
" usMinDownStreamHTLinkWidth:%hu\n",
(unsigned long)vgainfo.ulBootUpEngineClock,
(unsigned long)vgainfo.ulBootUpUMAClock,