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src/southbridge: Remove unnecessary whitespace before "\n" and "\t"

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Change-Id: I42cc5b8736e73728c5deec6349e8d2a814e19e83
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16281
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Omar Pakker
This commit is contained in:
Elyes HAOUAS
2016-08-21 12:06:54 +02:00
committed by Martin Roth
parent d6e96864c9
commit 7f9df96825
11 changed files with 47 additions and 47 deletions
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2
src/southbridge/amd/amd8132/bridge.c
View File

@ -151,7 +151,7 @@ static void amd8132_scan_bus(struct bus *bus,
info.sstatus = pci_read_config16(bus->dev, pos + PCI_X_SEC_STATUS);
/* Print the PCI-X bus speed */
printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x \n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
printk(BIOS_DEBUG, "PCI: %02x: %s sstatus=%04x rev=%02x\n", bus->secondary, pcix_speed(info.sstatus), info.sstatus, info.rev);
/* Examine the bus and find out how loaded it is */

66
src/southbridge/amd/rs780/gfx.c
View File

@ -197,7 +197,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
{
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x \n", Value);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
//Found Creative SB
@ -228,7 +228,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
}
}
}
printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit);
printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x\n", MMIOStart, MMIOLimit);
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
@ -570,44 +570,44 @@ static void internal_gfx_pci_dev_init(struct device *dev)
poweron_ddi_lanes(nb_dev);
printk(BIOS_DEBUG,"vgainfo:\n"
" ulBootUpEngineClock:%lu \n"
" ulBootUpUMAClock:%lu \n"
" ulBootUpSidePortClock:%lu \n"
" ulMinSidePortClock:%lu \n"
" ulSystemConfig:%lu \n"
" ulBootUpReqDisplayVector:%lu \n"
" ulOtherDisplayMisc:%lu \n"
" ulDDISlot1Config:%lu \n"
" ulDDISlot2Config:%lu \n"
" ulBootUpEngineClock:%lu\n"
" ulBootUpUMAClock:%lu\n"
" ulBootUpSidePortClock:%lu\n"
" ulMinSidePortClock:%lu\n"
" ulSystemConfig:%lu\n"
" ulBootUpReqDisplayVector:%lu\n"
" ulOtherDisplayMisc:%lu\n"
" ulDDISlot1Config:%lu\n"
" ulDDISlot2Config:%lu\n"
" ucMemoryType:%u \n"
" ucUMAChannelNumber:%u \n"
" ucDockingPinBit:%u \n"
" ucDockingPinPolarity:%u \n"
" ucMemoryType:%u\n"
" ucUMAChannelNumber:%u\n"
" ucDockingPinBit:%u\n"
" ucDockingPinPolarity:%u\n"
" ulDockingPinCFGInfo:%lu \n"
" ulCPUCapInfo: %lu \n"
" ulDockingPinCFGInfo:%lu\n"
" ulCPUCapInfo: %lu\n"
" usNumberOfCyclesInPeriod:%hu \n"
" usMaxNBVoltage:%hu \n"
" usMinNBVoltage:%hu \n"
" usBootUpNBVoltage:%hu \n"
" usNumberOfCyclesInPeriod:%hu\n"
" usMaxNBVoltage:%hu\n"
" usMinNBVoltage:%hu\n"
" usBootUpNBVoltage:%hu\n"
" ulHTLinkFreq:%lu \n"
" ulHTLinkFreq:%lu\n"
" usMinHTLinkWidth:%hu \n"
" usMaxHTLinkWidth:%hu \n"
" usUMASyncStartDelay:%hu \n"
" usUMADataReturnTime:%hu \n"
" usLinkStatusZeroTime:%hu \n"
" usMinHTLinkWidth:%hu\n"
" usMaxHTLinkWidth:%hu\n"
" usUMASyncStartDelay:%hu\n"
" usUMADataReturnTime:%hu\n"
" usLinkStatusZeroTime:%hu\n"
" ulHighVoltageHTLinkFreq:%lu \n"
" ulLowVoltageHTLinkFreq:%lu \n"
" ulHighVoltageHTLinkFreq:%lu\n"
" ulLowVoltageHTLinkFreq:%lu\n"
" usMaxUpStreamHTLinkWidth:%hu \n"
" usMaxDownStreamHTLinkWidth:%hu \n"
" usMinUpStreamHTLinkWidth:%hu \n"
" usMinDownStreamHTLinkWidth:%hu \n",
" usMaxUpStreamHTLinkWidth:%hu\n"
" usMaxDownStreamHTLinkWidth:%hu\n"
" usMinUpStreamHTLinkWidth:%hu\n"
" usMinDownStreamHTLinkWidth:%hu\n",
(unsigned long)vgainfo.ulBootUpEngineClock,
(unsigned long)vgainfo.ulBootUpUMAClock,

2
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -210,7 +210,7 @@ static void soc_pirq_init(device_t dev)
/* Set up the PIRQ PIC routing based on static config. */
printk(BIOS_SPEW, "Start writing IRQ assignments\n"
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);

2
src/southbridge/nvidia/ck804/ide.c
View File

@ -36,7 +36,7 @@ static void ide_init(struct device *dev)
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
printk(BIOS_DEBUG, "IDE1 \t");
printk(BIOS_DEBUG, "IDE1\t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */

2
src/southbridge/nvidia/ck804/lpc.c
View File

@ -111,7 +111,7 @@ static void lpc_init(device_t dev)
lpc_common_init(dev);
pm_base = pci_read_config32(dev, 0x60) & 0xff00;
printk(BIOS_INFO, "%s: pm_base = %x \n", __func__, pm_base);
printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base);
/* Power after power fail */
on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;

2
src/southbridge/nvidia/ck804/sata.c
View File

@ -102,7 +102,7 @@ static void sata_init(struct device *dev)
if (conf->sata1_enable) {
/* Enable secondary SATA interface. */
dword |= (1 << 0);
printk(BIOS_DEBUG, "SATA S \t");
printk(BIOS_DEBUG, "SATA S\t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface. */

2
src/southbridge/nvidia/mcp55/ide.c
View File

@ -38,7 +38,7 @@ static void ide_init(struct device *dev)
if (conf->ide1_enable) {
/* Enable secondary IDE interface. */
word |= (1 << 0);
printk(BIOS_DEBUG, "IDE1 \t");
printk(BIOS_DEBUG, "IDE1\t");
}
if (conf->ide0_enable) {
/* Enable primary IDE interface. */

6
src/southbridge/nvidia/mcp55/sata.c
View File

@ -39,16 +39,16 @@ static void sata_init(struct device *dev)
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
printk(BIOS_DEBUG, "SATA S \t");
printk(BIOS_DEBUG, "SATA S\t");
}
if (conf->sata0_enable) {
/* Enable primary SATA interface */
dword |= (1<<1);
printk(BIOS_DEBUG, "SATA P \n");
printk(BIOS_DEBUG, "SATA P\n");
}
} else {
dword |= (1<<1) | (1<<0);
printk(BIOS_DEBUG, "SATA P and S \n");
printk(BIOS_DEBUG, "SATA P and S\n");
}

2
src/southbridge/sis/sis966/aza.c
View File

@ -100,7 +100,7 @@ static int codec_detect(u8 *base)
do{
dword = read32(base + 0x08)&0x1;
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!! \n"); break;}
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
} while (dword !=1);
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId

2
src/southbridge/sis/sis966/ide.c
View File

@ -120,7 +120,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
if (conf->ide1_enable) {
/* Enable secondary ide interface */
word |= (1<<0);
printk(BIOS_DEBUG, "IDE1 \t");
printk(BIOS_DEBUG, "IDE1\t");
}
if (conf->ide0_enable) {
/* Enable primary ide interface */

6
src/southbridge/sis/sis966/nic.c
View File

@ -221,7 +221,7 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
if(!bFoundPhy)
{
printk(BIOS_DEBUG, "PHY not found !!!! \n");
printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
*PhyAddr=PhyAddress;
@ -283,7 +283,7 @@ static void nic_init(struct device *dev)
// if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL));
printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL));
for(i=0;i<3;i++) {
//status = smbus_read_byte(dev_eeprom, i);
ulValue=ReadEEprom( dev, base, i+3L);
@ -294,7 +294,7 @@ static void nic_init(struct device *dev)
}
}else{
// read MAC address from firmware
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
MacAddr[1]=read16((u16 *)0xffffffc2);
MacAddr[2]=read16((u16 *)0xffffffc4);