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baytrail: Add reserved MMIO regions to ACPI

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Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.

Add a region for the "abort page" documented in the EDS.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4934
Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
2013-11-04 17:00:22 -08:00
committed by Aaron Durbin
parent a90a59f5a3
commit 7fbe20bd2c
4 changed files with 82 additions and 9 deletions
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15
src/soc/intel/baytrail/southcluster.c
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@@ -41,13 +41,14 @@ add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size)
static void sc_add_mmio_resources(device_t dev)
{
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, 1024);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, 16 * 1024);
add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, 1024);
add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, 1024);
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, 1024 * 1024);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, 2048);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, 1024);
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE);
add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE);
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
}
/* Default IO range claimed by the LPC device. The upper bound is exclusive. */