sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arch/x86/asembly_entry: reorder conditional stage entry macros

Browse Source 
The path that just clears CAR_GLOBAL variables and jumps
to the stage entry point needs another condition for
separate verstage just after bootblock. However, the
current conditional is a negative conditional so
swap the logic around to make it easier to extend.

Change-Id: Iab6682498054715a6eaa0476390da6355238b9bc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14547
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Aaron Durbin
2016-04-29 12:10:28 -05:00
parent a6e9051bc6
commit 800b0173c9
1 changed files with 23 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

44
src/arch/x86/assembly_entry.S
View File

@@ -14,28 +14,8 @@
* GNU General Public License for more details.
*/
#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/* This file assembles the start of the romstage program by the order of the
* includes. Thus, it's extremely important that one pays very careful
* attention to the order of the includes. */
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
#if IS_ENABLED(CONFIG_SSE)
#include <cpu/x86/sse_enable.inc>
#endif
/*
* The assembly.inc is generated based on the requirements of the mainboard.
* For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
* processed by ROMCC and added. In non-ROMCC boards the chipsets'
* cache-as-ram setup files would be here.
*/
#include <generated/assembly.inc>
#else
/*
* This path is for stages that post bootblock when employing
* CONFIG_C_ENVIRONMENT_BOOTBLOCK. There's no need to re-load the gdt, etc
@@ -65,4 +45,26 @@ _start:
car_stage_entry:
1:
jmp 1b
#else
/* This file assembles the start of the romstage program by the order of the
* includes. Thus, it's extremely important that one pays very careful
* attention to the order of the includes. */
#include <arch/x86/prologue.inc>
#include <cpu/x86/32bit/entry32.inc>
#include <cpu/x86/fpu_enable.inc>
#if IS_ENABLED(CONFIG_SSE)
#include <cpu/x86/sse_enable.inc>
#endif
/*
* The assembly.inc is generated based on the requirements of the mainboard.
* For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be
* processed by ROMCC and added. In non-ROMCC boards the chipsets'
* cache-as-ram setup files would be here.
*/
#include <generated/assembly.inc>
#endif