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src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines

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The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.

BUG=N/A
TEST=Intel BayTrail CRB

Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Huang Jin <huang.jin@intel.com>
This commit is contained in:
Frans Hendriks
2018-10-29 14:17:16 +01:00
committed by Felix Held
parent 2f1ef98bdc
commit 802f43d67f
1 changed files with 3 additions and 2 deletions
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5
src/soc/intel/baytrail/southcluster.c
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@@ -3,6 +3,7 @@
* *
* Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2008-2009 coresystems GmbH
* Copyright (C) 2013 Google Inc. * Copyright (C) 2013 Google Inc.
* Copyright (C) 2018 Eltan B.V.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -106,10 +107,10 @@ static void sc_add_io_resources(struct device *dev)
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* GPIO */ /* GPIO */
sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE);
/* ACPI */ /* ACPI */
sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE);
} }
static void sc_read_resources(struct device *dev) static void sc_read_resources(struct device *dev)