sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/poppy/variants/atlas: Update DPTF parameters

Browse Source 
Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
  in thermal chamber test

BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test

Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
This commit is contained in:
Puthikorn Voravootivat
2019-02-26 15:56:14 -08:00
committed by Patrick Georgi
parent 8997f67cf0
commit 805bd10ede
1 changed files with 17 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl
View File

@ -24,17 +24,17 @@
#define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_NAME "Charger" #define DPTF_TSR1_SENSOR_NAME "Charger"
#define DPTF_TSR1_PASSIVE 48 #define DPTF_TSR1_PASSIVE 53
#define DPTF_TSR1_CRITICAL 90 #define DPTF_TSR1_CRITICAL 90
#define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM" #define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_PASSIVE 54
#define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4 #define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "eMMC" #define DPTF_TSR3_SENSOR_NAME "eMMC"
#define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_PASSIVE 54
#define DPTF_TSR3_CRITICAL 75 #define DPTF_TSR3_CRITICAL 75
#undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_FAN_CONTROL
@ -52,20 +52,26 @@ Name (DTRT, Package () {
/* CPU Throttle Effect on CPU */ /* CPU Throttle Effect on CPU */
Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR0 */ /* CPU Throttle Effect on Ambient */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR1 */ /* CPU Throttle Effect on DRAM */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR2 */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
/* CPU Throttle Effect on TSR3 */ /* CPU Throttle Effect on eMMC */
Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
/* Charger Throttle Effect on TSR0 */ /* Charger Throttle Effect on Ambient */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 200, 50, 0, 0, 0, 0 },
/* Charger Throttle Effect on Charger */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 50, 0, 0, 0, 0 },
/* Charger Throttle Effect on DRAM */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 50, 0, 0, 0, 0 },
/* Charger Throttle Effect on eMMC */
Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 200, 50, 0, 0, 0, 0 },
}) })
Name (MPPC, Package () Name (MPPC, Package ()