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mb/google: Get rid of whitespace before tab

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Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2018-05-28 13:30:59 +02:00
committed by Patrick Georgi
parent 5e4b8ad5a7
commit 808fc8ef87
12 changed files with 30 additions and 30 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl
View File

@@ -31,9 +31,9 @@ Method(_PRT)
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// EHCI 0:1d.0
// EHCI 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// XHCI 0:14.0
// XHCI 0:14.0
Package() { 0x0014ffff, 0, 0, 18 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 22 },
@@ -61,9 +61,9 @@ Method(_PRT)
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI 0:1d.0
// EHCI 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// XHCI 0:14.0
// XHCI 0:14.0
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },

6
src/mainboard/google/beltino/variants/mccloud/led.c
View File

@@ -20,11 +20,11 @@
void set_power_led(int state)
{
it8772f_gpio_led(IT8772F_GPIO_DEV,
1, /* set */
0x01, /* select */
1, /* set */
0x01, /* select */
state == LED_BLINK ? 0x01 : 0x00, /* polarity */
state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */
0x01, /* output */
0x01, /* output */
state == LED_BLINK ? 0x00 : 0x01, /* I/O function */
SIO_GPIO_BLINK_GPIO10,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);

10
src/mainboard/google/beltino/variants/tricky/led.c
View File

@@ -20,12 +20,12 @@
void set_power_led(int state)
{
it8772f_gpio_led(IT8772F_GPIO_DEV,
2, /* set */
0xF7, /* select */
2, /* set */
0xF7, /* select */
state == LED_OFF ? 0x00 : 0x04, /* polarity */
state == LED_BLINK ? 0x04 : 0x00, /* pullup/pulldown */
0x04, /* output */
state == LED_BLINK ? 0x00 : 0x04, /* I/O function */
state == LED_BLINK ? 0x04 : 0x00, /* pullup/pulldown */
0x04, /* output */
state == LED_BLINK ? 0x00 : 0x04, /* I/O function */
SIO_GPIO_BLINK_GPIO22,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);
}

2
src/mainboard/google/butterfly/Kconfig
View File

@@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1.
select SERIRQ_CONTINUOUS_MODE # Workaround for EC/KBC IRQ1.
config VBOOT
select VBOOT_VBNV_CMOS

6
src/mainboard/google/cyan/variants/cyan/include/variant/onboard.h
View File

@@ -64,9 +64,9 @@
#define AUDIO_CODEC_DDN "Maxim 98090 Codec "
#define AUDIO_CODEC_I2C_ADDR 0x10
#define TI_SWITCH_HID "104C227E"
#define TI_SWITCH_CID "104C227E"
#define TI_SWITCH_DDN "TI SWITCH "
#define TI_SWITCH_HID "104C227E"
#define TI_SWITCH_CID "104C227E"
#define TI_SWITCH_DDN "TI SWITCH "
#define TI_SWITCH_I2C_ADDR 0x3B
#define DPTF_CPU_PASSIVE 88

6
src/mainboard/google/jecht/led.c
View File

@@ -28,11 +28,11 @@ void set_power_led(int state)
}
it8772f_gpio_led(IT8772F_GPIO_DEV,
1, /* set */
0x01, /* select */
1, /* set */
0x01, /* select */
polarity, /* polarity */
state == LED_BLINK ? 0x01 : 0x00, /* pullup/pulldown */
0x01, /* output */
0x01, /* output */
state == LED_BLINK ? 0x00 : 0x01, /* I/O function */
SIO_GPIO_BLINK_GPIO10,
IT8772F_GPIO_BLINK_FREQUENCY_1_HZ);

6
src/mainboard/google/link/i915.c
View File

@@ -305,7 +305,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x21000000;
/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
@@ -319,7 +319,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x22000000;
/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_LANE0_SET << 8|0x3;
@@ -333,7 +333,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info,
auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_TRAINING_PATTERN_SET << 8|0x0;
auxout[1] = 0x00000000;
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);

2
src/mainboard/google/link/i915io.h
View File

@@ -48,7 +48,7 @@
* 2 -> print IO ops
* 4 -> print the number of times we spin on a register in a poll
* 8 -> restore whatever the previous verbosity level was
* (only one deep stack)
* (only one deep stack)
*
* Again, this is not really meant for human consumption. There is not a poll
* operator as such because, sometimes, there is a read/write/read where the

2
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@@ -184,7 +184,7 @@ chip soc/intel/apollolake
register "has_power_resource" = "1"
device i2c 10 on end
end
end # - I2C 7
end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2

2
src/mainboard/google/octopus/variants/bip/devicetree.cb
View File

@@ -180,7 +180,7 @@ chip soc/intel/apollolake
register "has_power_resource" = "1"
device i2c 10 on end
end
end # - I2C 7
end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 off end # - UART 1
device pci 18.2 on end # - UART 2

2
src/mainboard/google/rambi/variants/squawks/devicetree.cb
View File

@@ -1,6 +1,6 @@
chip soc/intel/baytrail
# SATA port enable mask (2 ports)
# SATA port enable mask (2 ports)
register "sata_port_map" = "0x1"
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"

8
src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
View File

@@ -31,9 +31,9 @@ Method(_PRT)
Package() { 0x001cffff, 1, 0, 17 },
Package() { 0x001cffff, 2, 0, 18 },
Package() { 0x001cffff, 3, 0, 19 },
// EHCI 0:1d.0
// EHCI 0:1d.0
Package() { 0x001dffff, 0, 0, 19 },
// XHCI 0:14.0
// XHCI 0:14.0
Package() { 0x0014ffff, 0, 0, 18 },
// LPC devices 0:1f.0
Package() { 0x001fffff, 0, 0, 22 },
@@ -61,9 +61,9 @@ Method(_PRT)
Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
// EHCI 0:1d.0
// EHCI 0:1d.0
Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
// XHCI 0:14.0
// XHCI 0:14.0
Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
// LPC device 0:1f.0
Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },