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GX2: Clean up some white space and comments.

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Also, add a copyright header to pll_reset.c.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Nils Jacobs
2010-11-01 14:36:54 +00:00
committed by Uwe Hermann
parent fc9fcf7414
commit 809e29ec8f
2 changed files with 146 additions and 150 deletions
Download Patch File Download Diff File Expand all files Collapse all files

45
src/include/cpu/amd/gx2def.h
View File

@@ -1,5 +1,6 @@
#ifndef CPU_AMD_GX2DEF_H
#define CPU_AMD_GX2DEF_H
#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/
#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/
#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/
@@ -13,6 +14,7 @@
#define CPU_REV_2_1 0x021
#define CPU_REV_2_2 0x022
#define CPU_REV_3_0 0x030
/* GeodeLink Control Processor Registers, GLIU1, Port 3 */
#define GLCP_CLK_DIS_DELAY 0x4c000008
#define GLCP_PMCLKDISABLE 0x4c000009
@@ -59,7 +61,6 @@
/* port4 - PCI */
/* port5 - FG */
#define GL0_GLIU0 0
#define GL0_MC 1
#define GL0_GLIU1 2
@@ -88,14 +89,11 @@
#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */
#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
/* South Bridge */
#define SB_PORT 2 /* port of the SouthBridge */
/**/
/* GeodeLink Interface Unit 0 (GLIU0) port0 */
/**/
#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
@@ -103,10 +101,7 @@
#define GLIU0_CAP (MSR_GLIU0 + 0x86)
#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
/**/
/* Memory Controller GLIU0 port 1 */
/**/
#define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
#define MC_GLD_MSR_PM (MSR_MC + 0x2004)
@@ -129,7 +124,6 @@
#define CF07_LOWER_REF_TEST_SET (1 << 3)
#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
#define MC_CF8F_DATA (MSR_MC + 0x19)
#define CF8F_UPPER_XOR_BS_SHIFT 19
@@ -164,19 +158,13 @@
#define MC_CF_RDSYNC (MSR_MC + 0x1F)
/**/
/* GLIU1 GLIU0 port2 */
/**/
#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
/**/
/* CPU ; does not need routing instructions since we are executing there. */
/**/
#define CPU_GLD_MSR_CAP 0x2000
#define CPU_GLD_MSR_CONFIG 0x2001
#define CPU_GLD_MSR_PM 0x2004
@@ -215,13 +203,13 @@
#define CPU_IM_BIST_TAG 0x1730
#define CPU_IM_BIST_DATA 0x1731
/* various CPU MSRs */
#define CPU_DM_CONFIG0 0x1800
#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8)
#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
/* configuration MSRs */
#define CPU_RCONF_DEFAULT 0x1808
#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
@@ -294,10 +282,7 @@
#define TSC_SUSP_SET (1<<5)
#define SUSP_EN_SET (1<<12)
/**/
/* VG GLIU0 port4 */
/**/
#define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
#define VG_GLD_MSR_PM (MSR_VG + 0x2004)
@@ -306,22 +291,13 @@
#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
#define GP_GLD_MSR_PM (MSR_GP + 0x2004)
/**/
/* DF GLIU0 port6 */
/**/
#define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
#define DF_LOWER_LCD_SHIFT 6
#define DF_GLD_MSR_PM (MSR_DF + 0x2004)
/**/
/* GeodeLink Control Processor GLIU1 port3 */
/**/
#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
@@ -355,10 +331,7 @@
#define GLCP_DOTPLL (MSR_GLCP + 0x15 /* R/W */)
#define DOTPPL_LOWER_PD_SET (1<<14)
/**/
/* GLIU1 port 4 */
/**/
#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
@@ -423,27 +396,23 @@
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
/**/
/* FooGlue GLIU1 port 5 */
/**/
#define FG_GLD_MSR_CAP (MSR_FG + 0x2000)
#define FG_GLD_MSR_PM (MSR_FG + 0x2004)
/* VIP GLIU1 port 5 */
/* */
#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
#define VIP_BIST (MSR_VIP + 0x2005)
#define VIP_GIO_MSR_SEL (MSR_VIP + 0x2010)
/* */
/* AES GLIU1 port 6 */
/* */
#define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
#define AES_CONTROL (MSR_AES + 0x2006)
/* more fun stuff */
#define BM 1 /* Base Mask - map power of 2 size aligned region */
#define BMO 2 /* BM with an offset */
@@ -503,9 +472,7 @@
#define CHIPSET_DEV_NUM 15
#define IDSEL_BASE 11 // bit 11 = device 1
/* */
/* SB LBAR IO + MEMORY MAP */
/* */
#define SMBUS_BASE ( 0x6000)
#define GPIO_BASE ( 0x6100)
#define MFGPT_BASE ( 0x6200)

117
src/northbridge/amd/gx2/pll_reset.c
View File

@@ -1,3 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/tsc.h>
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
@@ -69,7 +89,7 @@ bad_ctc:
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
* CPU Clock = sppl_raw_clk / VDIV
* CPU Clock = spll_raw_clk / VDIV
*/
/* table for Feedback divisor to FbDiv register value */
@@ -99,6 +119,15 @@ static const unsigned char pci33_ddr_crt [] = {
26, 2, 3 // 433/289
};
/* FbDIV VDIV MDIV CPU/GeodeLink */
/* 12 2 3 200/133 */
/* 16 2 3 266/177 */
/* 18 2 3 300/200 */
/* 20 2 3 333/222 */
/* 22 2 3 366/244 */
/* 24 2 3 400/266 */
/* 26 2 3 433/289 */
#if 0
static unsigned int get_memory_speed(void)
{
@@ -118,12 +147,12 @@ static unsigned int get_memory_speed(void)
///////////////////////////////////////////////////////////////////////////////
// Goodrich Version of pll_reset
// PLLCHECK_COMPLETED is the "we've already done this" flag
/* PLLCHECK_COMPLETED is the "we've already done this" flag */
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
#endif // RSTPPL_LOWER_BYPASS_SET
#endif /* RSTPPL_LOWER_BYPASS_SET */
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
@@ -133,84 +162,84 @@ static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
unsigned MDIV_VDIV_FBDIV;
unsigned SyncBits; // store the sync bits in up ebx
unsigned SyncBits; /* store the sync bits in up ebx */
// clear the Bypass bit
/* clear the Bypass bit */
// If the straps say we are in bypass and the syspll is not AND there are no software
// bits set then FS2 or something set up the PLL and we should not change it.
/* If the straps say we are in bypass and the syspll is not AND there are no software */
/* bits set then FS2 or something set up the PLL and we should not change it. */
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// If the "we've already been here" flag is set, don't reconfigure the pll
/* If the "we've already been here" flag is set, don't reconfigure the pll */
if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
{ // we haven't configured the PLL; do it now
{ /* we haven't configured the PLL; do it now */
// Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
// correct Strap Table.
/* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
/* correct Strap Table. */
post_code(POST_PLL_INIT);
// configure for DDR
/* configure for DDR */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// Use Manual settings
// UseManual:
/* Use Manual settings */
/* UseManual: */
post_code(POST_PLL_MANUAL);
// DIV settings manually entered.
// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
// use gs and fs since we don't need them.
/* DIV settings manually entered. */
/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
/* use gs and fs since we don't need them. */
// ProgramClocks:
// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
// move everything into ebx
// VDIV
/* ProgramClocks: */
/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
/* move everything into ebx */
/* VDIV */
MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);
// MDIV
/* MDIV */
MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);
// FbDIV
/* FbDIV */
MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
// write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values
/* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// Set Reset, LockWait, and SW flag
// DoReset:
/* Set Reset, LockWait, and SW flag */
/* DoReset: */
// CheckSemiSync proc
// Check for Semi-Sync in GeodeLink and CPU.
// We need to do this here since the strap settings don't account for these bits.
/* CheckSemiSync proc */
/* Check for Semi-Sync in GeodeLink and CPU. */
/* We need to do this here since the strap settings don't account for these bits. */
SyncBits = 0; // store the sync bits in up ebx
// Check for Bypass mode.
/* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
{
// If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.
/* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */
SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
}
else
{
// CheckPCIsync:
// If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater
// look up the real divider... if we get a 0 we have serious problems
/* CheckPCIsync: */
/* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
/* look up the real divider... if we get a 0 we have serious problems */
if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
// CheckCPUSync:
// If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync.
// CPU is always greater or equal.
/* CheckCPUSync: */
/* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */
/* CPU is always greater or equal. */
if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))
{
@@ -219,29 +248,29 @@ static void pll_reset(void)
}
// SetSync:
/* SetSync: */
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
msrGlcpSysRstpll.lo |= SyncBits;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// CheckSemiSync endp
/* CheckSemiSync endp */
// now we do the reset
// Set hold count to 99 (063h)
/* now we do the reset */
/* Set hold count to 99 (063h) */
msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= PLLCHECK_COMPLETED; // Say we are done
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// Don't want to use LOCKWAIT
/* Don't want to use LOCKWAIT */
msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// You should never get here..... The chip has reset.
/* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL);
while (1);
} // we haven't configured the PLL; do it now
} /* we haven't configured the PLL; do it now */
}
// End of Goodrich version of pll_reset