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AGESA f14 vendorcode: Remove unused sources

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Change-Id: Ie4a735b156ded934fac0c9248fbb9042bf9be781
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Kyösti Mälkki
2017-08-29 13:08:43 +03:00
parent be76344331
commit 80b8f69ac9
75 changed files with 0 additions and 13552 deletions
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222
src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafe.c
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@ -1,222 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Cable safe module
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e $Revision: $ @e $Date: $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "GnbRegistersON.h"
#include "cpuFamilyTranslation.h"
#include "NbSmuLib.h"
#include "GnbCableSafeDefs.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_MODULES_GNBCABLESAFE_GNBCABLESAFE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
UINT8 HdpIndexTranslationTable [] = {
3, 2, 1, 0, 7, 6
};
UINT8 AuxIndexTranslationTable [] = {
5, 4, 11, 10, 9, 8
};
UINT8 AuxDataTranslationTable [] = {
0x10, 0x20, 0x40, 0x01, 0x02, 0x04
};
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
GnbCableSafeGetConnectorInfoArrayCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
);
BOOLEAN
GnbCableSafeIsSupported (
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------*/
/**
* Cable Safe module entry
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_STATUS
*/
AGESA_STATUS
GnbCableSafeEntry (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
PCIe_PLATFORM_CONFIG *Pcie;
PCIe_ENGINE_CONFIG *DdiEngineList [MaxHdp];
UINT8 HdpIndex;
UINT8 CurrentIndex;
GNB_CABLE_SAFE_DATA CableSafeData;
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Enter\n");
Status = AGESA_SUCCESS;
if (GnbCableSafeIsSupported (StdHeader)) {
if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) {
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
DdiEngineList[HdpIndex] = NULL;
}
LibAmdMemFill (&CableSafeData, 0, sizeof (CableSafeData), StdHeader);
PcieConfigRunProcForAllEngines (
DESCRIPTOR_ALLOCATED | DESCRIPTOR_DDI_ENGINE,
GnbCableSafeGetConnectorInfoArrayCallback,
DdiEngineList,
Pcie
);
CurrentIndex = 0;
for (HdpIndex = 0; HdpIndex < MaxHdp; HdpIndex++) {
if (DdiEngineList [HdpIndex] != NULL) {
CableSafeData.Data[HdpIndexTranslationTable[CurrentIndex]] = HdpIndex + 1;
CableSafeData.Data[AuxIndexTranslationTable[CurrentIndex]] = AuxDataTranslationTable [(DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex];
IDS_HDT_CONSOLE (NB_MISC, " Index [%d] HDP 0x%02x AUX 0x%02x\n", CurrentIndex, HdpIndex, (DdiEngineList [HdpIndex])->Type.Ddi.DdiData.AuxIndex);
CurrentIndex++;
}
}
CableSafeData.Config.Enable = 0x1;
CableSafeData.Config.DebounceFilter = 0x2;
CableSafeData.Config.SoftPeriod = 0x4;
CableSafeData.Config.Unit = 0x1;
CableSafeData.Config.Period = 0xf424;
NbSmuRcuRegisterWrite (
SMUx0B_x85D0_ADDRESS,
(UINT32*) &CableSafeData,
sizeof (CableSafeData) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuServiceRequest (0x05, TRUE, StdHeader);
} else {
Status = AGESA_ERROR;
}
}
IDS_HDT_CONSOLE (GNB_TRACE, "GnbCableSafeEntry Exit [Status = 0x%04x]\n", Status);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Callback to init max port Gen capability
*
*
*
*
* @param[in] Engine Pointer to engine config descriptor
* @param[in, out] Buffer Not used
* @param[in] Pcie Pointer to global PCIe configuration
*
*/
VOID
STATIC
GnbCableSafeGetConnectorInfoArrayCallback (
IN PCIe_ENGINE_CONFIG *Engine,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_ENGINE_CONFIG **EngineList;
EngineList = (PCIe_ENGINE_CONFIG**) Buffer;
EngineList [Engine->Type.Ddi.DdiData.HdpIndex] = Engine;
}
/*----------------------------------------------------------------------------------------*/
/**
* Check if feature supported
*
* Module requre for LN B0 and above
*
*
* @param[in] StdHeader Standard configuration header
* @retval TRUE Cable safe needs to be enabled
*/
BOOLEAN
GnbCableSafeIsSupported (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN Result;
CPU_LOGICAL_ID LogicalId;
SMU_FIRMWARE_REV FirmwareRev;
Result = FALSE;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
FirmwareRev = NbSmuFirmwareRevision (StdHeader);
if (SMI_FIRMWARE_REVISION (FirmwareRev) >= 0x010904 && LogicalId.Revision > AMD_F12_LN_A1) {
Result = TRUE;
}
return Result;
}

66
src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbCableSafe/GnbCableSafeDefs.h
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@ -1,66 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Cable safe module
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e $Revision: $ @e $Date: $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _GNBCABLESAFEDEFS_H_
#define _GNBCABLESAFEDEFS_H_
#pragma pack (push, 1)
/// Cable safe data package
typedef struct {
struct {
UINT32 Enable :1; ///< Enable cable safe
UINT32 DebounceFilter :3; ///< Debounce filter
UINT32 SoftPeriod :4; ///< Soft period
UINT32 Unit :4; ///< Unit
UINT32 Reserved :4; ///< Reserved
UINT32 Period :16; ///< Period
} Config; ///< Configuration package
UINT8 Data [12]; ///< HDP/AUX info array
} GNB_CABLE_SAFE_DATA;
#pragma pack (pop)
#endif

217
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl
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@ -1,217 +0,0 @@
/**
* @file
*
* ALIB PSPP Pcie Smu Lib V1
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------*/
/**
* SMU indirect register read
*
* Arg0 - Smu register offset
*
*/
Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) {
Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
// Access 32 bit width
Increment (Arg0)
// Reverse ReqToggle
Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
// Assign Address and ReqType = 0
Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0)
procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0)
return (Local0)
}
/*----------------------------------------------------------------------------------------*/
/**
* SMU indirect register Write
*
* Arg0 - Smu register offset
* Arg1 - Value
* Arg2 - Width, 0 = 16, 1 = 32
*
*/
Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) {
Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0)
// Get low 16 bit value
Store (And (Arg1, 0xFFFF), Local1)
// Reverse ReqToggle
Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
// Assign Address
Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0)
// ReqType = 1
Or (Local0, 0x02000000, Local0)
// Assign Low 16 bit value
Or (Local0, Local1, Local0)
procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
if (LEqual (Arg2, 1)) {
// Get high 16 bit value
Store (ShiftRight (Arg1, 16), Local1)
// Reverse ReqToggle
Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0)
// Assign Address
Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0)
// Assign High 16 bit value
Or (Local0, Local1, Local0)
procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0)
}
}
/*----------------------------------------------------------------------------------------*/
/**
* SMU Service request
*
* Arg0 - Smu service id
* Arg1 - Flags - Poll Ack = 1, Poll down = 2
*
*/
Method (procNbSmuServiceRequest, 2, NotSerialized) {
Store ("NbSmuServiceRequest Enter", Debug)
Store ("Request id =", Debug)
Store (Arg0, Debug)
Or (ShiftLeft (Arg0, 3), 0x1, Local0)
procNbSmuIndirectRegisterWrite (0x3, Local0, 1)
if (LAnd (Arg1, 1)) {
while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) {
Store ("--Wait Ack--", Debug)
}
}
if (LAnd (Arg1, 2)) {
while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) {
Store ("--Wait Done--", Debug)
}
}
// Clear IRQ register
procNbSmuIndirectRegisterWrite (0x3, 0, 0)
Store ("NbSmuServiceRequest Exit", Debug)
}
/*----------------------------------------------------------------------------------------*/
/**
* Write RCU register
*
* Arg0 - Register Address
* Arg1 - Register Data
*
*/
Method (procSmuRcuWrite, 2, NotSerialized) {
procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
procNbSmuIndirectRegisterWrite (0x5, Arg1, 1)
}
/*----------------------------------------------------------------------------------------*/
/**
* Read RCU register
*
* Arg0 - Register Address
* Retval - RCU register value
*/
Method (procSmuRcuRead, 1, NotSerialized) {
procNbSmuIndirectRegisterWrite (0xB, Arg0, 0)
Store (procNbSmuIndirectRegisterRead (0x5), Local0)
return (Local0)
}
/*----------------------------------------------------------------------------------------*/
/**
* SMU SRBM Register Read
*
* Arg0 - FCR register address
*
*/
Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) {
//SMUx0B_x8600
Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
//SMUx0B_x8604
Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
//SMUx0B_x8608
Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
//Write SMU RCU
procSmuRcuWrite (0x8600, Local0)
procSmuRcuWrite (0x8604, Local1)
procSmuRcuWrite (0x8608, Local2)
// ServiceId
if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) {
procNbSmuServiceRequest (0xD, 0x3)
}
if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) {
procNbSmuServiceRequest (0xB, 0x3)
}
return (procSmuRcuRead(0x8650))
}
/*----------------------------------------------------------------------------------------*/
/**
* SMU SRBM Register Write
*
* Arg0 - FCR register address
* Arg1 - Value
*
*/
Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) {
//SMUx0B_x8600
Store (Or (And (Arg0, 0xFF), 0x01865000), Local0)
//SMUx0B_x8604
Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1)
//SMUx0B_x8608
Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2)
Or (Local2, ShiftLeft (1, 16), Local2)
//Write SMU RCU
procSmuRcuWrite (0x8600, Local0)
procSmuRcuWrite (0x8604, Local1)
procSmuRcuWrite (0x8608, Local2)
//Write Data
procSmuRcuWrite (0x8650, Arg1)
// ServiceId
procNbSmuServiceRequest (0xB, 0x3)
}

372
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.c
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@ -1,372 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* PCIe power gate
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "amdlib.h"
#include "Gnb.h"
#include "GnbPcie.h"
#include "PcieInit.h"
#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1)
#include GNB_MODULE_DEFINITIONS (GnbPcieConfig)
#include "PciePowerGate.h"
#include "GnbRegistersON.h"
#include "NbSmuLib.h"
#include "Filecode.h"
#define FILECODE PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define FORCE_PCIE_POWERGATING_DISABLE (1 << 2)
#define FORCE_PCIE_PHY_POWERGATING_DISABLE (1 << 1)
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
POWER_GATE_DATA PciePowerGatingData = {
113, 50, 50, 50, 50, 50
};
/// PCIe power gating
UINT32 PciePowerGatingTable_1[] = {
// SMUx0B_x8408_ADDRESS
0,
// SMUx0B_x840C_ADDRESS
0,
// SMUx0B_x8410_ADDRESS
(0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) |
(0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) |
(0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET)
};
/*----------------------------------------------------------------------------------------*/
/**
* PCIe Power Gating
*
*
*
* @param[in] StdHeader Standard Configuration Header
* @param[in] Flags Force Powergating disable or Phy disable flag.
* @param[in] PowerGateData Power Gate data
*/
VOID
STATIC
PcieSmuPowerGatingInit (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT8 Flags,
IN POWER_GATE_DATA *PowerGateData
)
{
NbSmuRcuRegisterWrite (
SMUx0B_x8408_ADDRESS,
&PciePowerGatingTable_1[0],
sizeof (PciePowerGatingTable_1) / sizeof (UINT32),
TRUE,
StdHeader
);
NbSmuRcuRegisterWrite (
SMUx0B_x84A0_ADDRESS,
(UINT32 *) PowerGateData,
sizeof (POWER_GATE_DATA) / sizeof (UINT32),
TRUE,
StdHeader
);
if (Flags != 0) {
UINT32 Value;
ASSERT ((Flags & (~(BIT1 | BIT2))) == 0);
NbSmuRcuRegisterRead (SMUx0B_x8410_ADDRESS, &Value, 1, StdHeader);
Value |= (Flags & (BIT1 | BIT2));
NbSmuRcuRegisterWrite (SMUx0B_x8410_ADDRESS, &Value, 1, TRUE, StdHeader);
}
NbSmuServiceRequest (0x01, TRUE, StdHeader);
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIe PowerGate PHY lanes
*
*
* @param[in] WrapperLaneBitMap Lane bitmap on wrapper
* @param[in] WrapperStartlaneId Start Line Id of the wrapper
* @param[in] Service Power gate service
* @param[in] Core Core power gate request
* @param[in] Tx Tx power gate request
* @param[in] Rx Rx power gate request
* @param[in] Pcie PCIe configuration data
*/
VOID
STATIC
PcieSmuPowerGateLanes (
IN UINT32 WrapperLaneBitMap,
IN UINT16 WrapperStartlaneId,
IN UINT8 Service,
IN UINT8 Core,
IN UINT8 Tx,
IN UINT8 Rx,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
PCIe_PHY_POWER_GATE LaneSegment;
UINT8 NumberOfLanes;
UINT8 Index;
LaneSegment.Tx = Tx;
LaneSegment.Rx = Rx;
LaneSegment.Core = Core;
NumberOfLanes = 0;
for (Index = 0; Index <= 32; Index++) {
if ((WrapperLaneBitMap & 1) != 0) {
NumberOfLanes++;
} else {
if (NumberOfLanes != 0) {
LaneSegment.LowerLaneId = Index - NumberOfLanes + WrapperStartlaneId;
LaneSegment.UpperLaneId = Index - 1 + WrapperStartlaneId;
IDS_HDT_CONSOLE (PCIE_MISC, " Powergate Phy Lanes %d - %d (Service = 0x%x, Core = 0x%x, Tx = 0x%x, Rx = 0x%x)\n",
LaneSegment.LowerLaneId, LaneSegment.UpperLaneId, Service, Core, Tx, Rx
);
NbSmuRcuRegisterWrite (
0x858C,
(UINT32*) &LaneSegment,
1,
TRUE,
GnbLibGetHeader (Pcie)
);
NbSmuServiceRequest (Service, TRUE, GnbLibGetHeader (Pcie));
NumberOfLanes = 0;
}
}
WrapperLaneBitMap >>= 1;
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Pll access required
*
* @param[in] PllId Pll ID
* @param[in] AccessRequired Access required
* @param[in] Pcie Pointer to global PCIe configuration
*/
VOID
STATIC
PciePowerGatePllControl (
IN UINT8 PllId,
IN BOOLEAN AccessRequired,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 Value;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n");
NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie));
Value = (Value & 0xFFFFFF00) | PllId;
NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie));
NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie));
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n");
}
/*----------------------------------------------------------------------------------------*/
/**
* Report used lanes to SMU.
*
*
* @param[in] Wrapper Wrapper configuration descriptor
* @param[in, out] Buffer Not used
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
PciePowerGateReportUsedLanesCallback (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LaneBitmap;
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie);
if (LaneBitmap != 0) {
PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie);
}
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIe PowerGate PHY lanes
*
*
* @param[in] Wrapper Wrapper configuration descriptor
* @param[out] Buffer Pointer to Boolean to report if DDI lanes present
* @param[in] Pcie Pointer to global PCIe configuration
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
PciePowerGatePhyLaneCallback (
IN PCIe_WRAPPER_CONFIG *Wrapper,
IN OUT VOID *Buffer,
IN PCIe_PLATFORM_CONFIG *Pcie
)
{
UINT32 LaneBitmap;
BOOLEAN *IsDdiPresent;
IsDdiPresent = (BOOLEAN*) Buffer;
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, Wrapper, Pcie);
if (LaneBitmap != 0) {
PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie);
}
// Powergate inactive hotplug lanes
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, LANE_TYPE_PCIE_ACTIVE, Wrapper, Pcie);
if (LaneBitmap != 0) {
PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie);
}
// Powergate DDI lanes
LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ACTIVE, 0, Wrapper, Pcie);
if (LaneBitmap != 0) {
*IsDdiPresent = TRUE;
PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie);
}
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* PCIe PowerGate PHY lanes
*
*
*
* @param[in] StdHeader Standard Configuration Header
* @retval AGESA_STATUS
*/
AGESA_STATUS
STATIC
PciePowerGatePhyLane (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
AGESA_STATUS AgesaStatus;
BOOLEAN IsDdiPresent;
PCIe_PLATFORM_CONFIG *Pcie;
AgesaStatus = AGESA_SUCCESS;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n");
Status = PcieLocateConfigurationData (StdHeader, &Pcie);
ASSERT (Status == AGESA_SUCCESS);
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (Status == AGESA_SUCCESS) {
PciePortsVisibilityControl (UnhidePorts, Pcie);
IsDdiPresent = FALSE;
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie );
AGESA_STATUS_UPDATE (Status, AgesaStatus);
PciePowerGatePllControl (0x1, TRUE, Pcie);
Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie );
AGESA_STATUS_UPDATE (Status, AgesaStatus);
if (!IsDdiPresent) {
PciePowerGatePllControl (0x1, FALSE, Pcie);
}
PciePortsVisibilityControl (HidePorts, Pcie);
}
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n");
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Power PCIe block
*
*
*
* @param[in] StdHeader Pointer to Standard configuration
* @retval AGESA_STATUS
*/
AGESA_STATUS
PciePowerGateFeature (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
PCIE_POWERGATE_CONFIG PciePowerGate;
AGESA_STATUS Status;
UINT8 Flags;
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n");
Status = AGESA_SUCCESS;
PciePowerGate.Services.PciePowerGate = 0x1;
PciePowerGate.Services.PciePhyLanePowerGate = 0x1;
LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader);
IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader);
Flags = 0;
if (PciePowerGate.Services.PciePowerGate == 0x0) {
IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n");
Flags |= FORCE_PCIE_POWERGATING_DISABLE;
}
if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) {
IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n");
Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE;
}
PcieSmuPowerGatingInit (StdHeader, Flags, &PciePowerGate.Pcie);
Status = PciePowerGatePhyLane (StdHeader);
IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status);
return Status;
}

69
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Feature/PciePowerGate.h
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@ -1,69 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Service procedure to calculate PCIe topology segment maximum exit latency
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _PCIEPOWERGATE_H_
#define _PCIEPOWERGATE_H_
/// PCIe power gate configuration
typedef struct {
struct {
UINT32 PciePowerGate :1; ///< Enable core power gating
UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating
} Services; ///< Power gating services
POWER_GATE_DATA Pcie; ///< PCIe Power gating Data
} PCIE_POWERGATE_CONFIG;
/// PCIe PHY power gate config
typedef struct {
UINT32 Rx :1; ///< RX state
UINT32 Tx :1; ///< TX state
UINT32 Core :1; ///< Core
UINT32 Reserved :13; ///< reserved
UINT32 LowerLaneId :8; ///< Lower lane ID
UINT32 UpperLaneId :8; ///< Upper lane ID
} PCIe_PHY_POWER_GATE;
#endif

163
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.c
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@ -1,163 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Family 10h Routines.
*
* Coherent feature Northbridge implementation specific to Family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbCoherentFam10.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBCOHERENTFAM10_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Return whether the current configuration exceeds the capability.
*
* @HtNbMethod{::F_IS_EXCEEDED_CAPABLE}.
*
* Get Node capability and update the minimum supported system capability.
*
* @param[in] Node the Node
* @param[in] State sysMpCap (updated) and NodesDiscovered
* @param[in] Nb this northbridge
*
* @retval TRUE system is not capable of current config.
* @retval FALSE system is capable of current config.
*/
BOOLEAN
Fam10IsExceededCapable (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
UINT8 MaxNodes;
PCI_ADDR Reg;
ASSERT (Node < MAX_NODES);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_CAPABILITY_3XE8);
LibAmdPciReadBits (Reg, 18, 16, &Temp, Nb->ConfigHandle);
if (Temp != 0) {
MaxNodes = (UINT8) (1 << (~Temp & 0x3)); // That is, 1, 2, 4, or 8
} else {
MaxNodes = 8;
}
if (State->SysMpCap > MaxNodes) {
State->SysMpCap = MaxNodes;
}
// Note since sysMpCap is one based and NodesDiscovered is zero based, equal returns true
//
return ((BOOLEAN) (State->SysMpCap <= State->NodesDiscovered));
}
/**
* Stop a link, so that it is isolated from a connected device.
*
* @HtNbMethod{::F_STOP_LINK}.
*
* Use is for fatal incompatible configurations, or for user interface
* request to power off a link (IgnoreLink, SkipRegang).
* Set ConnDly to make the power effective at the warm reset.
* Set XMT and RCV off.
*
* @param[in] Node the node to stop a link on.
* @param[in] Link the link to stop.
* @param[in] State access to special routine for writing link control register
* @param[in] Nb this northbridge.
*/
VOID
Fam10StopLink (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
// Set ConnDly
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_GLOBAL_EXT_CONTROL_0x16C);
Temp = 1;
LibAmdPciWriteBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
// Set TransOff and EndOfChain
Reg = Nb->MakeLinkBase (Node, Link, Nb);
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
Temp = 3;
State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
}

67
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbCoherentFam10.h
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@ -1,67 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Family 10h specific Routines.
*
* Coherent feature Northbridge implementation specific to Family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Return whether the current configuration exceeds the capability.
*
*/
BOOLEAN
Fam10IsExceededCapable (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);
/**
* Stop a link, so that it is isolated from a connected device.
*/
VOID
Fam10StopLink (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);

362
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbFam10.c
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@ -1,362 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Initializers for Family 10h northbridge support.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "OptionsHt.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "CommonReturns.h"
#include "htNbCoherent.h"
#include "htNbCoherentFam10.h"
#include "htNbNonCoherent.h"
#include "htNbNonCoherentFam10.h"
#include "htNbOptimization.h"
#include "htNbOptimizationFam10.h"
#include "htNbSystemFam10.h"
#include "htNbUtilities.h"
#include "htNbUtilitiesFam10.h"
#include "cpuFamRegisters.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBFAM10_FILECODE
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
/**
* Map Northbridge links to package links for Family 10h, Rev D, multi-module.
*
* Unfortunately, there is no way to do this except to type the BKDG text into this data structure.
* Note that there is one entry per package external sublink and each connected internal link.
*/
CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam10RevDPackageLinkMap[] =
{
{0, 0, 0}, ///< Module zero, link 0: package link 0
{4, 0, 4}, ///< Module zero, link 4: package link 4
{0, 1, 1}, ///< Module one, link 0: package link 1
{4, 1, 5}, ///< Module one, link 4: package link 5
{3, 0, 2}, ///< Module zero, link 3: package link 2
{7, 0, 6}, ///< Module zero, link 7: package link 6
{2, 0, 3}, ///< Module zero, link 2: package link 3
{1, 1, 7}, ///< Module one, link 1: package link 7
{1, 0, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
{5, 0, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
{6, 0, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
{2, 1, HT_LIST_MATCH_INTERNAL_LINK_0}, ///< Internal Link
{6, 1, HT_LIST_MATCH_INTERNAL_LINK_1}, ///< Internal Link
{5, 1, HT_LIST_MATCH_INTERNAL_LINK_2}, ///< Internal Link
{HT_LIST_TERMINAL, HT_LIST_TERMINAL, HT_LIST_TERMINAL}, ///< End
};
/**
* A default Ignore Link list for rev D to power off the 3rd internal sublink.
*/
STATIC CONST IGNORE_LINK ROMDATA Fam10RevDIgnoreLinkList[] = {
HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK_2, POWERED_OFF,
HT_LIST_TERMINAL
};
/**
* Initial construction data for Family 10h North Bridge, default, full features.
*/
CONST NORTHBRIDGE ROMDATA HtFam10NbDefault =
{
8,
WriteRoutingTable,
WriteNodeID,
ReadDefaultLink,
EnableRoutingTables,
DisableRoutingTables,
VerifyLinkIsCoherent,
ReadToken,
WriteToken,
WriteFullRoutingTable,
IsIllegalTypeMix,
Fam10IsExceededCapable,
Fam10StopLink,
(PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
HandleSpecialNodeCase,
ReadSouthbridgeLink,
VerifyLinkIsNonCoherent,
Fam10SetConfigAddrMap,
Fam10NorthBridgeFreqMask,
GatherLinkFeatures,
SetLinkRegang,
SetLinkFrequency,
SetLinkUnitIdClumping,
Fam10WriteTrafficDistribution,
Fam10WriteLinkPairDistribution,
Fam10BufferOptimizations,
Fam10GetNumCoresOnNode,
SetTotalNodesAndCores,
GetNodeCount,
LimitNodes,
ReadTrueLinkFailStatus,
Fam10GetNextLink,
GetPackageLink,
MakeLinkBase,
Fam10GetModuleInfo,
Fam10PostMailbox,
Fam10RetrieveMailbox,
Fam10GetSocket,
(PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
(PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
0x00000001,
0x00000200,
18,
TRUE,
TRUE,
((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
NULL,
0,
NULL,
MakeKey,
NULL
};
/**
* Initial construction data for Family 10h North Bridge, default, full features.
*/
CONST NORTHBRIDGE ROMDATA HtFam10RevDNbDefault =
{
8,
WriteRoutingTable,
WriteNodeID,
ReadDefaultLink,
EnableRoutingTables,
DisableRoutingTables,
VerifyLinkIsCoherent,
ReadToken,
WriteToken,
WriteFullRoutingTable,
IsIllegalTypeMix,
Fam10IsExceededCapable,
Fam10StopLink,
(PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
HandleSpecialNodeCase,
ReadSouthbridgeLink,
VerifyLinkIsNonCoherent,
Fam10SetConfigAddrMap,
Fam10RevDNorthBridgeFreqMask,
GatherLinkFeatures,
SetLinkRegang,
SetLinkFrequency,
SetLinkUnitIdClumping,
Fam10WriteTrafficDistribution,
Fam10WriteLinkPairDistribution,
Fam10RevDBufferOptimizations,
Fam10RevDGetNumCoresOnNode,
SetTotalNodesAndCores,
GetNodeCount,
LimitNodes,
ReadTrueLinkFailStatus,
Fam10GetNextLink,
GetPackageLink,
MakeLinkBase,
Fam10GetModuleInfo,
Fam10PostMailbox,
Fam10RetrieveMailbox,
Fam10RevDGetSocket,
(PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
(PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
0x00000001,
0x00000200,
18,
TRUE,
TRUE,
(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
(PACKAGE_HTLINK_MAP) &HtFam10RevDPackageLinkMap,
0,
(IGNORE_LINK *)&Fam10RevDIgnoreLinkList,
MakeKey,
NULL
};
/**
* Initial construction data for Family 10h North Bridge, for non-coherent only builds.
*/
CONST NORTHBRIDGE ROMDATA HtFam10NbNonCoherentOnly =
{
8,
(PF_WRITE_ROUTING_TABLE)CommonVoid,
(PF_WRITE_NODEID)CommonVoid,
(PF_READ_DEFAULT_LINK)CommonReturnZero8,
(PF_ENABLE_ROUTING_TABLES)CommonVoid,
(PF_DISABLE_ROUTING_TABLES)CommonVoid,
(PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
(PF_READ_TOKEN)CommonReturnZero8,
(PF_WRITE_TOKEN)CommonVoid,
(PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
(PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
(PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
(PF_STOP_LINK)CommonVoid,
(PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
(PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
ReadSouthbridgeLink,
VerifyLinkIsNonCoherent,
Fam10SetConfigAddrMap,
Fam10NorthBridgeFreqMask,
GatherLinkFeatures,
SetLinkRegang,
SetLinkFrequency,
SetLinkUnitIdClumping,
(PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
(PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
Fam10BufferOptimizations,
Fam10GetNumCoresOnNode,
SetTotalNodesAndCores,
GetNodeCount,
LimitNodes,
ReadTrueLinkFailStatus,
Fam10GetNextLink,
GetPackageLink,
MakeLinkBase,
Fam10GetModuleInfo,
Fam10PostMailbox,
Fam10RetrieveMailbox,
Fam10GetSocket,
(PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
(PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
0x00000001,
0x00000200,
18,
TRUE,
TRUE,
((AMD_FAMILY_10) & ~(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH)),
NULL,
0,
NULL,
MakeKey,
NULL
};
/**
* Initial construction data for Family 10h North Bridge, for RevD compatible non-coherent only builds.
*/
CONST NORTHBRIDGE ROMDATA HtFam10RevDNbNonCoherentOnly =
{
8,
(PF_WRITE_ROUTING_TABLE)CommonVoid,
(PF_WRITE_NODEID)CommonVoid,
(PF_READ_DEFAULT_LINK)CommonReturnZero8,
(PF_ENABLE_ROUTING_TABLES)CommonVoid,
(PF_DISABLE_ROUTING_TABLES)CommonVoid,
(PF_VERIFY_LINK_IS_COHERENT)CommonReturnFalse,
(PF_READ_TOKEN)CommonReturnZero8,
(PF_WRITE_TOKEN)CommonVoid,
(PF_WRITE_FULL_ROUTING_TABLE)CommonVoid,
(PF_IS_ILLEGAL_TYPE_MIX)CommonReturnFalse,
(PF_IS_EXCEEDED_CAPABLE)CommonReturnFalse,
(PF_STOP_LINK)CommonVoid,
(PF_HANDLE_SPECIAL_LINK_CASE)CommonReturnFalse,
(PF_HANDLE_SPECIAL_NODE_CASE)CommonReturnFalse,
ReadSouthbridgeLink,
VerifyLinkIsNonCoherent,
Fam10SetConfigAddrMap,
Fam10RevDNorthBridgeFreqMask,
GatherLinkFeatures,
SetLinkRegang,
SetLinkFrequency,
SetLinkUnitIdClumping,
(PF_WRITE_TRAFFIC_DISTRIBUTION)CommonVoid,
(PF_WRITE_LINK_PAIR_DISTRIBUTION)CommonVoid,
Fam10BufferOptimizations,
Fam10RevDGetNumCoresOnNode,
SetTotalNodesAndCores,
GetNodeCount,
LimitNodes,
ReadTrueLinkFailStatus,
Fam10GetNextLink,
GetPackageLink,
MakeLinkBase,
Fam10GetModuleInfo,
Fam10PostMailbox,
Fam10RetrieveMailbox,
Fam10GetSocket,
(PF_GET_ENABLED_COMPUTE_UNITS)CommonReturnZero8,
(PF_GET_DUALCORE_COMPUTE_UNITS)CommonReturnZero8,
0x00000001,
0x00000200,
18,
TRUE,
TRUE,
(AMD_FAMILY_10_HY | AMD_FAMILY_10_PH),
NULL,
0,
NULL,
MakeKey,
NULL
};

121
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.c
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@ -1,121 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge non-coherent support for Family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbNonCoherentFam10.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBNONCOHERENTFAM10_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Enable config access to a non-coherent chain for the given bus range.
*
* @HtNbMethod{::F_SET_CONFIG_ADDR_MAP}
*
* @param[in] ConfigMapIndex the map entry to set
* @param[in] SecBus The secondary bus number to use
* @param[in] SubBus The subordinate bus number to use
* @param[in] TargetNode The Node that shall be the recipient of the traffic
* @param[in] TargetLink The Link that shall be the recipient of the traffic
* @param[in] State our global state
* @param[in] Nb this northbridge
*/
VOID
Fam10SetConfigAddrMap (
IN UINT8 ConfigMapIndex,
IN UINT8 SecBus,
IN UINT8 SubBus,
IN UINT8 TargetNode,
IN UINT8 TargetLink,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT8 CurNode;
PCI_ADDR Reg;
UINT32 Temp;
Reg = Nb->MakeLinkBase (TargetNode, TargetLink, Nb);
ASSERT (SecBus <= SubBus);
ASSERT (TargetNode <= State->NodesDiscovered);
ASSERT (TargetLink < Nb->MaxLinks);
Temp = SecBus;
Reg.Address.Register += HTHOST_ISOC_REG;
LibAmdPciWriteBits (Reg, 15, 8, &Temp, Nb->ConfigHandle);
Temp = ((UINT32)SubBus << 24) + ((UINT32)SecBus << 16) + ((UINT32)TargetLink << 8) +
((UINT32)TargetNode << 4) + (UINT32)3;
for (CurNode = 0; CurNode < (State->NodesDiscovered + 1); CurNode++) {
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (CurNode),
MakePciBusFromNode (CurNode),
MakePciDeviceFromNode (CurNode),
CPU_ADDR_FUNC_01,
REG_ADDR_CONFIG_MAP0_1XE0 + (4 * ConfigMapIndex));
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
}

58
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbNonCoherentFam10.h
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@ -1,58 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge non-coherent support for Family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Enable config access to a non-coherent chain for the given bus range.
*
*/
VOID
Fam10SetConfigAddrMap (
IN UINT8 ConfigMapIndex,
IN UINT8 SecBus,
IN UINT8 SubBus,
IN UINT8 TargetNode,
IN UINT8 TargetLink,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);

222
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.c
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@ -1,222 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link optimization support specific to family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htNbOptimizationFam10.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBOPTIMIZATIONFAM10_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Northbridge specific Frequency limit.
*
* @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
*
* Return a mask that eliminates HT frequencies that cannot be used due to a slow
* northbridge frequency.
*
* @param[in] Node Result could (later) be for a specific Node
* @param[in] Interface Access to non-HT support functions.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] Nb this northbridge
*
* @return Frequency mask
*/
UINT32
Fam10NorthBridgeFreqMask (
IN UINT8 Node,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
)
{
UINT32 NbCoreFreq;
UINT32 Supported;
ASSERT (Node < MAX_NODES);
ASSERT (Interface != NULL);
// The interface to power management will return a system based result.
// So we only need to call it once, not on every link. Save the answer,
// and check to see if we can use a saved answer on subsequent calls.
//
if (Nb->CoreFrequency == 0) {
NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
NbCoreFreq = (NbCoreFreq / 100);
ASSERT (NbCoreFreq != 0);
Nb->CoreFrequency = NbCoreFreq;
} else {
NbCoreFreq = Nb->CoreFrequency;
}
//
// NbCoreFreq is minimum northbridge speed in hundreds of MHz.
// HT can not go faster than the minimum speed of the northbridge.
//
if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
// Convert frequency to bit and all less significant bits,
// by setting next power of 2 and subtracting 1.
//
Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
} else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
// Convert frequency to bit and all less significant bits,
// by setting next power of 2 and subtracting 1, noting that
// next power of two is two greater than non-extended frequencies
// (because of the register break).
//
Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
} else if (NbCoreFreq > 32) {
Supported = HT_FREQUENCY_LIMIT_MAX;
} else if (NbCoreFreq == 4) {
// unlikely cases, but include as a defensive measure, also avoid trick above
Supported = HT_FREQUENCY_LIMIT_400M;
} else if (NbCoreFreq == 2) {
Supported = HT_FREQUENCY_LIMIT_200M;
} else {
ASSERT (FALSE);
Supported = HT_FREQUENCY_LIMIT_200M;
}
return (Supported);
}
/*----------------------------------------------------------------------------------------*/
/**
* Northbridge specific Frequency limit.
*
* @HtNbMethod{::F_NORTH_BRIDGE_FREQ_MASK}
*
* Return a mask that eliminates HT frequencies that cannot be used due to a slow
* northbridge frequency.
*
* @param[in] Node Result could (later) be for a specific Node
* @param[in] Interface Access to non-HT support functions.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] Nb this northbridge
*
* @return Frequency mask
*/
UINT32
Fam10RevDNorthBridgeFreqMask (
IN UINT8 Node,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
)
{
UINT32 NbCoreFreq;
UINT32 Supported;
ASSERT (Node < MAX_NODES);
ASSERT (Interface != NULL);
// The interface to power management will return a system based result.
// So we only need to call it once, not on every link. Save the answer,
// and check to see if we can use a saved answer on subsequent calls.
//
if (Nb->CoreFrequency == 0) {
NbCoreFreq = Interface->GetMinNbCoreFreq (PlatformConfig, Nb->ConfigHandle);
NbCoreFreq = (NbCoreFreq / 100);
ASSERT (NbCoreFreq != 0);
Nb->CoreFrequency = NbCoreFreq;
} else {
NbCoreFreq = Nb->CoreFrequency;
}
// For Rev D, the Ht frequency can go twice the Nb COF, as long as it's HT3.
// (side note: we are not speculatively upgrading HT1 at 6 .. 10 to HT3,
// to avoid complicated recovery if the final speed is HT1.)
if (NbCoreFreq > 10) {
NbCoreFreq = NbCoreFreq * 2;
}
//
// NbCoreFreq is minimum northbridge speed in hundreds of MHz.
// HT can not go faster than the minimum speed of the northbridge.
//
if ((NbCoreFreq >= 6) && (NbCoreFreq <= 26)) {
// Convert frequency to bit and all less significant bits,
// by setting next power of 2 and subtracting 1.
//
Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 2)) - 1;
} else if ((NbCoreFreq > 26) && (NbCoreFreq <= 32)) {
// Convert frequency to bit and all less significant bits,
// by setting next power of 2 and subtracting 1, noting that
// next power of two is two greater than non-extended frequencies
// (because of the register break).
//
Supported = ((UINT32)1 << ((NbCoreFreq >> 1) + 4)) - 1;
} else if (NbCoreFreq > 32) {
Supported = HT_FREQUENCY_LIMIT_MAX;
} else if (NbCoreFreq == 4) {
// unlikely cases, but include as a defensive measure, also avoid trick above
Supported = HT_FREQUENCY_LIMIT_400M;
} else if (NbCoreFreq == 2) {
Supported = HT_FREQUENCY_LIMIT_200M;
} else {
ASSERT (FALSE);
Supported = HT_FREQUENCY_LIMIT_200M;
}
return (Supported);
}

74
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbOptimizationFam10.h
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@ -1,74 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link optimization support specific to family 10h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
/**
* Northbridge specific Frequency limit.
*
*/
UINT32
Fam10NorthBridgeFreqMask (
IN UINT8 Node,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
);
/**
* Northbridge specific Frequency limit.
*
*/
UINT32
Fam10RevDNorthBridgeFreqMask (
IN UINT8 Node,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
);

402
src/vendorcode/amd/agesa/f14/Proc/HT/Fam10/htNbSystemFam10.c
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@ -1,402 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* System Tuning Family 10h specific routines
*
* Support for Traffic Distribution and buffer tunings which
* can not be done in a register table.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbSystemFam10.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBSYSTEMFAM10_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/**
* Register Fields for an individual link pair.
*/
typedef struct {
UINT32 Enable:1; ///< Enable distribution on this pair.
UINT32 Asymmetric:1; ///< Links are different widths.
UINT32 MasterSelect:3; ///< The master link.
UINT32 AlternateSelect:3; ///< The alternate link.
} PAIR_SELECT_FIELDS;
/**
* Register access union for ::PAIR_SELECT_FIELDS.
*/
typedef union {
UINT32 Value; ///< access as a 32 bit value or register.
PAIR_SELECT_FIELDS Fields; ///< access individual fields.
} PAIR_SELECT;
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Set the traffic distribution register for the Links provided.
*
* @HtNbMethod{::F_WRITE_TRAFFIC_DISTRIBUTION}
*
* @param[in] Links01 coherent Links from Node 0 to 1
* @param[in] Links10 coherent Links from Node 1 to 0
* @param[in] Nb this northbridge
*/
VOID
Fam10WriteTrafficDistribution (
IN UINT32 Links01,
IN UINT32 Links10,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR TrafficDistReg;
TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
MakePciBusFromNode (0),
MakePciDeviceFromNode (0),
CPU_HTNB_FUNC_00,
REG_HT_TRAFFIC_DIST_0X164);
// Node 0
// DstLnk
LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links01, Nb->ConfigHandle);
// DstNode = 1, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
Temp = 0x0107;
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
TrafficDistReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (1),
MakePciBusFromNode (1),
MakePciDeviceFromNode (1),
CPU_HTNB_FUNC_00,
REG_HT_TRAFFIC_DIST_0X164);
// Node 1
// DstLnk
LibAmdPciWriteBits (TrafficDistReg, 23, 16, &Links10, Nb->ConfigHandle);
// DstNode = 0, cHTPrbDistEn = 1, cHTRspDistEn = 1, cHTReqDistEn = 1
Temp = 0x0007;
LibAmdPciWriteBits (TrafficDistReg, 15, 0, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Write a link pair to the link pair distribution and fixups.
*
* @HtNbMethod{::F_WRITE_LINK_PAIR_DISTRIBUTION}
*
* Set the links as a pair using the link pair index provided. Set asymmetric attribute as
* provided. If the Master Link is not currently used as the route, fixup the routes for all
* nodes which specify the alternate link.
*
* @param[in] Node Set the pair on this node
* @param[in] ConnectedNode The Node to which this link pair directly connects.
* @param[in] Pair Using this pair set in the register
* @param[in] Asymmetric True if different widths
* @param[in] MasterLink Set this as the master link and in the route
* @param[in] AlternateLink Set this as the alternate link
* @param[in] Nb this northbridge
*
*/
VOID
Fam10WriteLinkPairDistribution (
IN UINT8 Node,
IN UINT8 ConnectedNode,
IN UINT8 Pair,
IN BOOLEAN Asymmetric,
IN UINT8 MasterLink,
IN UINT8 AlternateLink,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 CurrentRoute;
UINT32 MasterRoute;
UINT32 AlternateRoute;
PAIR_SELECT Selection;
UINT32 RouteIndex;
ASSERT ((Node < MAX_NODES) && (ConnectedNode < MAX_NODES));
ASSERT (Pair < MAX_LINK_PAIRS);
ASSERT (MasterLink < Nb->MaxLinks);
ASSERT (AlternateLink < Nb->MaxLinks);
// Make the master link the route for all routes to or through NodeB, by replacing all occurrences of
// Alternate link with Master link. If routing used the master link, no update is necessary.
MasterRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (MasterLink + 1));
AlternateRoute = (((1 << Nb->BroadcastSelfBit) | Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (AlternateLink + 1));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_ROUTE0_0X40);
for (RouteIndex = 0; RouteIndex < MAX_NODES; RouteIndex++) {
Reg.Address.Register = REG_ROUTE0_0X40 + (RouteIndex * 4);
LibAmdPciReadBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
if ((CurrentRoute & AlternateRoute) != 0) {
// Since Master and Alternate are redundant, the route must use one or the other but not both.
ASSERT ((CurrentRoute & MasterRoute) == 0);
// Set the master route for Request, Response or Broadcast only if the alternate was used for that case.
// Example, use of a link as a broadcast link is typically not the same route register as its use for Request, Response.
CurrentRoute = ((CurrentRoute & ~AlternateRoute) |
((((CurrentRoute & AlternateRoute) >> (AlternateLink + 1)) << (MasterLink + 1)) & MasterRoute));
LibAmdPciWriteBits (Reg, 31, 0, &CurrentRoute, Nb->ConfigHandle);
}
}
// Set the Link Pair and Enable it
Selection.Fields.Enable = 1;
Selection.Fields.Asymmetric = Asymmetric;
Selection.Fields.MasterSelect = MasterLink;
Selection.Fields.AlternateSelect = AlternateLink;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_PAIR_DIST_0X1E0);
LibAmdPciWriteBits (
Reg,
((PAIR_SELECT_OFFSET * (Pair + 1)) - 1),
(PAIR_SELECT_OFFSET * Pair),
&Selection.Value,
Nb->ConfigHandle
);
}
/*----------------------------------------------------------------------------------------*/
/**
* Family 10h specific tunings.
*
* @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
*
* Buffer tunings are inherently northbridge specific. Check for specific configs
* which require adjustments and apply any standard workarounds to this Node.
*
* @param[in] Node the Node to tune
* @param[in] State global state
* @param[in] Nb this northbridge
*/
VOID
Fam10BufferOptimizations (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR currentPtr;
PCI_ADDR GangedReg;
UINT8 i;
ASSERT (Node < MAX_NODES);
//
// Link to XCS Token Count Tuning
//
// For each active Link that we reganged (so this unfortunately can't go into the PCI reg
// table), we have to switch the Link to XCS Token Counts to the ganged state.
// We do this here for the non - uma case, which is to write the values that would have
// been power on defaults if the Link was ganged at cold reset.
//
for (i = 0; i < (State->TotalLinks * 2); i++) {
if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
// If the Link is greater than 4, this is a subLink 1, so it is not reganged.
if ((*State->PortList)[i].Link < 4) {
currentPtr.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_LINK_XCS_TOKEN0_3X148 + (4 * (*State->PortList)[i].Link)
);
if ((*State->PortList)[i].SelRegang) {
// Handle all the regang Token count adjustments
// SubLink 0: [Probe0tok] = 2 [Rsp0tok] = 2 [PReq0tok] = 2 [Req0tok] = 2
Temp = 0xAA;
LibAmdPciWriteBits (currentPtr, 7, 0, &Temp, Nb->ConfigHandle);
// SubLink 1: [Probe1tok] = 0 [Rsp1tok] = 0 [PReq1tok] = 0 [Req1tok] = 0
Temp = 0;
LibAmdPciWriteBits (currentPtr, 23, 16, &Temp, Nb->ConfigHandle);
// [FreeTok] = 3
Temp = 3;
LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
} else {
// Read the regang bit in hardware
GangedReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode ((*State->PortList)[i].NodeID),
MakePciBusFromNode ((*State->PortList)[i].NodeID),
MakePciDeviceFromNode ((*State->PortList)[i].NodeID),
CPU_HTNB_FUNC_00,
REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
LibAmdPciReadBits (GangedReg, 0, 0, &Temp, Nb->ConfigHandle);
if (Temp == 1) {
// handle a minor adjustment for strapped ganged Links. If SelRegang is false we
// didn't do the regang, so if the bit is on then it's hardware strapped.
//
// [FreeTok] = 3
Temp = 3;
LibAmdPciWriteBits (currentPtr, 15, 14, &Temp, Nb->ConfigHandle);
}
}
}
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Family 10h specific tunings.
*
* @HtNbMethod{::F_BUFFER_OPTIMIZATIONS}
*
* Buffer tunings are inherently northbridge specific. Check for specific configs
* which require adjustments and apply any standard workarounds to this Node.
*
* @param[in] Node the Node to tune
* @param[in] State global state
* @param[in] Nb this northbridge
*/
VOID
Fam10RevDBufferOptimizations (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
UINT8 i;
FINAL_LINK_STATE FinalLinkState;
UINT32 WidthIn;
UINT32 WidthOut;
ASSERT (Node < MAX_NODES);
//
// Internal link fixup.
// When powering off internal link 2, a performance optimization may be possible where its buffers
// can be made available to the external paired sublink. If the conditions are met, do the fix up here.
//
for (i = 0; i < (State->TotalLinks * 2); i++) {
if (((*State->PortList)[i].NodeID == Node) && ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU)) {
// Is this a sublink 0 paired with internal link 2?
if (((*State->PortList)[i].Link < 4) &&
(Nb->GetPackageLink (Node, ((*State->PortList)[i].Link + 4), Nb) == HT_LIST_MATCH_INTERNAL_LINK_2)) {
FinalLinkState = State->HtInterface->GetIgnoreLink (Node, ((*State->PortList)[i].Link + 4), Nb->DefaultIgnoreLinkList, State);
// Are we ignoring the internal link 2 with Power Off?
if (FinalLinkState == POWERED_OFF) {
// Read the regang bit in hardware.
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * (*State->PortList)[i].Link));
LibAmdPciReadBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
// If it's already ganged, skip to the width fix up.
if (Temp == 0) {
// Clear EndOfChain / XmitOff on internal sublink
Reg = Nb->MakeLinkBase (Node, ((*State->PortList)[i].Link + 4), Nb);
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
Temp = 0;
State->HtFeatures->SetHtControlRegisterBits (Reg, 7, 6, &Temp, State);
// Gang the link
Nb->SetLinkRegang (Node, (*State->PortList)[i].Link, Nb);
}
// Set InLnSt = PHY_OFF in register table.
// Set sublink 0 widths to 8 bits
if ((*State->PortList)[i].SelWidthOut > 8) {
(*State->PortList)[i].SelWidthOut = 8;
}
if ((*State->PortList)[i].SelWidthIn > 8) {
(*State->PortList)[i].SelWidthIn = 8;
}
WidthOut = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
WidthIn = State->HtFeatures->ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
Temp = (WidthIn & 7) | ((WidthOut & 7) << 4);
Reg = Nb->MakeLinkBase (Node, (*State->PortList)[i].Link, Nb);
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
}
}
}
}
}

91
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@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* System Tuning Family 10h specific routines
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Set the traffic distribution register for the Links provided.
*
*/
VOID
Fam10WriteTrafficDistribution (
IN UINT32 Links01,
IN UINT32 Links10,
IN NORTHBRIDGE *Nb
);
/**
* Write a link pair to the link pair distribution and fixups.
*
*/
VOID
Fam10WriteLinkPairDistribution (
IN UINT8 Node,
IN UINT8 ConnectedNode,
IN UINT8 Pair,
IN BOOLEAN Asymmetric,
IN UINT8 MasterLink,
IN UINT8 AlternateLink,
IN NORTHBRIDGE *Nb
);
/**
* Family 10h specific tunings.
*
*/
VOID
Fam10BufferOptimizations (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);
/**
* Family 10h Rev D specific tunings.
*
*/
VOID
Fam10RevDBufferOptimizations (
IN UINT8 Node,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);

445
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@ -1,445 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge utility routines.
*
* These routines are needed for support of more than one feature area.
* Collect them in this file so build options don't remove them.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbUtilitiesFam10.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FAM10_HTNBUTILITIESFAM10_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Return the number of cores (1 based count) on Node.
*
* @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}
*
* @param[in] Node the Node that will be examined
* @param[in] Nb this northbridge
*
* @return the number of cores
*/
UINT8
Fam10GetNumCoresOnNode (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Result;
UINT32 Leveling;
UINT32 Cores;
UINT8 i;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
// Read CmpCap
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_CAPABILITY_3XE8);
LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
// Support Downcoring
Result = Cores;
Cores++;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_DOWNCORE_3X190);
LibAmdPciReadBits (Reg, 3, 0, &Leveling, Nb->ConfigHandle);
for (i = 0; i < Cores; i++) {
if ((Leveling & ((UINT32) 1 << i)) != 0) {
Result--;
}
}
return (UINT8) (Result + 1);
}
/*----------------------------------------------------------------------------------------*/
/**
* Return the number of cores (1 based count) on Node.
*
* @HtNbMethod{::F_GET_NUM_CORES_ON_NODE}.
*
* @param[in] Node the Node that will be examined
* @param[in] Nb this northbridge
*
* @return the number of cores
*/
UINT8
Fam10RevDGetNumCoresOnNode (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Result;
UINT32 Leveling;
UINT32 Cores;
UINT32 Cores2;
UINT8 i;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
// Read CmpCap
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_CAPABILITY_3XE8);
LibAmdPciReadBits (Reg, 13, 12, &Cores, Nb->ConfigHandle);
LibAmdPciReadBits (Reg, 15, 15, &Cores2, Nb->ConfigHandle);
Cores = Cores + (Cores2 << 2);
// Support Downcoring
Result = Cores;
Cores++;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_DOWNCORE_3X190);
LibAmdPciReadBits (Reg, 5, 0, &Leveling, Nb->ConfigHandle);
for (i = 0; i < Cores; i++) {
if ((Leveling & ((UINT32) 1 << i)) != 0) {
Result--;
}
}
return (UINT8) (Result + 1);
}
/*----------------------------------------------------------------------------------------*/
/**
* Get the next link for iterating over the links on a node in the correct order.
*
* @HtNbMethod{::F_GET_NEXT_LINK}
*
* Family 10h specific implementation use the Internal Link field in
* the northbridge to prioritize internal links in the order.
*
* @param[in] Node The node on which to iterate links.
* @param[in,out] Link IN: the current iteration context, OUT: the next link.
* @param[in] Nb This Northbridge, access to config pointer.
*
* @retval LinkIteratorExternal The current Link is an external link.
* @retval LinkIteratorInternal The current Link is an internal link.
* @retval LinkIteratorEnd There is no next link (Link is back to BEGIN).
*
*/
LINK_ITERATOR_STATUS
Fam10GetNextLink (
IN UINT8 Node,
IN OUT UINT8 *Link,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 InternalLinks;
UINT32 ExternalLinks;
UINT32 HigherLinks;
BOOLEAN IsInternalLink;
LINK_ITERATOR_STATUS Status;
ASSERT ((Node < MAX_NODES));
ASSERT ((*Link < Nb->MaxLinks) || (*Link == LINK_ITERATOR_BEGIN));
InternalLinks = 0;
ExternalLinks = 0;
// Read IntLnkRoute from the Link Initialization Status register.
// (Note that this register field is not reserved prior to rev D, but should be zero.)
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_INITIALIZATION_0X1A0);
LibAmdPciReadBits (Reg, 23, 16, &InternalLinks, Nb->ConfigHandle);
// The external links are all possible links which are not Internal
ExternalLinks = (((1 << Nb->MaxLinks) - 1) ^ InternalLinks);
// Can't have no possible links!
ASSERT ((ExternalLinks != 0) || (InternalLinks != 0));
if (*Link == LINK_ITERATOR_BEGIN) {
// If the request is for the first link (BEGIN), get it
if (InternalLinks != 0) {
*Link = LibAmdBitScanForward (InternalLinks);
Status = LinkIteratorInternal;
} else {
*Link = LibAmdBitScanForward (ExternalLinks);
Status = LinkIteratorExternal;
}
} else {
// If the iterator is not at the beginning, search for the next Link starting from the
// current link.
HigherLinks = InternalLinks & ~((1 << (*Link + 1)) - 1);
IsInternalLink = (BOOLEAN) ((InternalLinks & (1 << *Link)) != 0);
if (IsInternalLink && (HigherLinks != 0)) {
// We are still on internal links and there are more to do.
*Link = LibAmdBitScanForward (HigherLinks);
Status = LinkIteratorInternal;
} else {
if (IsInternalLink) {
// We are transitioning now from internal to external, so get the first external link
HigherLinks = ExternalLinks;
} else {
// We are already iterating over external links, so get the next one
HigherLinks = ExternalLinks & ~((1 << (*Link + 1)) - 1);
}
if (HigherLinks != 0) {
*Link = LibAmdBitScanForward (HigherLinks);
Status = LinkIteratorExternal;
} else {
// The end of all links
*Link = LINK_ITERATOR_BEGIN;
Status = LinkIteratorEnd;
}
}
}
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Get Info about Module Type of this northbridge
*
* @HtNbMethod{::F_GET_MODULE_INFO}
*
* Provide the Processor module type, single or multi, and the node's module id.
*
* @param[in] Node the Node
* @param[out] ModuleType 0 for Single, 1 for Multi
* @param[out] Module The module number of this node (0 if Single)
* @param[in] Nb this northbridge
*
*/
VOID
Fam10GetModuleInfo (
IN UINT8 Node,
OUT UINT8 *ModuleType,
OUT UINT8 *Module,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 MultNodeCpu;
UINT32 IntNodeNum;
ASSERT (Node < MAX_NODES);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_CAPABILITY_3XE8);
LibAmdPciReadBits (Reg, 29, 29, &MultNodeCpu, Nb->ConfigHandle);
LibAmdPciReadBits (Reg, 31, 30, &IntNodeNum, Nb->ConfigHandle);
*ModuleType = (UINT8) MultNodeCpu;
*Module = (UINT8) IntNodeNum;
}
/*----------------------------------------------------------------------------------------*/
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
* @HtNbMethod{::F_GET_SOCKET}
*
* The hardware socket naming method is not available for Family 10h prior to rev D.
*
* @param[in] Node The node for which we want the socket id.
* @param[in] TempNode The temporary node id route where the node can be accessed.
* @param[in] Nb Our Northbridge.
*
* @return The Socket Id
*/
UINT8
Fam10GetSocket (
IN UINT8 Node,
IN UINT8 TempNode,
IN NORTHBRIDGE *Nb
)
{
ASSERT ((Node < MAX_NODES));
ASSERT (TempNode < MAX_NODES);
ASSERT (Nb != NULL);
return (Node);
}
/*----------------------------------------------------------------------------------------*/
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
* @HtNbMethod{::F_GET_SOCKET}
*
* The Socket Id is strapped to the Sbi Control Register, F3X1E4[6:4]SbiAddr.
*
* @param[in] Node The node for which we want the socket id.
* @param[in] TempNode The temporary node id route where the node can be accessed.
* @param[in] Nb Our Northbridge.
*
* @return The Socket Id
*/
UINT8
Fam10RevDGetSocket (
IN UINT8 Node,
IN UINT8 TempNode,
IN NORTHBRIDGE *Nb
)
{
UINT32 Socket;
PCI_ADDR Reg;
ASSERT ((TempNode < MAX_NODES));
ASSERT ((Node < MAX_NODES));
// Read SbiAddr
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (TempNode),
MakePciBusFromNode (TempNode),
MakePciDeviceFromNode (TempNode),
CPU_NB_FUNC_03,
REG_NB_SBI_CONTROL_3X1E4);
LibAmdPciReadBits (Reg, 6, 4, &Socket, Nb->ConfigHandle);
return ((UINT8) Socket);
}
/*----------------------------------------------------------------------------------------*/
/**
* Post info to AP cores via a mailbox.
*
* @HtNbMethod{::F_POST_MAILBOX}
*
* Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
* and module info.
*
* @param[in] Node the Node
* @param[in] ApMailboxes The info to post
* @param[in] Nb this northbridge
*
*/
VOID
Fam10PostMailbox (
IN UINT8 Node,
IN AP_MAILBOXES ApMailboxes,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
ASSERT (Node < MAX_NODES);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_MCA_LINK_THRESHOLD_3X168);
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailInfo.Info, Nb->ConfigHandle);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_MCA_L3_THRESHOLD_3X170);
LibAmdPciWriteBits (Reg, 11, 0, &ApMailboxes.ApMailExtInfo.Info, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Retrieve info from a node's mailbox.
*
* @HtNbMethod{::F_RETRIEVE_MAILBOX}
*
* Use the link MCA counter register as a PCI -> MSR mailbox, for info such as node id,
* and module info.
*
* @param[in] Node the Node
* @param[in] Nb this northbridge
*
* @return The ap mailbox info
*
*/
AP_MAIL_INFO
Fam10RetrieveMailbox (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
AP_MAIL_INFO ApMailInfo;
ASSERT (Node < MAX_NODES);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_NB_FUNC_03,
REG_NB_MCA_LINK_THRESHOLD_3X168);
LibAmdPciReadBits (Reg, 11, 0, &ApMailInfo.Info, Nb->ConfigHandle);
return ApMailInfo;
}

129
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@ -1,129 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge utility routines.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Return the number of cores (1 based count) on Node.
*
*/
UINT8
Fam10GetNumCoresOnNode (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Return the number of cores (1 based count) on Node.
*
*/
UINT8
Fam10RevDGetNumCoresOnNode (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Get the next link for iterating over the links on a node in the correct order.
*
*/
LINK_ITERATOR_STATUS
Fam10GetNextLink (
IN UINT8 Node,
IN OUT UINT8 *Link,
IN NORTHBRIDGE *Nb
);
/**
* Get Info about Module Type of this northbridge
*
*/
VOID
Fam10GetModuleInfo (
IN UINT8 Node,
OUT UINT8 *ModuleType,
OUT UINT8 *Module,
IN NORTHBRIDGE *Nb
);
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
*/
UINT8
Fam10GetSocket (
IN UINT8 Node,
IN UINT8 TempNode,
IN NORTHBRIDGE *Nb
);
/**
* Implement the hardware method of doing Socket Naming, by accessing this northbridge's Socket Id register.
*
*/
UINT8
Fam10RevDGetSocket (
IN UINT8 Node,
IN UINT8 TempNode,
IN NORTHBRIDGE *Nb
);
/**
* Post info to AP cores via a mailbox.
*
*/
VOID
Fam10PostMailbox (
IN UINT8 Node,
IN AP_MAILBOXES ApMailboxes,
IN NORTHBRIDGE *Nb
);
/**
* Retrieve info from a node's mailbox.
*
*/
AP_MAIL_INFO
Fam10RetrieveMailbox (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);

783
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.c
View File

@ -1,783 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Discovery Routines.
*
* Contains routines for discovery, along with Temporary routing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNotify.h"
#include "htNb.h"
#include "htFeatDynamicDiscovery.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATDYNAMICDISCOVERY_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
#define LOGICAL_PROCESSOR_NONE 0xFF
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/**
* Status result from exploring for a new node on a link.
*/
typedef enum {
ExploreNodeStatusNew, ///< A new node was discovered
ExploreNodeStatusGood, ///< A new link to an already known node was discovered
ExploreNodeStatusStop, ///< Discovery must halt now.
ExploreNodeStatusIgnore, ///< A new node was ignored on purpose.
ExploreNodeStatusMax ///< Use for bounds check and limit only
} EXPLORE_NODE_STATUS;
/**
* Save all the information needed about a node at its discovery.
*
* When we can access the node at a known temporary route, read everything needed
* to do node to socket mapping, post to ap mailbox at later times.
*/
typedef struct {
UINT8 LogicalProcessor; ///< Independent of Node,Socket group nodes into logical
///< processors based on discovery.
UINT8 CurrentNode; ///< The node from which discovery occurred.
UINT8 CurrentLink; ///< The link on that node which we explored.
UINT8 PackageLink; ///< The package level link corresponding to CurrentLink.
UINT8 CurrentModuleType; ///< The current node's module type, Single or Multiple.
UINT8 CurrentModule; ///< This current node's module id.
UINT8 HardwareSocket; ///< Save the hardware socket strap (for hardware socket method).
UINT8 NewModuleType; ///< The new node's module type, Single or Multiple.
UINT8 NewModule; ///< The new node's module id.
} NEW_NODE_SAVED_INFO_ITEM;
/**
* A "no info" initializer for saved new node info.
*/
STATIC CONST NEW_NODE_SAVED_INFO_ITEM ROMDATA NoInfoSavedYet =
{
LOGICAL_PROCESSOR_NONE, 0, 0, 0, 0, 0, 0, 0
};
/**
* A list of all the new node info, indexed by each new node's nodeid.
*/
typedef NEW_NODE_SAVED_INFO_ITEM (*NEW_NODE_SAVED_INFO_LIST) [MAX_NODES];
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** GENERIC HYPERTRANSPORT DISCOVERY CODE ***
***************************************************************************/
/*-----------------------------------------------------------------------------------*/
/**
* Ensure a request / response route from target Node to bsp.
*
* Since target Node is always a predecessor of actual target Node, each Node gets a
* route to actual target on the Link that goes to target. The routing produced by
* this routine is adequate for config access during discovery, but NOT for coherency.
*
* @param[in] TargetNode the path to actual target goes through target
* @param[in] ActualTarget the ultimate target being routed to
* @param[in] State our global state, port config info
*
*/
VOID
STATIC
routeFromBSP (
IN UINT8 TargetNode,
IN UINT8 ActualTarget,
IN STATE_DATA *State
)
{
UINT8 PredecessorNode;
UINT8 PredecessorLink;
UINT8 CurrentPair;
if (TargetNode == 0) {
return; // BSP has no predecessor, stop
}
// Search for the Link that connects TargetNode to its predecessor
CurrentPair = 0;
while ((*State->PortList)[CurrentPair*2 + 1].NodeID != TargetNode) {
CurrentPair++;
ASSERT (CurrentPair < State->TotalLinks);
}
PredecessorNode = (*State->PortList)[ (CurrentPair * 2)].NodeID;
PredecessorLink = (*State->PortList)[ (CurrentPair * 2)].Link;
// Recursively call self to ensure the route from the BSP to the Predecessor
// Node is established
routeFromBSP (PredecessorNode, ActualTarget, State);
State->Nb->WriteRoutingTable (PredecessorNode, ActualTarget, PredecessorLink, State->Nb);
}
/*----------------------------------------------------------------------------------------*/
/**
* Test Compatibility of a new node, and handle failure.
*
* Make the compatibility test call for the northbridge.
* If the new node is incompatible, force 1P. Notify the event.
* Additionally, invoke the northbridge stop link method, to
* implement isolation of the BSP from any incompatible node.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] CurrentLink The Link on that node to explore.
* @param[in] State Access to Northbridge interface.
*
* @retval TRUE Check is Ok
* @retval FALSE Check failed and is handled
*/
BOOLEAN
STATIC
CheckCompatible (
IN UINT8 CurrentNode,
IN UINT8 CurrentLink,
IN STATE_DATA *State
)
{
UINT8 NodeToKill;
BOOLEAN Result;
Result = TRUE;
// Check the northbridge of the Node we just found, to make sure it is compatible
// before doing anything else to it.
//
if (State->Nb->IsIllegalTypeMix ((CurrentNode + 1), State->Nb)) {
IDS_ERROR_TRAP;
// Notify BIOS of event
NotifyFatalCohProcessorTypeMix (
CurrentNode,
CurrentLink,
State->NodesDiscovered,
State
);
// If Node is not compatible, force boot to 1P
// If they are not compatible stop cHT init and:
// 1. Disable all cHT Links on the BSP
// 2. Configure the BSP routing tables as a UP.
// 3. Notify main BIOS.
//
State->NodesDiscovered = 0;
State->TotalLinks = 0;
// Abandon our coherent Link data structure. At this point there may
// be coherent Links on the BSP that are not yet in the portList, and
// we have to turn them off anyway. So depend on the hardware to tell us.
//
for (CurrentLink = 0; CurrentLink < State->Nb->MaxLinks; CurrentLink++) {
// Stop all Links which are connected, coherent, and ready
if (State->Nb->VerifyLinkIsCoherent (0, CurrentLink, State->Nb)) {
State->Nb->StopLink (0, CurrentLink, State, State->Nb);
}
}
for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
}
State->HtInterface->CleanMapsAfterError (State);
// End Coherent Discovery
Result = FALSE;
}
return Result;
}
/*----------------------------------------------------------------------------------------*/
/**
* Check the system MP capability with a new node and handle any failure.
*
* Invoke the northbridge MP capability check. If it fails, notify the event and force
* 1P. Should not need to stop links on the BSP.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] CurrentLink The Link on that node to explore.
* @param[in] State Access to Northbridge interface.
*
* @retval TRUE Check is Ok
* @retval FALSE Check Failed and is handled
*/
BOOLEAN
STATIC
CheckCapable (
IN UINT8 CurrentNode,
IN UINT8 CurrentLink,
IN STATE_DATA *State
)
{
UINT8 NodeToKill;
BOOLEAN Result;
Result = TRUE;
// Check the capability of northbridges against the currently known configuration
if (State->Nb->IsExceededCapable ((CurrentNode + 1), State, State->Nb)) {
IDS_ERROR_TRAP;
// Notify BIOS of event
NotifyFatalCohMpCapMismatch (
CurrentNode,
CurrentLink,
State->SysMpCap,
State->NodesDiscovered,
State
);
State->NodesDiscovered = 0;
State->TotalLinks = 0;
for (NodeToKill = 0; NodeToKill < MAX_NODES; NodeToKill++) {
State->Nb->WriteFullRoutingTable (0, NodeToKill, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
}
State->HtInterface->CleanMapsAfterError (State);
// End Coherent Discovery
Result = FALSE;
}
return Result;
}
/*----------------------------------------------------------------------------------------*/
/**
* Make all the tests needed to determine if a link should be added to the system data structure.
*
* The link should be added to the system data structure if it is:
* - not being Ignored on this boot
* - not having a hard failure
* - coherent and connected
* - not already in the system data structure
* - not subject to some special handling case.
* .
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] CurrentLink The Link on that node to explore.
* @param[in] State Access to Northbridge interface.
*
* @retval FALSE This link should not be added.
* @retval TRUE This link should explored and added to the system.
*/
BOOLEAN
STATIC
IsLinkToAdd (
IN UINT8 CurrentNode,
IN UINT8 CurrentLink,
IN STATE_DATA *State
)
{
BOOLEAN Linkfound;
UINTN Port;
FINAL_LINK_STATE FinalLinkState;
BOOLEAN Result;
Result = FALSE;
FinalLinkState = State->HtInterface->GetIgnoreLink (CurrentNode, CurrentLink, State->Nb->DefaultIgnoreLinkList, State);
if ((FinalLinkState != MATCHED) && (FinalLinkState != POWERED_OFF)) {
if (!State->Nb->ReadTrueLinkFailStatus (CurrentNode, CurrentLink, State, State->Nb)) {
// Make sure that the Link is connected, coherent, and ready
if (State->Nb->VerifyLinkIsCoherent (CurrentNode, CurrentLink, State->Nb)) {
// Test to see if the CurrentLink has already been explored
Linkfound = FALSE;
for (Port = 0; Port < State->TotalLinks; Port++) {
if ((((*State->PortList)[ (Port * 2 + 1)].NodeID == CurrentNode) &&
((*State->PortList)[ (Port * 2 + 1)].Link == CurrentLink)) ||
(((*State->PortList)[ (Port * 2)].NodeID == CurrentNode) &&
((*State->PortList)[ (Port * 2)].Link == CurrentLink))) {
Linkfound = TRUE;
break;
}
}
if (!Linkfound) {
if (!State->Nb->HandleSpecialLinkCase (CurrentNode, CurrentLink, State, State->Nb)) {
Result = TRUE;
}
}
}
}
} else {
if (FinalLinkState == POWERED_OFF) {
State->Nb->StopLink (CurrentNode, CurrentLink, State, State->Nb);
}
}
return Result;
}
/*----------------------------------------------------------------------------------------*/
/**
* Explore for a new node over a link, handling whatever is found.
*
* Open a temporary route over a link on the current node.
* Make checks for compatibility and capability in the proper sequence.
* If the node found is new, set a token to it, so it will be recognized in the
* future, and notify an event for finding a new node.
* If the node is already found (token is set), just return status.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] CurrentLink The Link on that node to explore.
* @param[in] LogicalProcessor The processor to update in the maps.
* @param[in,out] NewNodeSavedInfo The saved info for nodes in that processor.
* @param[in] State Access to Northbridge interface.
*
* @retval ExploreNodeStatusNew A new node was found
* @retval ExploreNodeStatusGood This is a good link to an already known node
* @retval ExploreNodeStatusStop Stop Coherent Discovery
*/
EXPLORE_NODE_STATUS
STATIC
ExploreNode (
IN UINT8 CurrentNode,
IN UINT8 CurrentLink,
IN UINT8 LogicalProcessor,
IN OUT NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
IN STATE_DATA *State
)
{
UINT8 Token;
EXPLORE_NODE_STATUS Status;
// Modify CurrentNode's routing table to use CurrentLink to send
// traffic to CurrentNode + 1
//
State->Nb->WriteRoutingTable (CurrentNode, (CurrentNode + 1), CurrentLink, State->Nb);
if (!State->Nb->HandleSpecialNodeCase ((CurrentNode + 1), CurrentLink, State, State->Nb)) {
if (CheckCompatible (CurrentNode, CurrentLink, State)) {
// Read Token from Current + 1
Token = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
ASSERT (Token <= State->NodesDiscovered);
if (Token == 0) {
State->NodesDiscovered++;
ASSERT (State->NodesDiscovered < MAX_NODES);
if (CheckCapable (CurrentNode, CurrentLink, State)) {
Token = State->NodesDiscovered;
State->Nb->WriteToken ((CurrentNode + 1), Token, State->Nb);
// Fill in Saved New Node info for the discovered node.
// We do this so we don't have to keep a temporary route open to it.
// So we save everything that might be needed to set the socket and node
// maps for either the software or hardware method.
//
(*NewNodeSavedInfo)[Token].LogicalProcessor = LogicalProcessor;
(*NewNodeSavedInfo)[Token].CurrentNode = CurrentNode;
(*NewNodeSavedInfo)[Token].CurrentLink = CurrentLink;
(*NewNodeSavedInfo)[Token].PackageLink = State->Nb->GetPackageLink (CurrentNode, CurrentLink, State->Nb);
(*NewNodeSavedInfo)[Token].HardwareSocket = State->Nb->GetSocket (Token, (CurrentNode + 1), State->Nb);
State->Nb->GetModuleInfo (
CurrentNode,
&((*NewNodeSavedInfo)[Token].CurrentModuleType),
&((*NewNodeSavedInfo)[Token].CurrentModule),
State->Nb
);
State->Nb->GetModuleInfo (
(CurrentNode + 1),
&((*NewNodeSavedInfo)[Token].NewModuleType),
&((*NewNodeSavedInfo)[Token].NewModule),
State->Nb
);
// Notify BIOS with info
NotifyInfoCohNodeDiscovered (
CurrentNode,
CurrentLink,
Token,
(CurrentNode + 1),
State
);
Status = ExploreNodeStatusNew;
} else {
// Failed Capable
Status = ExploreNodeStatusStop;
}
} else {
// Not a new node, token already set
Status = ExploreNodeStatusGood;
}
} else {
// Failed Compatible
Status = ExploreNodeStatusStop;
}
} else {
// Ignore this node
Status = ExploreNodeStatusIgnore;
}
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* Process all the saved new node info for the current processor.
*
* When all nodes in the processor have been discovered, we can process all the saved
* info about the nodes. We add each node to the socket and node maps.
*
* @param[in] LogicalProcessor The processor to update in the maps.
* @param[in] NewNodeSavedInfo The saved info for nodes in that processor.
* @param[in] State Our system representation.
*/
VOID
STATIC
ProcessSavedNodeInfo (
IN UINT8 LogicalProcessor,
IN NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo,
IN STATE_DATA *State
)
{
UINT8 NewNode;
UINT8 HardwareSocket;
// Can't have more processors than nodes, just more (or equal) nodes than processors.
ASSERT (LogicalProcessor <= (State->NodesDiscovered));
HardwareSocket = 0xFF;
// Find the Hardware Socket value to use (if we are using the hardware socket naming method).
// The new nodes are the ones in this processor, so find the one that is module 0.
for (NewNode = 0; NewNode < (State->NodesDiscovered + 1); NewNode++) {
if (((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) &&
((*NewNodeSavedInfo)[NewNode].NewModule == 0)) {
HardwareSocket = (*NewNodeSavedInfo)[NewNode].HardwareSocket;
break;
}
}
// We must have found a result, however, the hardware socket value doesn't have to be correct
// unless we are using the hardware socket naming method. Northbridge code should return the
// node number for the hardware socket if hardware socket strapping is not supported (i.e. no sbi).
ASSERT (HardwareSocket != 0xFF);
// Set the node to socket maps for this processor. Node zero is always handled specially,
// so skip it in this loop.
for (NewNode = 1; NewNode < (State->NodesDiscovered + 1); NewNode++) {
if ((*NewNodeSavedInfo)[NewNode].LogicalProcessor == LogicalProcessor) {
// For the currently discovered logical processor, update node to socket
// map for all the processor's nodes.
State->HtInterface->SetNodeToSocketMap (
(*NewNodeSavedInfo)[NewNode].CurrentNode,
(*NewNodeSavedInfo)[NewNode].CurrentModule,
(*NewNodeSavedInfo)[NewNode].PackageLink,
NewNode,
HardwareSocket,
(*NewNodeSavedInfo)[NewNode].NewModule,
State);
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Create and add a new link to the system data structure.
*
* Add the two port list data structures, source first, initializing
* the two node ids and the link values. The node id of the remote
* node is its token value. Also, update the adjacency matrix and
* node degree table.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] CurrentLink The Link on that node to explore.
* @param[in] TempRoute The temporary node route that goes over that link.
* @param[in] State Access to Northbridge interface.
*
*/
VOID
STATIC
AddLinkToSystem (
IN UINT8 CurrentNode,
IN UINT8 CurrentLink,
IN UINT8 TempRoute,
IN STATE_DATA *State
)
{
UINT8 Token;
ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
Token = State->Nb->ReadToken (TempRoute, State->Nb);
(*State->PortList)[State->TotalLinks * 2].Type = PORTLIST_TYPE_CPU;
(*State->PortList)[State->TotalLinks * 2].Link = CurrentLink;
(*State->PortList)[State->TotalLinks * 2].NodeID = CurrentNode;
(*State->PortList)[State->TotalLinks * 2 + 1].Type = PORTLIST_TYPE_CPU;
(*State->PortList)[State->TotalLinks * 2 + 1].Link = State->Nb->ReadDefaultLink (TempRoute, State->Nb);
(*State->PortList)[State->TotalLinks * 2 + 1].NodeID = Token;
State->TotalLinks++;
if ( !State->Fabric->SysMatrix[CurrentNode][Token] ) {
State->Fabric->SysDegree[CurrentNode]++;
State->Fabric->SysDegree[Token]++;
State->Fabric->SysMatrix[CurrentNode][Token] = TRUE;
State->Fabric->SysMatrix[Token][CurrentNode] = TRUE;
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Start discovery from a new node.
*
* If the node is not the BSP, establish a route between the node and the
* BSP for request/response.
* Set the node id, and enable routing on this node. This gives us control
* on that node to isolate links, by specifying each link in turn as the route
* to a possible new node.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] State Access to Northbridge interface.
*
*/
VOID
STATIC
StartFromANewNode (
IN UINT8 CurrentNode,
IN STATE_DATA *State
)
{
if (CurrentNode != 0) {
// Set path from BSP to CurrentNode
routeFromBSP (CurrentNode, CurrentNode, State);
// Set path from BSP to CurrentNode for CurrentNode + 1 if
// CurrentNode + 1 != MAX_NODES
//
if ((CurrentNode + 1) != MAX_NODES) {
routeFromBSP (CurrentNode, (CurrentNode + 1), State);
}
// Configure CurrentNode to route traffic to the BSP through its
// default Link
//
State->Nb->WriteRoutingTable (CurrentNode, 0, State->Nb->ReadDefaultLink (CurrentNode, State->Nb), State->Nb);
}
// Set CurrentNode's NodeID field to CurrentNode
State->Nb->WriteNodeID (CurrentNode, CurrentNode, State->Nb);
// Enable routing tables on CurrentNode
State->Nb->EnableRoutingTables (CurrentNode, State->Nb);
}
/*----------------------------------------------------------------------------------------*/
/**
* Back up from exploring a one-deep internal node.
*
* When a newly discovered node has internal package links to another
* node in the same processor, discovery moves to that node to do the
* internal links. Afterwards, this routine provides recovery from that.
* The node needs to respond again using deflnk rather than routing, so
* that connections from other nodes to that one can be identified.
*
* @param[in] CurrentNode The node we are exploring from
* @param[in] State Access to Northbridge interface.
*
*/
VOID
STATIC
BackUpFromANode (
IN UINT8 CurrentNode,
IN STATE_DATA *State
)
{
if (CurrentNode != 0) {
// Disable routing tables on CurrentNode
State->Nb->DisableRoutingTables (CurrentNode, State->Nb);
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Dynamically Discover all coherent devices in the system.
*
* @HtFeatMethod{::F_COHERENT_DISCOVERY}
*
* Initialize some basics like Node IDs and total Nodes found in the
* process. As we go we also build a representation of the discovered
* system which we will use later to program the routing tables.
* During this step, the routing is via default Link back to BSP and
* to each new Node on the Link it was discovered on (no coherency is
* active yet).
*
* In the case of multiple nodes per processor, do a one deep exploration of internal links
* to ensure those node pairs are always numbered n, n + 1.
*
* @param[in,out] State our global state
*
*/
VOID
CoherentDiscovery (
IN OUT STATE_DATA *State
)
{
UINT8 CurrentNode;
UINT8 OneDeepNode;
UINT8 OneDeepLink;
UINT8 CurrentLink;
UINT8 LogicalProcessor;
EXPLORE_NODE_STATUS ExplorationStatus;
LINK_ITERATOR_STATUS LinkIteratorStatus;
NEW_NODE_SAVED_INFO_ITEM NewNodeSavedInfoItems [MAX_NODES];
NEW_NODE_SAVED_INFO_LIST NewNodeSavedInfo;
// Initially no info exists for any node, but the BSP is part of logical processor zero.
for (CurrentNode = 0; CurrentNode < MAX_NODES; CurrentNode++) {
NewNodeSavedInfoItems [CurrentNode] = NoInfoSavedYet;
}
NewNodeSavedInfoItems[0].LogicalProcessor = 0;
NewNodeSavedInfoItems[0].HardwareSocket = State->Nb->GetSocket (0, 0, State->Nb);
State->Nb->GetModuleInfo (0, &NewNodeSavedInfoItems[0].NewModuleType, &NewNodeSavedInfoItems[0].NewModule, State->Nb);
NewNodeSavedInfo = (NEW_NODE_SAVED_INFO_LIST) NewNodeSavedInfoItems;
CurrentNode = 0;
CurrentLink = LINK_ITERATOR_BEGIN;
LogicalProcessor = 0;
// An initial status, for node zero if you will.
ExplorationStatus = ExploreNodeStatusGood;
//
// Entries are always added in pairs, the even indices are the 'source'
// side closest to the BSP, the odd indices are the 'destination' side
//
while ((CurrentNode <= State->NodesDiscovered) && (ExplorationStatus != ExploreNodeStatusStop)) {
StartFromANewNode (CurrentNode, State);
//
// Explore all internal links
//
LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
while ((LinkIteratorStatus == LinkIteratorInternal) &&
(ExplorationStatus != ExploreNodeStatusStop)) {
if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
if ((ExplorationStatus == ExploreNodeStatusGood) ||
(ExplorationStatus == ExploreNodeStatusNew)) {
AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
}
}
LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
}
if (CurrentNode == 0) {
// The BSP processor is completely discovered now.
ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
LogicalProcessor++;
}
//
// Explore all the external links from this node.
//
// Starting this iteration using the link that we last got in the iteration above.
while ((LinkIteratorStatus == LinkIteratorExternal) &&
(ExplorationStatus != ExploreNodeStatusStop)) {
if (IsLinkToAdd (CurrentNode, CurrentLink, State)) {
ExplorationStatus = ExploreNode (CurrentNode, CurrentLink, LogicalProcessor, NewNodeSavedInfo, State);
if (ExplorationStatus == ExploreNodeStatusNew) {
AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
// If this is a new node, we need to explore to its internal mate, if any.
// This allows us to keep internal node pairs as ids n, n+1
// We use special link and node variables so we can keep our context.
OneDeepLink = 0xFF;
OneDeepNode = State->Nb->ReadToken ((CurrentNode + 1), State->Nb);
StartFromANewNode (OneDeepNode, State);
LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
while ((LinkIteratorStatus == LinkIteratorInternal) &&
(ExplorationStatus != ExploreNodeStatusStop)) {
if (IsLinkToAdd (OneDeepNode, OneDeepLink, State)) {
ExplorationStatus = ExploreNode (OneDeepNode, OneDeepLink, LogicalProcessor, NewNodeSavedInfo, State);
if ((ExplorationStatus == ExploreNodeStatusGood) ||
(ExplorationStatus == ExploreNodeStatusNew)) {
AddLinkToSystem (OneDeepNode, OneDeepLink, (OneDeepNode + 1), State);
}
}
LinkIteratorStatus = State->Nb->GetNextLink (OneDeepNode, &OneDeepLink, State->Nb);
}
// Since we completed all the node's internal links, we found all the nodes in that processor.
ProcessSavedNodeInfo (LogicalProcessor, NewNodeSavedInfo, State);
LogicalProcessor++;
// Restore node to discoverable state. Otherwise you can't tell what links it is connected on.
BackUpFromANode (OneDeepNode, State);
} else {
if (ExplorationStatus == ExploreNodeStatusGood) {
AddLinkToSystem (CurrentNode, CurrentLink, (CurrentNode + 1), State);
}
}
}
LinkIteratorStatus = State->Nb->GetNextLink (CurrentNode, &CurrentLink, State->Nb);
}
CurrentNode++;
}
}

80
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatDynamicDiscovery.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Discovery Interface.
*
* Contains interface to the coherent discovery feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_DYNAMIC_DISCOVERY_H_
#define _HT_FEAT_DYNAMIC_DISCOVERY_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Dynamically Discover all coherent devices in the system.
*
*/
VOID
CoherentDiscovery (
IN OUT STATE_DATA *State
);
#endif /* _HT_FEAT_DYNAMIC_DISCOVERY_H_ */

218
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.c
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@ -1,218 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Routines for re-ganging Links.
*
* Implement the reganging feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htFeatGanging.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATGANGING_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Link Optimization ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
* @HtFeatMethod{::F_REGANG_LINKS}
*
* If they do, update the port list data to indicate that this should be done.
* @note no actual hardware state is changed in this routine.
*
* @param[in,out] State Our global state
*/
VOID
RegangLinks (
IN OUT STATE_DATA *State
)
{
FINAL_LINK_STATE FinalLinkState;
UINT8 i;
UINT8 j;
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
// Data validation
ASSERT ((*State->PortList)[i].Type < 2 && (*State->PortList)[i].Link < State->Nb->MaxLinks);
ASSERT ((*State->PortList)[i + 1].Type < 2 && (*State->PortList)[i + 1].Link < State->Nb->MaxLinks);
// Regang is false unless we pass all conditions below
(*State->PortList)[i].SelRegang = FALSE;
(*State->PortList)[i + 1].SelRegang = FALSE;
// Only process cpu to cpu Links
if ( ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) ||
((*State->PortList)[i + 1].Type != PORTLIST_TYPE_CPU)) {
continue;
}
for (j = i + 2; j < State->TotalLinks*2; j += 2) {
// Only process cpu to cpu Links
if ( ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) ||
((*State->PortList)[j + 1].Type != PORTLIST_TYPE_CPU) ) {
continue;
}
// Links must be from the same source
if ((*State->PortList)[i].NodeID != (*State->PortList)[j].NodeID) {
continue;
}
// Link must be to the same target
if ((*State->PortList)[i + 1].NodeID != (*State->PortList)[j + 1].NodeID) {
continue;
}
// Ensure same source base port
if (((*State->PortList)[i].Link & 3) != ((*State->PortList)[j].Link & 3)) {
continue;
}
// Ensure same destination base port
if (((*State->PortList)[i + 1].Link & 3) != ((*State->PortList)[j + 1].Link & 3)) {
continue;
}
// Ensure subLink0 routes to subLink0
if (((*State->PortList)[i].Link & 4) != ((*State->PortList)[i + 1].Link & 4)) {
continue;
}
// (therefore subLink1 routes to subLink1)
ASSERT (((*State->PortList)[j].Link & 4) == ((*State->PortList)[j + 1].Link & 4));
FinalLinkState = State->HtInterface->GetSkipRegang ((*State->PortList)[i].NodeID,
(*State->PortList)[i].Link & 0x03,
(*State->PortList)[i + 1].NodeID,
(*State->PortList)[i + 1].Link & 0x03,
State);
if (FinalLinkState == MATCHED) {
continue;
} else if (FinalLinkState == POWERED_OFF) {
// StopLink will be done on the sublink 1, thus OR in 4 to the link to ensure it.
State->Nb->StopLink ((*State->PortList)[i].NodeID, ((*State->PortList)[i].Link | 4), State, State->Nb);
State->Nb->StopLink ((*State->PortList)[i + 1].NodeID, ((*State->PortList)[i + 1].Link | 4), State, State->Nb);
}
//
// Create a ganged portlist entry for the two regang-able subLinks.
//
// All info will be that of subLink zero.
// (If Link discovery order was other than ascending, fix the .Pointer field too.)
//
//
if (((*State->PortList)[i].Link & 4) != 0) {
(*State->PortList)[i].Pointer = (*State->PortList)[j].Pointer;
(*State->PortList)[i + 1].Pointer = (*State->PortList)[j + 1].Pointer;
}
(*State->PortList)[i].Link &= 0x03; // Force to point to subLink0
(*State->PortList)[i + 1].Link &= 0x03;
// If powered off, sublink 1 is removed but the link is still 8 bits.
if (FinalLinkState != POWERED_OFF) {
(*State->PortList)[i].SelRegang = TRUE; // Enable Link reganging
(*State->PortList)[i + 1].SelRegang = TRUE;
(*State->PortList)[i].PrvWidthOutCap = HT_WIDTH_16_BITS;
(*State->PortList)[i + 1].PrvWidthOutCap = HT_WIDTH_16_BITS;
(*State->PortList)[i].PrvWidthInCap = HT_WIDTH_16_BITS;
(*State->PortList)[i + 1].PrvWidthInCap = HT_WIDTH_16_BITS;
}
// Delete PortList[j, j + 1], slow but easy to debug implementation
State->TotalLinks--;
LibAmdMemCopy (&((*State->PortList)[j]),
&((*State->PortList)[j + 2]),
sizeof (PORT_DESCRIPTOR)*(State->TotalLinks* 2 - j),
State->ConfigHandle);
LibAmdMemFill (&((*State->PortList)[State->TotalLinks * 2]), INVALID_LINK, (sizeof (PORT_DESCRIPTOR) * 2), State->ConfigHandle);
break; // Exit loop, advance to PortList[i + 2]
}
}
}

80
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatGanging.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link Reganging Interface.
*
* Contains interface to the Reganging feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_GANGING_H_
#define _HT_FEAT_GANGING_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Test the subLinks of a Link to see if they qualify to be reganged.
*
*/
VOID
RegangLinks (
IN OUT STATE_DATA *State
);
#endif /* _HT_FEAT_GANGING_H_ */

375
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.c
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@ -1,375 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Non-Coherent Discovery Routines.
*
* Contains routines for enumerating and initializing non-coherent devices.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35740 $ @e \$Date: 2010-07-30 00:04:17 +0800 (Fri, 30 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNotify.h"
#include "htNb.h"
#include "htFeatNoncoherent.h"
#include "htFeatOptimization.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATNONCOHERENT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
#define NO_DEVICE 0xFFFFFFFFull
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Non-coherent init code ***
*** Algorithms ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Process a non-coherent Link.
*
* @HtFeatMethod{::F_PROCESS_LINK}
*
* Enable a range of bus numbers, and set the device ID for all devices found. Add
* non-coherent devices, links to the system data structure.
*
* @param[in] Node Node on which to process nc init
* @param[in] Link The non-coherent Link on that Node
* @param[in] IsCompatChain Is this the chain with the southbridge? TRUE if yes.
* @param[in,out] State our global state
*/
VOID
ProcessLink (
IN UINT8 Node,
IN UINT8 Link,
IN BOOLEAN IsCompatChain,
IN OUT STATE_DATA *State
)
{
UINT8 SecBus;
UINT8 SubBus;
UINT32 CurrentBuid;
UINT32 Temp;
UINT32 UnitIdCount;
PCI_ADDR CurrentPtr;
PCI_ADDR Link1ControlRegister;
UINT8 Depth;
BUID_SWAP_LIST *SwapPtr;
UINT8 LastLink;
BOOLEAN IsCaveDevice;
ASSERT ((Node < MAX_NODES) && (Link < State->Nb->MaxLinks));
if (!State->HtInterface->GetOverrideBusNumbers (Node, Link, &SecBus, &SubBus, State)) {
// Assign Bus numbers
if (State->AutoBusCurrent >= State->HtBlock->AutoBusMax) {
// If we run out of Bus Numbers, notify and skip this chain
//
IDS_ERROR_TRAP;
NotifyErrorNcohBusMaxExceed (Node, Link, State->AutoBusCurrent, State);
return;
}
if (State->UsedCfgMapEntries >= 4) {
// If we have used all the PCI Config maps we can't add another chain.
// Notify and if call back is unimplemented or returns, skip this chain.
//
IDS_ERROR_TRAP;
NotifyErrorNcohCfgMapExceed (Node, Link, State);
return;
}
SecBus = State->AutoBusCurrent;
SubBus = SecBus + State->HtBlock->AutoBusIncrement - 1;
State->AutoBusCurrent = State->AutoBusCurrent + State->HtBlock->AutoBusIncrement;
}
State->Nb->SetConfigAddrMap (State->UsedCfgMapEntries, SecBus, SubBus, Node, Link, State, State->Nb);
State->UsedCfgMapEntries++;
if (State->HtInterface->GetManualBuidSwapList (Node, Link, &SwapPtr, State)) {
// Manual non-coherent BUID assignment
AGESA_TESTPOINT (TpProcHtManualNc, State->ConfigHandle);
if (!IsCompatChain || !State->IsUsingRecoveryHt) {
// If this is the not southbridge chain or Recovery HT was not used
// then we need to assign BUIDs here.
//
Depth = 0;
// Assign BUID's per manual override
while (SwapPtr->Swaps[Depth].FromId != 0xFF) {
CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, SwapPtr->Swaps[Depth].FromId, 0, 0);
if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
// Set the device's BUID field [20:16] to the current buid
CurrentBuid = SwapPtr->Swaps[Depth].ToId;
LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
Depth++;
} else {
// All non-coherent devices must have a slave interface capability.
ASSERT (FALSE);
break;
}
}
}
// Build chain of devices. Do this even if Recovery HT assign BUIDs for this chain.
Depth = 0;
while (SwapPtr->FinalIds[Depth] != 0xFF) {
ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
(*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
// Note: depth == 0 is true before depth > 0. This makes LastLink variable work.
if (Depth == 0) {
(*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
(*State->PortList)[(State->TotalLinks * 2)].Link = Link;
} else {
// Fill in the host side port. Link and base pointer can be deduced from the upstream link's
// downstream port.
(*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
(*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Link;
(*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
(*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
(*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[(((State->TotalLinks - 1) * 2) + 1)].Pointer;
}
(*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
(*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
(*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
(*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, (SwapPtr->FinalIds[Depth] & 0x3F), 0, 0);
if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
(*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
} else {
// All non-coherent devices must have a slave interface capability.
ASSERT (FALSE);
break;
}
// Bit 6 indicates whether orientation override is desired.
// Bit 7 indicates the upstream Link if overriding.
//
// assert catches at least the one known incorrect setting, that a non-zero link
// is specified, but override desired is not set.
ASSERT (((SwapPtr->FinalIds[Depth] & 0x40) != 0) || ((SwapPtr->FinalIds[Depth] & 0x80) == 0));
if ((SwapPtr->FinalIds[Depth] & 0x40) != 0) {
// Override the device's orientation
LastLink = SwapPtr->FinalIds[Depth] >> 7;
} else {
// Detect the device's orientation, by reading the Master Host bit [26]
LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
LastLink = (UINT8)Temp;
}
(*State->PortList)[(State->TotalLinks * 2) + 1].Link = LastLink;
Depth++;
State->TotalLinks++;
}
} else {
// Automatic non-coherent device detection
AGESA_TESTPOINT (TpProcHtAutoNc, State->ConfigHandle);
IDS_HDT_CONSOLE (HT_TRACE, "Auto IO chain init on node=%d, link=%d, secbus=%d, subbus=%d%s.\n",
Node, Link, SecBus, SubBus, (IsCompatChain ? ", Compat" : ""));
Depth = 0;
CurrentBuid = 1;
for (; ; ) {
CurrentPtr.AddressValue = MAKE_SBDFO (0, SecBus, 0, 0, 0);
LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
if (Temp == NO_DEVICE) {
if (IsCompatChain && State->IsUsingRecoveryHt) {
// See if the device is aleady at a non-zero BUID because HT Init Reset aleady assigned it.
CurrentPtr.Address.Device = CurrentBuid;
LibAmdPciRead (AccessWidth32, CurrentPtr, &Temp, State->ConfigHandle);
if (Temp == NO_DEVICE) {
// No more devices already assigned.
break;
}
} else {
// No more devices found.
break;
}
}
ASSERT (State->TotalLinks < MAX_PLATFORM_LINKS);
(*State->PortList)[(State->TotalLinks * 2)].NodeID = Node;
if (Depth == 0) {
(*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_CPU;
(*State->PortList)[(State->TotalLinks * 2)].Link = Link;
} else {
// Fill in the host side port. Link and base pointer can be deduced from the upstream link's
// downstream port.
(*State->PortList)[(State->TotalLinks * 2)].Type = PORTLIST_TYPE_IO;
(*State->PortList)[(State->TotalLinks * 2)].Link = 1 - (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Link;
(*State->PortList)[(State->TotalLinks * 2)].HostLink = Link;
(*State->PortList)[(State->TotalLinks * 2)].HostDepth = Depth - 1;
(*State->PortList)[(State->TotalLinks * 2)].Pointer = (*State->PortList)[((State->TotalLinks - 1) * 2) + 1].Pointer;
}
(*State->PortList)[(State->TotalLinks * 2) + 1].Type = PORTLIST_TYPE_IO;
(*State->PortList)[(State->TotalLinks * 2) + 1].NodeID = Node;
(*State->PortList)[(State->TotalLinks * 2) + 1].HostLink = Link;
(*State->PortList)[(State->TotalLinks * 2) + 1].HostDepth = Depth;
if (DoesDeviceHaveHtSubtypeCap (CurrentPtr, HT_SLAVE_CAPABILITY, &CurrentPtr, State)) {
// Get device's unit id count [25:21]
LibAmdPciReadBits (CurrentPtr, 25, 21, &UnitIdCount, State->ConfigHandle);
if (((UnitIdCount + CurrentBuid) > MAX_BUID) || ((SecBus == 0) && ((UnitIdCount + CurrentBuid) > 24))) {
// An error handler for the case where we run out of BUID's on a chain
NotifyErrorNcohBuidExceed (Node, Link, Depth, (UINT8)CurrentBuid, (UINT8)UnitIdCount, State);
IDS_ERROR_TRAP;
break;
}
// While we are still certain we are accessing this device, remember if it is a cave device.
// This is found by reading EOC from the Link 1 Control Register.
Link1ControlRegister = CurrentPtr;
Link1ControlRegister.Address.Register += (HTSLAVE_LINK01_OFFSET + HTSLAVE_LINK_CONTROL_0_REG);
LibAmdPciReadBits (Link1ControlRegister, 6, 6, &Temp, State->ConfigHandle);
IsCaveDevice = ((Temp == 0) ? FALSE : TRUE);
// Attempt to write the new BUID. Unless this chain was aleady assigned BUIDs during Init Reset,
// then just re-discover the chain. Note this may be true whether the device was found at
// BUID zero or not.
IDS_HDT_CONSOLE (HT_TRACE, "Found device at depth=%d, BUID=%d.\n", Depth, CurrentPtr.Address.Device);
if (!IsCompatChain || !State->IsUsingRecoveryHt) {
IDS_HDT_CONSOLE (HT_TRACE, "Assigning device to BUID=%d.\n", CurrentBuid);
LibAmdPciWriteBits (CurrentPtr, 20, 16, &CurrentBuid, State->ConfigHandle);
}
CurrentPtr.Address.Device = CurrentBuid;
LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
if (Temp != CurrentBuid) {
if ((Depth == 0) && IsCaveDevice) {
// If the chain only consists of a single cave device, that device may have retained zero
// for it's BUID.
CurrentPtr.Address.Device = 0;
LibAmdPciReadBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
if (Temp == 0) {
// Per HyperTransport specification, devices not accepting BUID reassignment hardwire BUID to zero.
(*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
(*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
State->TotalLinks++;
Depth++;
// Success!
IDS_HDT_CONSOLE (HT_TRACE, "%s Cave left at BUID=0.\n", ((!IsCompatChain || !State->IsUsingRecoveryHt) ? "Compatible" : "Already Assigned"));
break;
} else if (Temp == CurrentBuid) {
// and then, there are the other kind of devices ....
// Restore the writable BUID field (which contains the value we just wrote) to zero.
Temp = 0;
LibAmdPciWriteBits (CurrentPtr, 20, 16, &Temp, State->ConfigHandle);
(*State->PortList)[(State->TotalLinks * 2) + 1].Link = 0;
(*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
State->TotalLinks++;
Depth++;
// Success!
IDS_HDT_CONSOLE (HT_TRACE, "Cave left at BUID=0.\n");
break;
}
}
// An error handler for this error,
// this often occurs in new BIOS ports and it means you need to use a Manual BUID Swap List.
NotifyErrorNcohDeviceFailed (Node, Link, Depth, (UINT8)CurrentBuid, State);
IDS_ERROR_TRAP;
break;
}
LibAmdPciReadBits (CurrentPtr, 26, 26, &Temp, State->ConfigHandle);
(*State->PortList)[(State->TotalLinks * 2) + 1].Link = (UINT8)Temp;
(*State->PortList)[(State->TotalLinks * 2) + 1].Pointer = CurrentPtr;
IDS_HDT_CONSOLE (HT_TRACE, "Device assigned.\n");
Depth++;
State->TotalLinks++;
CurrentBuid += UnitIdCount;
} else {
// All non-coherent devices must have a slave interface capability.
ASSERT (FALSE);
break;
}
}
// Provide information on automatic device results
NotifyInfoNcohAutoDepth (Node, Link, (Depth - 1), State);
}
}

81
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatNoncoherent.h
View File

@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Non-Coherent Discovery Interface.
*
* Contains interface to the Non-Coherent Link processing feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_NONCOHERENT_H_
#define _HT_FEAT_NONCOHERENT_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Process a non-coherent Link.
*
*/
VOID
ProcessLink (
IN UINT8 Node,
IN UINT8 Link,
IN BOOLEAN IsCompatChain,
IN OUT STATE_DATA *State
);
#endif /* _HT_FEAT_NONCOHERENT_H_ */

886
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.c
View File

@ -1,886 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link Optimization Routines.
*
* Contains routines for determining width, frequency, and other
* Link features
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "IdsHt.h"
#include "htInterface.h"
#include "htNb.h"
#include "htFeatOptimization.h"
#include "htNotify.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATOPTIMIZATION_FILECODE
extern CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride;
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
#define PCI_CONFIG_COMMAND_REG04 4
#define PCI_CONFIG_REVISION_REG08 8
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Link Optimization ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Given the bits set in the register field, return the width it represents.
*
* As invalid width values or encodings are rare except during debug, catch those using
* ASSERT(). This means theoretically we are returning an incorrect result if that
* happens. The default chosen for the result is arbitrarily 8 bits. This is likely
* not to be the actual correct width and may cause a crash, hang, or incorrect operation.
* Hardware often ignores writes of invalid width encodings.
*
* @note This routine is used for CPUs as well as IO devices, as all comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Value The bits for the register
*
* @return The width
*/
UINT8
STATIC
ConvertBitsToWidth (
IN UINT8 Value
)
{
UINT8 Result;
Result = 0;
switch (Value) {
case 1:
Result = 16;
break;
case 0:
Result = 8;
break;
case 3:
Result = 32;
break;
case 5:
Result = 4;
break;
case 4:
Result = 2;
break;
default:
ASSERT (FALSE);
}
return Result;
}
/*----------------------------------------------------------------------------------------*/
/**
* Translate a desired width setting to the bits to set in the register field.
*
* As invalid width values or encodings are rare except during debug, catch those using
* ASSERT(). This means theoretically we are returning an incorrect result if that
* happens. The default chosen for the result is arbitrarily 8 bits. This is likely
* not to be the actual correct width and may cause a crash, hang, or incorrect operation.
* Hardware often ignores writes of invalid width encodings.
*
* @note This routine is used for CPUs as well as IO devices, as all comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Value the width Value
*
* @return The bits for the register
*/
UINT8
ConvertWidthToBits (
IN UINT8 Value
)
{
UINT8 Result;
Result = 8;
switch (Value) {
case 16:
Result = 1;
break;
case 8:
Result = 0;
break;
case 32:
Result = 3;
break;
case 4:
Result = 5;
break;
case 2:
Result = 4;
break;
default:
ASSERT (FALSE);
}
return Result;
}
/*----------------------------------------------------------------------------------------*/
/**
* Access HT Link Control Register.
*
* @HtFeatMethod{::F_SET_HT_CONTROL_REGISTER_BITS}
*
* Provide a common routine for accessing the HT Link Control registers (84, a4, c4,
* e4), to enforce not clearing the HT CRC error bits. Replaces direct use of
* AmdPCIWriteBits().
*
* @note: This routine is called for CPUs as well as IO Devices! All comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Reg the PCI config address the control register
* @param[in] HiBit the high bit number
* @param[in] LoBit the low bit number
* @param[in] Value the value to write to that bit range. Bit 0 => loBit.
* @param[in] State Our state, config handle for lib
*/
VOID
SetHtControlRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 HiBit,
IN UINT8 LoBit,
IN UINT32 *Value,
IN STATE_DATA *State
)
{
UINT32 Temp;
UINT32 mask;
ASSERT ((HiBit < 32) && (LoBit < 32) && (HiBit >= LoBit) && ((Reg.AddressValue & 0x3) == 0));
ASSERT ((HiBit < 8) || (LoBit > 9));
// A 1 << 32 == 1 << 0 due to x86 SHL instruction, so skip if that is the case
if ((HiBit - LoBit) != 31) {
mask = (((UINT32)1 << (HiBit - LoBit + 1)) - 1);
} else {
mask = (UINT32)0xFFFFFFFF;
}
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
Temp &= ~(mask << LoBit);
Temp |= (*Value & mask) << LoBit;
Temp &= (UINT32)HT_CONTROL_CLEAR_CRC;
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Set HT Frequency register for IO Devices
*
* Provide a common routine for accessing the HT Link Frequency registers at offset 8
* and 0x10, to enforce not clearing the HT Link error bits. Replaces direct use of
* AmdPCIWriteBits().
*
* @note This routine is called for IO Devices only!! All comply to the
* "HyperTransport I/O Link Specification ".
*
* @param[in] Reg the PCI config address the control register
* @param[in] Hibit the high bit number
* @param[in] Lobit the low bit number
* @param[in] Value the value to write to that bit range. Bit 0 => loBit.
* @param[in] State Our state, config handle for lib
*/
VOID
STATIC
SetHtIoFrequencyRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 Hibit,
IN UINT8 Lobit,
IN UINT32 *Value,
IN STATE_DATA *State
)
{
UINT32 Mask;
UINT32 Temp;
ASSERT ((Hibit < 32) && (Lobit < 32) && (Hibit >= Lobit) && ((Reg.AddressValue & 0x3) == 0));
ASSERT ((Hibit < 12) || (Lobit > 14));
// A 1<<32 == 1<<0 due to x86 SHL instruction, so skip if that is the case
if ((Hibit - Lobit) != 31) {
Mask = (((UINT32)1 << ((Hibit - Lobit) + 1)) - 1);
} else {
Mask = (UINT32)0xFFFFFFFF;
}
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
Temp &= ~(Mask << Lobit);
Temp |= (*Value & Mask) << Lobit;
Temp &= (UINT32)HT_FREQUENCY_CLEAR_LINK_ERRORS;
LibAmdPciWrite (AccessWidth32, Reg, &Temp, State->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Get Link features into system data structure.
*
* @HtFeatMethod{::F_GATHER_LINK_DATA}
*
* For all discovered Links, populate the port list with the frequency and width
* capabilities. Gather support data for:
* - Unit ID Clumping
*
* @param[in] State our global state, port list
*/
VOID
GatherLinkData (
IN STATE_DATA *State
)
{
UINT8 i;
PCI_ADDR LinkBase;
PCI_ADDR Reg;
UINT32 Bits;
UINT8 Revision;
// Get the capability base for whatever device type the link port is on
for (i = 0; i < (State->TotalLinks * 2); i++) {
if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
LinkBase = State->Nb->MakeLinkBase ((*State->PortList)[i].NodeID, (*State->PortList)[i].Link, State->Nb);
(*State->PortList)[i].Pointer = LinkBase;
} else {
LinkBase = (*State->PortList)[i].Pointer;
if ((*State->PortList)[i].Link == 1) {
LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
}
}
// Getting the Width is standard across device types
Reg = LinkBase;
Reg.Address.Register += HTSLAVE_LINK_CONTROL_0_REG;
LibAmdPciReadBits (Reg, 22, 20, &Bits, State->ConfigHandle);
(*State->PortList)[i].PrvWidthOutCap = ConvertBitsToWidth ((UINT8)Bits);
LibAmdPciReadBits (Reg, 18, 16, &Bits, State->ConfigHandle);
(*State->PortList)[i].PrvWidthInCap = ConvertBitsToWidth ((UINT8)Bits);
// Get Frequency and other device type specific features
if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
State->Nb->GatherLinkFeatures (&(*State->PortList)[i], State->HtInterface, State->PlatformConfiguration, State->Nb);
} else {
Reg = LinkBase;
Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
LibAmdPciReadBits (Reg, 31, 16, &Bits, State->ConfigHandle);
(*State->PortList)[i].PrvFrequencyCap = Bits;
// Unit ID Clumping Support
if (State->IsUsingUnitIdClumping) {
if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
Reg.Address.Register += HTUNIT_SUPPORT_REG;
LibAmdPciReadBits (Reg, 31, 0, &Bits, State->ConfigHandle);
} else {
// Not there, that's ok, we don't know that it should have one.
// Check for Passive support. (Bit 0 won't be set if full support is implemented,
// so we can use it to indicate passive support in our portlist struct).
Reg = LinkBase;
Reg.Address.Register += HTSLAVE_FEATURECAP_REG;
Bits = 1;
LibAmdPciWriteBits (Reg, 5, 5, &Bits, State->ConfigHandle);
LibAmdPciReadBits (Reg, 5, 5, &Bits, State->ConfigHandle);
}
(*State->PortList)[i].ClumpingSupport = Bits;
} else {
(*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
}
Reg = LinkBase;
Reg.Address.Register = PCI_CONFIG_REVISION_REG08;
LibAmdPciReadBits ( LinkBase, 7, 0, &Bits, State->ConfigHandle);
Revision = (UINT8) Bits;
LinkBase.Address.Register = 0;
LibAmdPciRead (AccessWidth32, LinkBase, &Bits, State->ConfigHandle);
State->HtInterface->GetDeviceCapOverride ((*State->PortList)[i].NodeID,
(*State->PortList)[i].HostLink,
(*State->PortList)[i].HostDepth,
(*State->PortList)[i].Pointer,
Bits,
Revision,
(*State->PortList)[i].Link,
&((*State->PortList)[i].PrvWidthInCap),
&((*State->PortList)[i].PrvWidthOutCap),
&((*State->PortList)[i].PrvFrequencyCap),
&((*State->PortList)[i].ClumpingSupport),
State);
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Optimize Links.
*
* @HtFeatMethod{::F_SELECT_OPTIMAL_WIDTH_AND_FREQUENCY}
*
* For all Links:
* Examine both sides of a Link and determine the optimal frequency and width,
* taking into account externally provided limits and enforcing any other limit
* or matching rules as applicable except subLink balancing. Update the port
* list data with the optimal settings.
*
* @note no hardware state changes in this routine.
*
* @param[in,out] State Process and update portlist
*/
VOID
SelectOptimalWidthAndFrequency (
IN OUT STATE_DATA *State
)
{
UINT8 i;
UINT8 j;
UINT8 Freq;
UINT32 Temp;
UINT32 CbPcbFreqLimit;
UINT8 CbPcbABDownstreamWidth;
UINT8 CbPcbBAUpstreamWidth;
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
CbPcbFreqLimit = HT_FREQUENCY_NO_LIMIT;
CbPcbABDownstreamWidth = HT_WIDTH_16_BITS;
CbPcbBAUpstreamWidth = HT_WIDTH_16_BITS;
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
State->HtInterface->GetCpu2CpuPcbLimits ((*State->PortList)[i].NodeID,
(*State->PortList)[i].Link,
(*State->PortList)[i + 1].NodeID,
(*State->PortList)[i + 1].Link,
&CbPcbABDownstreamWidth,
&CbPcbBAUpstreamWidth,
&CbPcbFreqLimit,
State
);
} else {
State->HtInterface->GetIoPcbLimits ((*State->PortList)[i + 1].NodeID,
(*State->PortList)[i + 1].HostLink,
(*State->PortList)[i + 1].HostDepth,
&CbPcbABDownstreamWidth,
&CbPcbBAUpstreamWidth,
&CbPcbFreqLimit,
State
);
}
Temp = (*State->PortList)[i].PrvFrequencyCap;
Temp &= (*State->PortList)[i + 1].PrvFrequencyCap;
Temp &= CbPcbFreqLimit;
(*State->PortList)[i].CompositeFrequencyCap = (UINT32)Temp;
(*State->PortList)[i + 1].CompositeFrequencyCap = (UINT32)Temp;
ASSERT (Temp != 0);
Freq = LibAmdBitScanReverse (Temp);
(*State->PortList)[i].SelFrequency = Freq;
(*State->PortList)[i + 1].SelFrequency = Freq;
Temp = (*State->PortList)[i].PrvWidthOutCap;
if ((*State->PortList)[i + 1].PrvWidthInCap < Temp) {
Temp = (*State->PortList)[i + 1].PrvWidthInCap;
}
if (CbPcbABDownstreamWidth < Temp) {
Temp = CbPcbABDownstreamWidth;
}
(*State->PortList)[i].SelWidthOut = (UINT8)Temp;
(*State->PortList)[i + 1].SelWidthIn = (UINT8)Temp;
Temp = (*State->PortList)[i].PrvWidthInCap;
if ((*State->PortList)[i + 1].PrvWidthOutCap < Temp) {
Temp = (*State->PortList)[i + 1].PrvWidthOutCap;
}
if (CbPcbBAUpstreamWidth < Temp) {
Temp = CbPcbBAUpstreamWidth;
}
(*State->PortList)[i].SelWidthIn = (UINT8)Temp;
(*State->PortList)[i + 1].SelWidthOut = (UINT8)Temp;
}
// Calculate unit id clumping
//
// Find the root of each IO Chain, process the chain for clumping support.
// The root is always the first link of the chain in the port list.
// Clumping is not device link specific, so we can just look at the upstream ports (j+1). Use ASSERTs to sanity
// check the downstream ports (j). If any device on the chain does not support clumping, the entire chain will be
// disabled for clumping.
// After analyzing the clumping support on the chain the CPU's portlist has the enable mask. Update all the
// IO Devices on the chain with the enable mask. If any device's only have passive support, that is already enabled.
//
if (State->IsUsingUnitIdClumping) {
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_IO)) {
(*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
(*State->PortList)[i].ClumpingSupport |= (*State->PortList)[i + 1].ClumpingSupport;
for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
ASSERT (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
((*State->PortList)[i].Link == (*State->PortList)[j].HostLink));
if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_DISABLE) {
ASSERT ((((*State->PortList)[j + 1].ClumpingSupport & HT_CLUMPING_PASSIVE) == 0) ||
(((*State->PortList)[j + 1].ClumpingSupport & ~(HT_CLUMPING_PASSIVE)) == 0));
(*State->PortList)[i].ClumpingSupport |= (*State->PortList)[j + 1].ClumpingSupport;
} else {
(*State->PortList)[i].ClumpingSupport = HT_CLUMPING_DISABLE;
break;
}
}
}
}
if ((*State->PortList)[i + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
(*State->PortList)[i + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
}
for (j = i + 2; j < (State->TotalLinks * 2); j += 2) {
if (((*State->PortList)[j].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[j + 1].Type == PORTLIST_TYPE_IO)) {
if (((*State->PortList)[i].NodeID == (*State->PortList)[j + 1].NodeID) &&
((*State->PortList)[i].Link == (*State->PortList)[j + 1].HostLink)) {
if ((*State->PortList)[j + 1].ClumpingSupport != HT_CLUMPING_PASSIVE) {
(*State->PortList)[j + 1].ClumpingSupport = (*State->PortList)[i].ClumpingSupport;
// The downstream isn't really passive, just mark it so in order to write the device only once.
(*State->PortList)[j].ClumpingSupport = HT_CLUMPING_PASSIVE;
}
}
}
}
}
}
}
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
*
* @HtFeatMethod{::F_SET_LINK_DATA}
*
* @param[in] State our global state, port list
*/
VOID
SetLinkData (
IN STATE_DATA *State
)
{
UINT8 i;
PCI_ADDR LinkBase;
PCI_ADDR Reg;
UINT32 Temp;
UINT32 Widthin;
UINT32 Widthout;
UINT32 Bits;
PCI_ADDR CurrentPtr;
HTIDS_PORT_OVERRIDE_LIST PortOverrides;
PortOverrides = NULL;
for (i = 0; i < (State->TotalLinks * 2); i++) {
ASSERT ((*State->PortList)[i & 0xFE].SelWidthOut == (*State->PortList)[ (i & 0xFE) + 1].SelWidthIn);
ASSERT ((*State->PortList)[i & 0xFE].SelWidthIn == (*State->PortList)[ (i & 0xFE) + 1].SelWidthOut);
ASSERT ((*State->PortList)[i & 0xFE].SelFrequency == (*State->PortList)[ (i & 0xFE) + 1].SelFrequency);
if ((*State->PortList)[i].SelRegang) {
ASSERT ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU);
ASSERT ((*State->PortList)[i].Link < 4);
State->Nb->SetLinkRegang (
(*State->PortList)[i].NodeID,
(*State->PortList)[i].Link,
State->Nb
);
}
//
// IDS port override for CPUs and IO Devices
//
pf_HtIdsGetPortOverride ((BOOLEAN) ((i & 1) == 0), &(*State->PortList)[i], &(*State->PortList)[i + 1], &PortOverrides, State);
LinkBase = (*State->PortList)[i].Pointer;
if (((*State->PortList)[i].Type == PORTLIST_TYPE_IO) && ((*State->PortList)[i].Link == 1)) {
LinkBase.Address.Register += HTSLAVE_LINK01_OFFSET;
}
// HT CRC Feature, set if configured. The default is not to set it, because with some chipsets it
// will lock up if done here.
if (State->IsSetHtCrcFlood) {
Temp = 1;
Reg = LinkBase;
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
State->HtFeatures->SetHtControlRegisterBits (Reg, 1, 1, &Temp, State);
if ((*State->PortList)[i].Type == PORTLIST_TYPE_IO) {
// IO Devices also need to have SERR enabled.
Reg = LinkBase;
Reg.Address.Register = PCI_CONFIG_COMMAND_REG04;
LibAmdPciWriteBits (Reg, 8, 8, &Temp, State->ConfigHandle);
}
}
// Some IO devices don't work properly when setting widths, so write them in a single operation,
// rather than individually.
//
Widthout = ConvertWidthToBits ((*State->PortList)[i].SelWidthOut);
ASSERT (Widthout == 1 || Widthout == 0 || Widthout == 5 || Widthout == 4);
Widthin = ConvertWidthToBits ((*State->PortList)[i].SelWidthIn);
ASSERT (Widthin == 1 || Widthin == 0 || Widthin == 5 || Widthin == 4);
Temp = (Widthin & 7) | ((Widthout & 7) << 4);
Reg = LinkBase;
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
State->HtFeatures->SetHtControlRegisterBits (Reg, 31, 24, &Temp, State);
Temp = (*State->PortList)[i].SelFrequency;
if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
State->Nb->SetLinkFrequency (
(*State->PortList)[i].NodeID,
(*State->PortList)[i].Link,
(UINT8)Temp,
State->Nb
);
} else {
ASSERT (Temp <= HT_FREQUENCY_2600M);
// Write the frequency setting
Reg = LinkBase;
Reg.Address.Register += HTSLAVE_FREQ_REV_0_REG;
SetHtIoFrequencyRegisterBits (Reg, 11, 8, &Temp, State);
// Handle additional HT3 frequency requirements, if needed,
// or clear them if switching down to ht1 on a warm reset.
// Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
//
// Even though we assert if debugging, we need to check that the capability was
// found always, since this is an unknown hardware device, also we are taking
// unqualified frequency from the external interface (could be trying to do ht3
// on an ht1 IO device).
//
if (Temp > HT_FREQUENCY_1000M) {
// Enabling features if gen 3
Bits = 1;
} else {
// Disabling features if gen 1
Bits = 0;
}
// Retry Enable
if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_RETRY_CAPABILITY, &CurrentPtr, State)) {
ASSERT ((*State->PortList)[i].Link < 2);
CurrentPtr.Address.Register += HTRETRY_CONTROL_REG;
LibAmdPciWriteBits (CurrentPtr,
((*State->PortList)[i].Link * 16),
((*State->PortList)[i].Link * 16),
&Bits,
State->ConfigHandle);
} else {
// If we are turning it off, that may mean the device was only ht1 capable,
// so don't complain that we can't do it.
//
if (Bits != 0) {
NotifyWarningOptRequiredCapRetry ((*State->PortList)[i].NodeID,
(*State->PortList)[i].HostLink,
(*State->PortList)[i].HostDepth,
State);
}
}
// Scrambling enable
if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_GEN3_CAPABILITY, &CurrentPtr, State)) {
ASSERT ((*State->PortList)[i].Link < 2);
CurrentPtr.Address.Register = CurrentPtr.Address.Register +
HTGEN3_LINK_TRAINING_0_REG +
((*State->PortList)[i].Link * HTGEN3_LINK01_OFFSET);
LibAmdPciWriteBits (CurrentPtr, 3, 3, &Bits, State->ConfigHandle);
} else {
// If we are turning it off, that may mean the device was only ht1 capable,
// so don't complain that we can't do it.
//
if (Bits != 0) {
NotifyWarningOptRequiredCapGen3 ((*State->PortList)[i].NodeID,
(*State->PortList)[i].HostLink,
(*State->PortList)[i].HostDepth,
State);
}
}
}
// Enable Unit ID Clumping if supported.
if (State->IsUsingUnitIdClumping) {
if (((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_PASSIVE) &&
((*State->PortList)[i].ClumpingSupport != HT_CLUMPING_DISABLE)) {
Bits = (*State->PortList)[i].ClumpingSupport;
if ((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) {
State->Nb->SetLinkUnitIdClumping (
(*State->PortList)[i].NodeID,
(*State->PortList)[i].Link,
(*State->PortList)[i].ClumpingSupport,
State->Nb
);
} else {
if (DoesDeviceHaveHtSubtypeCap (LinkBase, HT_UNITID_CAPABILITY, &Reg, State)) {
Reg.Address.Register += HTUNIT_ENABLE_REG;
LibAmdPciWriteBits (Reg, 31, 0, &Bits, State->ConfigHandle);
} else {
// If we found one when gathering support, we have to find one now.
ASSERT (FALSE);
}
}
}
}
}
}
/*------------------------------------------------------------------------------------------*/
/**
* Find a specific HT capability type.
*
* Search all the PCI Config space capabilities on any type of device for an
* HT capability of the specific subtype.
*
* @param[in] DevicePointer A PCI Config address somewhere in the device config space
* @param[in] CapSubType The HT capability subtype to find
* @param[out] CapabilityBase The Config space base address of the capability, if found.
* @param[in] State Our State
*
* @retval TRUE the capability was found
* @retval FALSE the capability was not found
*/
BOOLEAN
DoesDeviceHaveHtSubtypeCap (
IN PCI_ADDR DevicePointer,
IN UINT8 CapSubType,
OUT PCI_ADDR *CapabilityBase,
IN STATE_DATA *State
)
{
BOOLEAN IsFound;
BOOLEAN IsDone;
PCI_ADDR Reg;
UINT32 Temp;
UINT32 RegSubType;
UINT32 RegSubTypeMask;
// Set the PCI Config Space base and the match value.
IsFound = FALSE;
IsDone = FALSE;
Reg = DevicePointer;
Reg.Address.Register = 0;
if (CapSubType < (HT_HOST_CAPABILITY + 1)) {
// HT Interface sub type
RegSubType = ((UINT32) (CapSubType << 29) | (UINT32)8);
RegSubTypeMask = HT_INTERFACE_CAP_SUBTYPE_MASK;
} else {
// Other HT capability subtype
RegSubType = ((UINT32) (CapSubType << 27) | (UINT32)8);
RegSubTypeMask = HT_CAP_SUBTYPE_MASK;
}
(*CapabilityBase).AddressValue = (UINT32)ILLEGAL_SBDFO;
// Find it
do {
LibAmdPciFindNextCap (&Reg, State->ConfigHandle);
if (Reg.AddressValue != (UINT32)ILLEGAL_SBDFO) {
LibAmdPciRead (AccessWidth32, Reg, &Temp, State->ConfigHandle);
// HyperTransport and subtype capability ?
if ((Temp & RegSubTypeMask) == RegSubType) {
*CapabilityBase = Reg;
IsFound = TRUE;
}
// Some other capability, keep looking
} else {
// Not there
IsDone = TRUE;
}
} while (!IsFound && !IsDone);
return IsFound;
}
/*----------------------------------------------------------------------------------------*/
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
* @HtFeatMethod{::F_SET_LINK_DATA}
*
* Effectively, this means HT3 on some links cannot be mixed with HT1 on others.
* Scan the CPU to CPU links for this condition and limit those frequencies to HT1
* if it is detected.
* (Non-coherent links are independent.)
*
* @param[in,out] State global state, port frequency settings.
*
* @retval TRUE Fixup occurred, all coherent links HT1
* @retval FALSE No changes
*/
BOOLEAN
IsCoherentRetryFixup (
IN STATE_DATA *State
)
{
UINT8 Freq;
UINT8 i;
UINT8 DetectedFrequencyState;
BOOLEAN IsMixed;
UINT32 Temp;
//
// detectedFrequencyState:
// 0 - initial state
// 1 - HT1 Frequencies detected
// 2 - HT3 Frequencies detected
//
IsMixed = FALSE;
DetectedFrequencyState = 0;
// Scan coherent links for a mix of HT3 / HT1
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
// At this point, Frequency of port [i+1] must equal [i], so just check one of them.
switch (DetectedFrequencyState) {
case 0:
// Set current state to indicate what link frequency we found first
if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
// HT3 frequencies
DetectedFrequencyState = 2;
} else {
// HT1 frequencies
DetectedFrequencyState = 1;
}
break;
case 1:
// If HT1 frequency detected, fail any HT3 frequency
if ((*State->PortList)[i].SelFrequency > HT_FREQUENCY_1000M) {
IsMixed = TRUE;
}
break;
case 2:
// If HT3 frequency detected, fail any HT1 frequency
if ((*State->PortList)[i].SelFrequency <= HT_FREQUENCY_1000M) {
IsMixed = TRUE;
}
break;
default:
ASSERT (FALSE);
}
if (IsMixed) {
// Don't need to keep checking after we find a mix.
break;
}
}
}
if (IsMixed) {
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) && ((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
// Limit coherent links to HT 1 frequencies.
Temp = (*State->PortList)[i].CompositeFrequencyCap & (*State->PortList)[i + 1].CompositeFrequencyCap;
Temp &= HT_FREQUENCY_LIMIT_HT1_ONLY;
ASSERT (Temp != 0);
(*State->PortList)[i].CompositeFrequencyCap = Temp;
(*State->PortList)[i + 1].CompositeFrequencyCap = Temp;
Freq = LibAmdBitScanReverse (Temp);
(*State->PortList)[i].SelFrequency = Freq;
(*State->PortList)[i + 1].SelFrequency = Freq;
}
}
}
return (IsMixed);
}

140
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatOptimization.h
View File

@ -1,140 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link Optimization Feature.
*
* Contains interface for Link Optimization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_OPTIMIZATION_H_
#define _HT_FEAT_OPTIMIZATION_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Translate a desired width setting to the bits to set in the register field.
*/
UINT8
ConvertWidthToBits (
IN UINT8 Value
);
/**
* Access HT Link Control Register.
*
*/
VOID
SetHtControlRegisterBits (
IN PCI_ADDR Reg,
IN UINT8 HiBit,
IN UINT8 LoBit,
IN UINT32 *Value,
IN STATE_DATA *State
);
/**
* Get Link features into system data structure.
*
*/
VOID
GatherLinkData (
IN STATE_DATA *State
);
/**
* Optimize Links.
*
*/
VOID
SelectOptimalWidthAndFrequency (
IN OUT STATE_DATA *State
);
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
*
*/
VOID
SetLinkData (
IN STATE_DATA *State
);
/**
* Retry must be enabled on all coherent links if it is enabled on any coherent links.
*
*/
BOOLEAN
IsCoherentRetryFixup (
IN STATE_DATA *State
);
/**
* Find a specific HT capability type.
*
* @retval FALSE the capability was not found
*/
BOOLEAN
DoesDeviceHaveHtSubtypeCap (
IN PCI_ADDR DevicePointer,
IN UINT8 CapSubType,
OUT PCI_ADDR *CapabilityBase,
IN STATE_DATA *State
);
#endif /* _HT_FEAT_OPTIMIZATION_H_ */

493
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatRouting.c
View File

@ -1,493 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Routing Routines
*
* Contains routines for isomorphic topology matching,
* routing determination, and routing initialization.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNotify.h"
#include "htNb.h"
#include "htGraph.h"
#include "htFeatRouting.h"
#include "htTopologies.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATROUTING_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
typedef struct {
UINT8 **CurrentPosition;
BOOLEAN IsCustomList;
} TOPOLOGY_CONTEXT;
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** ISOMORPHISM BASED ROUTING TABLE GENERATION CODE ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Return the Link on source Node which connects to target Node
*
* @param[in] SourceNode The Node on which to find the Link
* @param[in] TargetNode The Link will connect to this Node
* @param[in] State Our global state
*
* @return the Link to target
*/
UINT8
STATIC
FindLinkToNode (
IN UINT8 SourceNode,
IN UINT8 TargetNode,
IN STATE_DATA *State
)
{
UINT8 TargetLink;
UINT8 k;
// A node linked to itself is not a supported topology graph, this is probably an error in the
// topology data. There is not going to be a portlist match for it.
ASSERT (SourceNode != TargetNode);
TargetLink = INVALID_LINK;
for (k = 0; k < State->TotalLinks*2; k += 2) {
if (((*State->PortList)[k].NodeID == SourceNode) && ((*State->PortList)[k + 1].NodeID == TargetNode)) {
TargetLink = (*State->PortList)[k].Link;
break;
} else if (((*State->PortList)[k + 1].NodeID == SourceNode) && ((*State->PortList)[k].NodeID == TargetNode)) {
TargetLink = (*State->PortList)[k + 1].Link;
break;
}
}
ASSERT (TargetLink != INVALID_LINK);
return TargetLink;
}
/*----------------------------------------------------------------------------------------*/
/**
* Is graphA isomorphic to graphB?
*
* If this function returns true, then Perm will contain the permutation
* required to transform graphB into graphA.
* We also use the degree of each Node, that is the number of connections it has, to
* speed up rejection of non-isomorphic graphs (if there is a Node in graphA with n
* connections, there must be at least one unmatched in graphB with n connections).
*
* @param[in] Node the discovered Node which we are trying to match
* with a permutation the topology
* @param[in,out] State our global state, degree and adjacency matrix,
* output a permutation if successful
* @retval TRUE the graphs are isomorphic
* @retval FALSE the graphs are not isomorphic
*
*/
BOOLEAN
STATIC
IsIsomorphic (
IN UINT8 Node,
IN OUT STATE_DATA *State
)
{
UINT8 j;
UINT8 k;
UINT8 Nodecnt;
// We have only been called if Nodecnt == pSelected->size !
Nodecnt = State->NodesDiscovered + 1;
if (Node != Nodecnt) {
// Keep building the permutation
for (j = 0; j < Nodecnt; j++) {
// Make sure the degree matches
if (State->Fabric->SysDegree[Node] != State->Fabric->DbDegree[j]) {
continue;
}
// Make sure that j hasn't been used yet (ought to use a "used"
// array instead, might be faster)
for (k = 0; k < Node; k++) {
if (State->Fabric->Perm[k] == j) {
break;
}
}
if (k != Node) {
continue;
}
State->Fabric->Perm[Node] = j;
if (IsIsomorphic (Node + 1, State)) {
return TRUE;
}
}
return FALSE;
} else {
// Test to see if the permutation is isomorphic
for (j = 0; j < Nodecnt; j++) {
for (k = 0; k < Nodecnt; k++) {
if (State->Fabric->SysMatrix[j][k] != State->Fabric->DbMatrix[State->Fabric->Perm[j]][State->Fabric->Perm[k]] ) {
return FALSE;
}
}
}
return TRUE;
}
}
/*----------------------------------------------------------------------------------------*/
/**
* Set Topology List iterator context to the Beginning and provide the first topology.
*
* Check the interface for a custom topology list. If one is found, set context to the
* first item, and return that item. Otherwise return the first item in the built in list.
*
* @param[in,out] TopologyContextHandle Initialize this context to beginning of lists.
* @param[out] NextTopology The next topology, NULL if end.
* @param[in] State Access to interface, handles.
*
*/
VOID
STATIC
BeginTopologies (
OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
OUT UINT8 **NextTopology,
IN STATE_DATA *State
)
{
if (State->HtBlock->Topolist != NULL) {
// Start with a custom list
TopologyContextHandle->CurrentPosition = State->HtBlock->Topolist;
TopologyContextHandle->IsCustomList = TRUE;
} else {
// Start with the built in list
GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
TopologyContextHandle->IsCustomList = FALSE;
}
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
/*----------------------------------------------------------------------------------------*/
/**
* Iterate through available topologies.
*
* Increment to the next list item. If we are doing a custom list, when we reach the end
* switch to the built in list.
*
* @param[in,out] TopologyContextHandle Maintain iterator's context from one call to the next
* @param[out] NextTopology The next topology, NULL if end.
*
*/
VOID
STATIC
GetNextTopology (
IN OUT TOPOLOGY_CONTEXT *TopologyContextHandle,
OUT UINT8 **NextTopology
)
{
// Not valid to continue calling this routine after reaching the end.
ASSERT (TopologyContextHandle->CurrentPosition != NULL);
if (TopologyContextHandle->IsCustomList) {
// We are iterating the custom list from the interface.
TopologyContextHandle->CurrentPosition++;
if (*TopologyContextHandle->CurrentPosition == NULL) {
// We are at the end of the custom list, switch to the built in list.
TopologyContextHandle->IsCustomList = FALSE;
GetAmdTopolist (&TopologyContextHandle->CurrentPosition);
}
} else {
// We are iterating the built in list
TopologyContextHandle->CurrentPosition++;
// If we are at the end of the built in list, NextTopology == NULL is the AtEnd.
}
*NextTopology = *TopologyContextHandle->CurrentPosition;
}
/*----------------------------------------------------------------------------------------*/
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
*
* @HtFeatMethod{::F_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES}
*
* A supported topology description matches the discovered fabric if the Nodes can be
* matched in such a way that all the Nodes connected in one set are exactly the
* Nodes connected in the other (formally, that the graphs are isomorphic). Which
* Links are used is not really important to matching. If the graphs match, then
* there is a permutation of one that translates the Node positions and Linkages to
* the other.
*
* In order to make the isomorphism test efficient, we test for matched number of Nodes
* (a 4 Node fabric is not isomorphic to a 2 Node topology), and provide degrees of Nodes
* to the isomorphism test.
*
* The generic routing table solution for any topology is predetermined and represented
* as part of the topology. The permutation we computed tells us how to interpret the
* routing onto the fabric we discovered. We do this working backward from the last
* Node discovered to the BSP, writing the routing tables as we go.
*
* @param[in,out] State the discovered fabric, degree matrix, permutation
*
*/
VOID
LookupComputeAndLoadRoutingTables (
IN OUT STATE_DATA *State
)
{
TOPOLOGY_CONTEXT TopologyContextHandle;
UINT8 *Selected;
UINT8 Size;
UINT8 PairCounter;
UINT8 ReqTargetLink;
UINT8 RspTargetLink;
UINT8 ReqTargetNode;
UINT8 RspTargetNode;
UINT8 AbstractBcTargetNodes;
UINT32 BcTargetLinks;
UINT8 NodeCounter;
UINT8 NodeBeingRouted;
UINT8 NodeRoutedTo;
UINT8 BroadcastSourceNode;
Size = State->NodesDiscovered + 1;
BeginTopologies (&TopologyContextHandle, &Selected, State);
while (Selected != NULL) {
if (GraphHowManyNodes (Selected) == Size) {
// Build Degree vector and Adjacency Matrix for this entry
for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
State->Fabric->DbDegree[NodeCounter] = 0;
for (PairCounter = 0; PairCounter < Size; PairCounter++) {
if (GraphIsAdjacent (Selected, NodeCounter, PairCounter)) {
State->Fabric->DbMatrix[NodeCounter][PairCounter] = TRUE;
State->Fabric->DbDegree[NodeCounter]++;
} else {
State->Fabric->DbMatrix[NodeCounter][PairCounter] = FALSE;
}
}
}
if (IsIsomorphic (0, State)) {
break; // A matching topology was found
}
}
GetNextTopology (&TopologyContextHandle, &Selected);
}
if (Selected != NULL) {
// Compute the reverse Permutation
for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
State->Fabric->ReversePerm[State->Fabric->Perm[NodeCounter]] = NodeCounter;
}
// Start with the last discovered Node, and move towards the BSP
for (NodeCounter = 0; NodeCounter < Size; NodeCounter++) {
NodeBeingRouted = ((Size - 1) - NodeCounter);
for (NodeRoutedTo = 0; NodeRoutedTo < Size; NodeRoutedTo++) {
BcTargetLinks = 0;
AbstractBcTargetNodes = GraphGetBc (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
for (BroadcastSourceNode = 0; BroadcastSourceNode < MAX_NODES; BroadcastSourceNode++) {
if ((AbstractBcTargetNodes & ((UINT32)1 << BroadcastSourceNode)) != 0) {
// Accepting broadcast from yourself is handled in Nb, so in the topology graph it is an error.
ASSERT (NodeBeingRouted != State->Fabric->ReversePerm[BroadcastSourceNode]);
BcTargetLinks |= (UINT32)1 << FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[BroadcastSourceNode], State);
}
}
if (NodeBeingRouted == NodeRoutedTo) {
ReqTargetLink = ROUTE_TO_SELF;
RspTargetLink = ROUTE_TO_SELF;
} else {
ReqTargetNode = GraphGetReq (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
ReqTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[ReqTargetNode], State);
RspTargetNode = GraphGetRsp (Selected, State->Fabric->Perm[NodeBeingRouted], State->Fabric->Perm[NodeRoutedTo]);
RspTargetLink = FindLinkToNode (NodeBeingRouted, State->Fabric->ReversePerm[RspTargetNode], State);
}
State->Nb->WriteFullRoutingTable (NodeBeingRouted, NodeRoutedTo, ReqTargetLink, RspTargetLink, BcTargetLinks, State->Nb);
}
// Clean up discovery 'footprint' that otherwise remains in the routing table. It didn't hurt
// anything, but might cause confusion during debug and validation. Do this by setting the
// route back to all self routes. Since it's the Node that would be one more than actually installed,
// this only applies if less than MaxNodes were found.
//
if (Size < MAX_NODES) {
State->Nb->WriteFullRoutingTable (NodeBeingRouted, Size, ROUTE_TO_SELF, ROUTE_TO_SELF, 0, State->Nb);
}
}
} else {
//
// No Matching Topology was found
// Error Strategy:
// Auto recovery doesn't seem likely, Force boot as 1P.
// For reporting, logging, provide number of Nodes
// If not implemented or returns, boot as BSP uniprocessor.
//
// This can be caused by not supplying an additional topology list, if your board is not one of the built-in topologies.
//
NotifyErrorCohNoTopology (State->NodesDiscovered, State);
IDS_ERROR_TRAP;
// Force 1P
State->NodesDiscovered = 0;
State->TotalLinks = 0;
State->Nb->EnableRoutingTables (0, State->Nb);
State->HtInterface->CleanMapsAfterError (State);
}
// Save the topology pointer, or NULL, for other features
State->Fabric->MatchedTopology = Selected;
IDS_HDT_CONSOLE (
HT_TRACE,
"System routed as %s.\n",
((TopologyContextHandle.IsCustomList) ?
"custom topology" :
(((Selected == amdHtTopologySingleNode) || (Selected == NULL)) ?
"single node" :
((Selected == amdHtTopologyDualNode) ?
"dual node" :
((Selected == amdHtTopologyFourSquare) ?
"four node box" :
((Selected == amdHtTopologyFourKite) ?
"four node kite" :
((Selected == amdHtTopologyFourFully) ?
"fully connected four-way" :
((Selected == amdHtTopologyEightDoubloon) ?
"MCM max performance" :
((Selected == amdHtTopologyEightTwinFullyFourWays) ?
"MCM max I/O" :
"AMD builtin topology"))))))))
);
}
/*----------------------------------------------------------------------------------------*/
/**
* Make a Hop Count Table for the installed topology.
*
* @HtFeatMethod{::F_MAKE_HOP_COUNT_TABLE}
*
* For SLIT, create a node x node matrix with the number of hops. We can do this
* using the topology and the permutation, counting the nodes visited in the routes between
* nodes.
*
* @param[in,out] State access topology, permutation, update hop table
*
*/
VOID
MakeHopCountTable (
IN OUT STATE_DATA *State
)
{
UINT8 Origin;
UINT8 Target;
UINT8 Current;
UINT8 Hops;
UINT8 Size;
ASSERT (State->Fabric != NULL);
if (State->HopCountTable != NULL) {
if (State->Fabric->MatchedTopology != NULL) {
Size = GraphHowManyNodes (State->Fabric->MatchedTopology);
State->HopCountTable->Size = Size;
//
// For each node, targeting each node, follow the request path through the database graph,
// counting the number of edges.
//
for (Origin = 0; Origin < Size; Origin++) {
for (Target = 0; Target < Size; Target++) {
// If both nodes are the same the answer will be zero
Hops = 0;
// Current starts as the database node corresponding to system node Origin.
Current = State->Fabric->Perm[Origin];
// Stop if Current is the database node corresponding to system node Target
while (Current != State->Fabric->Perm[Target]) {
// This is a hop, so count it. Move Current to the next intermediate database node.
Hops++;
Current = GraphGetReq (State->Fabric->MatchedTopology, Current, State->Fabric->Perm[Target]);
}
// Put the hop count in the table.
State->HopCountTable->Hops[ ((Origin * Size) + Target)] = Hops;
}
}
}
}
}

90
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@ -1,90 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Routing Feature Interface.
*
* Interfaces to routing and isomorphism routines.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_ROUTING_H_
#define _HT_FEAT_ROUTING_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Using the description of the fabric topology we discovered, try to find a match
* among the supported topologies.
*
*/
VOID
LookupComputeAndLoadRoutingTables (
IN OUT STATE_DATA *State
);
/**
* Make a Hop Count Table for the installed topology.
*
*/
VOID
MakeHopCountTable (
IN OUT STATE_DATA *State
);
#endif /* _HT_FEAT_ROUTING_H_ */

114
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@ -1,114 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* HyperTransport feature sets initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "OptionsHt.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "CommonReturns.h"
#include "htFeatDynamicDiscovery.h"
#include "htFeatRouting.h"
#include "htFeatNoncoherent.h"
#include "htFeatOptimization.h"
#include "htFeatGanging.h"
#include "htFeatSublinks.h"
#include "htFeatTrafficDistribution.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATSETS_FILECODE
extern CONST OPTION_HT_CONFIGURATION OptionHtConfiguration;
/**
* Initializer for the default feature set implementation,
* full features.
*/
CONST HT_FEATURES ROMDATA HtFeaturesDefault =
{
CoherentDiscovery,
LookupComputeAndLoadRoutingTables,
MakeHopCountTable,
ProcessLink,
GatherLinkData,
SelectOptimalWidthAndFrequency,
RegangLinks,
SubLinkRatioFixup,
IsCoherentRetryFixup,
SetLinkData,
TrafficDistribution,
SetHtControlRegisterBits,
ConvertWidthToBits
};
/**
* Initializer for the non-coherent only build option.
*/
CONST HT_FEATURES ROMDATA HtFeaturesNonCoherentOnly =
{
(PF_COHERENT_DISCOVERY)CommonVoid,
(PF_LOOKUP_COMPUTE_AND_LOAD_ROUTING_TABLES)CommonVoid,
(PF_MAKE_HOP_COUNT_TABLE)CommonVoid,
ProcessLink,
GatherLinkData,
SelectOptimalWidthAndFrequency,
(PF_REGANG_LINKS)CommonVoid,
(PF_SUBLINK_RATIO_FIXUP)CommonVoid,
(PF_IS_COHERENT_RETRY_FIXUP)CommonReturnFalse,
SetLinkData,
(PF_TRAFFIC_DISTRIBUTION)CommonVoid,
SetHtControlRegisterBits,
ConvertWidthToBits
};

232
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.c
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@ -1,232 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* SubLink management Routines.
*
* Contains routines for subLink frequency ratios.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "amdlib.h"
#include "Topology.h"
#include "htFeat.h"
#include "IdsHt.h"
#include "htFeatSublinks.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATSUBLINKS_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
typedef struct {
UINT8 HiFreq;
UINT8 LoFreq;
} VALID_RATIO_ITEM;
STATIC CONST VALID_RATIO_ITEM ROMDATA ValidRatioList[] =
{
{HT_FREQUENCY_3200M, HT_FREQUENCY_1600M}, // 3200MHz / 1600MHz 2:1
{HT_FREQUENCY_3200M, HT_FREQUENCY_800M}, // 3200MHz / 800MHz 4:1
{HT_FREQUENCY_3200M, HT_FREQUENCY_400M}, // 3200MHz / 400MHz 8:1
{HT_FREQUENCY_2800M, HT_FREQUENCY_1400M}, // 2800MHz / 1400MHz 2:1
{HT_FREQUENCY_2400M, HT_FREQUENCY_1200M}, // 2400MHz / 1200MHz 2:1
{HT_FREQUENCY_2400M, HT_FREQUENCY_600M}, // 2400MHz / 600MHz 4:1
{HT_FREQUENCY_2400M, HT_FREQUENCY_400M}, // 2400MHz / 400MHz 6:1
{HT_FREQUENCY_2000M, HT_FREQUENCY_1000M}, // 2000MHz / 1000MHz 2:1
{HT_FREQUENCY_1600M, HT_FREQUENCY_800M}, // 1600MHz / 800MHz 2:1
{HT_FREQUENCY_1600M, HT_FREQUENCY_400M}, // 1600MHz / 400MHz 4:1
{HT_FREQUENCY_1600M, HT_FREQUENCY_200M}, // 1600MHz / 200Mhz 8:1
{HT_FREQUENCY_1200M, HT_FREQUENCY_600M}, // 1200MHz / 600MHz 2:1
{HT_FREQUENCY_1200M, HT_FREQUENCY_200M}, // 1200MHz / 200MHz 6:1
{HT_FREQUENCY_800M, HT_FREQUENCY_400M}, // 800MHz / 400MHz 2:1
{HT_FREQUENCY_800M, HT_FREQUENCY_200M}, // 800MHz / 200MHz 4:1
{HT_FREQUENCY_400M, HT_FREQUENCY_200M} // 400MHz / 200MHz 2:1
};
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Link Optimization ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
* @HtFeatMethod{::F_SUBLINK_RATIO_FIXUP}
*
* Make the adjustment to the port list data so that the frequencies
* are at a valid ratio, reducing frequency as needed to achieve
* this. (All Links support the minimum 200 MHz frequency.) Repeat
* the above until no adjustments are needed.
* @note no hardware state changes in this routine.
*
* @param[in,out] State Link state and port list
*
*/
VOID
SubLinkRatioFixup (
IN OUT STATE_DATA *State
)
{
UINT8 i;
UINT8 j;
UINT8 ValidRatioItem;
BOOLEAN Changes;
BOOLEAN Downgrade;
UINT8 HiIndex;
UINT8 HiFreq;
UINT8 LoFreq;
UINT32 Temp;
do {
Changes = FALSE;
for (i = 0; i < State->TotalLinks*2; i++) {
// Must be a CPU Link
if ((*State->PortList)[i].Type != PORTLIST_TYPE_CPU) {
continue;
}
// Only look for subLink1's
if ((*State->PortList)[i].Link < 4) {
continue;
}
for (j = 0; j < State->TotalLinks*2; j++) {
// Step 1. Find the matching subLink0
if ((*State->PortList)[j].Type != PORTLIST_TYPE_CPU) {
continue;
}
if ((*State->PortList)[j].NodeID != (*State->PortList)[i].NodeID) {
continue;
}
if ((*State->PortList)[j].Link != ((*State->PortList)[i].Link & 0x03)) {
continue;
}
// Step 2. Check for an illegal frequency ratio
if ((*State->PortList)[i].SelFrequency >= (*State->PortList)[j].SelFrequency) {
HiIndex = i;
HiFreq = (*State->PortList)[i].SelFrequency;
LoFreq = (*State->PortList)[j].SelFrequency;
} else {
HiIndex = j;
HiFreq = (*State->PortList)[j].SelFrequency;
LoFreq = (*State->PortList)[i].SelFrequency;
}
// The frequencies are 1:1, no need to do anything
if (HiFreq == LoFreq) {
break;
}
Downgrade = TRUE;
for (ValidRatioItem = 0; ValidRatioItem < (sizeof (ValidRatioList) / sizeof (VALID_RATIO_ITEM)); ValidRatioItem++) {
if ((HiFreq == ValidRatioList[ValidRatioItem].HiFreq) &&
(LoFreq == ValidRatioList[ValidRatioItem].LoFreq)) {
Downgrade = FALSE;
break;
}
}
// Step 3. Downgrade the higher of the two frequencies, and set Changes to FALSE
if (Downgrade) {
// Although the problem was with the port specified by hiIndex, we need to
// Downgrade both ends of the Link.
HiIndex = HiIndex & 0xFE; // Select the 'upstream' (i.e. even) port
Temp = (*State->PortList)[HiIndex].CompositeFrequencyCap;
// Remove HiFreq from the list of valid frequencies
Temp = Temp & ~((UINT32)1 << HiFreq);
ASSERT (Temp != 0);
(*State->PortList)[HiIndex].CompositeFrequencyCap = (UINT32)Temp;
(*State->PortList)[HiIndex + 1].CompositeFrequencyCap = (UINT32)Temp;
HiFreq = LibAmdBitScanReverse (Temp);
(*State->PortList)[HiIndex].SelFrequency = HiFreq;
(*State->PortList)[HiIndex + 1].SelFrequency = HiFreq;
Changes = TRUE;
}
}
}
} while (Changes); // Repeat until a valid configuration is reached
}

80
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatSublinks.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* SubLink Interface.
*
* Contains interface to subLink management feature, for unganged subLinks.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_SUBLINKS_H_
#define _HT_FEAT_SUBLINKS_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Iterate through all Links, checking the frequency of each subLink pair.
*
*/
VOID
SubLinkRatioFixup (
IN OUT STATE_DATA *State
);
#endif /* _HT_FEAT_SUBLINKS_H_ */

278
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.c
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@ -1,278 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Traffic Distribution Routines.
*
* Contains routines for traffic distribution
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35978 $ @e \$Date: 2010-08-07 02:18:50 +0800 (Sat, 07 Aug 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htNotify.h"
#include "htFeatTrafficDistribution.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTFEATTRAFFICDISTRIBUTION_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Identify Links which can have traffic distribution.
*
* @HtFeatMethod{::F_TRAFFIC_DISTRIBUTION}
*
* If there are redundant links between any nodes, traffic distribution allows the
* redundant links to be used to improve performance.
*
* There are two types of traffic distribution. Their use is mutually exclusive, both
* can not be used at once.
*
* Coherent Traffic Distribution is for systems of exactly two nodes only. All links must
* be symmetrical (the same width). As many links as are connected can be distributed over.
*
* Link Pair Traffic Distribution works with redundant pairs of links between any two nodes,
* it does not matter how many nodes are in the system or how many have a redundant link pair.
* A node can have redundant link pairs with more than one other node.
* The link pair can be asymmetric, the largest link must be used as the master. However,
* between any pair of nodes there is only one pair of redundant links, and there is a limit
* to the total number of pairs each node can have. So not all links will necessarily be
* made usable.
*
* @param[in] State port list data
*/
VOID
TrafficDistribution (
IN STATE_DATA *State
)
{
UINT32 Links01;
UINT32 Links10;
UINT8 LinkCount;
UINT8 i;
UINT8 LastLink;
BOOLEAN IsAsymmetric;
UINT8 RedundantLinkCount[MAX_NODES][MAX_NODES];
UINT8 MasterLinkPort[MAX_NODES][MAX_NODES];
UINT8 AlternateLinkPort[MAX_NODES][MAX_NODES];
UINT8 NodeA;
UINT8 NodeB;
UINT8 PairCount;
LastLink = 0xFF;
IsAsymmetric = FALSE;
// Traffic Distribution is only used when there are exactly two Nodes in the system
// and when all the links are symmetric, same width.
if ((State->NodesDiscovered + 1) == 2) {
Links01 = 0;
Links10 = 0;
LinkCount = 0;
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
if ((LastLink != 0xFF) &&
((*State->PortList)[i].SelWidthOut != (*State->PortList)[LastLink].SelWidthOut) &&
((*State->PortList)[i + 1].SelWidthOut != (*State->PortList)[LastLink + 1].SelWidthOut)) {
IsAsymmetric = TRUE;
break;
}
Links01 |= (UINT32)1 << (*State->PortList)[i].Link;
Links10 |= (UINT32)1 << (*State->PortList)[i + 1].Link;
LinkCount++;
LastLink = i;
}
}
ASSERT (LinkCount != 0);
// Don't setup Traffic Distribution if only one Link is being used or there were asymmetric widths
if ((LinkCount != 1) && !IsAsymmetric) {
IDS_HDT_CONSOLE (HT_TRACE, "Applying coherent traffic distribution.\n");
State->Nb->WriteTrafficDistribution (Links01, Links10, State->Nb);
// If we did Traffic Distribution, we must not do Link Pair, so get out of here.
return;
}
}
// Either there are more than two nodes, Asymmetric links, or no redundant links.
// See if we can use Link Pair Traffic Distribution
LibAmdMemFill (&RedundantLinkCount, 0, (MAX_NODES * MAX_NODES), State->ConfigHandle);
for (i = 0; i < (State->TotalLinks * 2); i += 2) {
if (((*State->PortList)[i].Type == PORTLIST_TYPE_CPU) &&
((*State->PortList)[i + 1].Type == PORTLIST_TYPE_CPU)) {
NodeA = (*State->PortList)[i].NodeID;
NodeB = (*State->PortList)[i + 1].NodeID;
if (RedundantLinkCount[NodeA][NodeB] == 0) {
// This is the first link connecting two nodes
ASSERT (RedundantLinkCount[NodeB][NodeA] == 0);
MasterLinkPort[NodeA][NodeB] = i;
MasterLinkPort[NodeB][NodeA] = i + 1;
} else {
// This is a redundant link. If it is larger than the current master link,
// make it the new master link.
//
if (((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
((*State->PortList)[MasterLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
// Make the old master link the alternate, we don't need to check, it is bigger.
AlternateLinkPort[NodeA][NodeB] = MasterLinkPort[NodeA][NodeB];
AlternateLinkPort[NodeB][NodeA] = MasterLinkPort[NodeB][NodeA];
MasterLinkPort[NodeA][NodeB] = i;
MasterLinkPort[NodeB][NodeA] = i + 1;
} else {
// Since the new link isn't bigger than the Master, check if it is bigger than the alternate,
// if we have an alternate. If we don't have an alternate yet, make this link the alternate.
if (RedundantLinkCount[NodeA][NodeB] == 1) {
AlternateLinkPort[NodeA][NodeB] = i;
AlternateLinkPort[NodeB][NodeA] = i + 1;
} else {
if (((*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut < (*State->PortList)[i].SelWidthOut) &&
((*State->PortList)[AlternateLinkPort[NodeB][NodeA]].SelWidthOut < (*State->PortList)[i + 1].SelWidthOut)) {
// Warning: the alternate link is an unusable redundant link
// Then make the new link the alternate link.
NotifyWarningOptUnusedLinks (
NodeA,
(*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
NodeB,
(*State->PortList)[AlternateLinkPort[NodeB][NodeA]].Link,
State
);
ASSERT (RedundantLinkCount[NodeB][NodeA] > 1);
AlternateLinkPort[NodeA][NodeB] = i;
AlternateLinkPort[NodeB][NodeA] = i + 1;
} else {
// Warning the current link is an unusable redundant link
NotifyWarningOptUnusedLinks (NodeA, (*State->PortList)[i].Link, NodeB, (*State->PortList)[i].Link, State);
}
}
}
}
RedundantLinkCount[NodeA][NodeB]++;
RedundantLinkCount[NodeB][NodeA]++;
}
}
// If we found any, now apply up to 4 per node
for (NodeA = 0; NodeA < MAX_NODES; NodeA++) {
PairCount = 0;
for (NodeB = 0; NodeB < MAX_NODES; NodeB++) {
if (RedundantLinkCount[NodeA][NodeB] > 1) {
// Then there is a pair of links (at least, but we only care about the pair not the extras)
if (PairCount < MAX_LINK_PAIRS) {
// Program it
if ((*State->PortList)[MasterLinkPort[NodeA][NodeB]].SelWidthOut
!= (*State->PortList)[AlternateLinkPort[NodeA][NodeB]].SelWidthOut) {
IsAsymmetric = TRUE;
} else {
IsAsymmetric = FALSE;
}
State->Nb->WriteLinkPairDistribution (
NodeA,
NodeB,
PairCount,
IsAsymmetric,
(*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
(*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
State->Nb
);
PairCount++;
} else {
// Warning: More link pairs than can be distributed
NotifyWarningOptLinkPairExceed (
NodeA, NodeB,
(*State->PortList)[MasterLinkPort[NodeA][NodeB]].Link,
(*State->PortList)[AlternateLinkPort[NodeA][NodeB]].Link,
State);
// Disable the link pair from the other node, the analysis loop made sure there
// can only be a single link pair between a pair of nodes.
RedundantLinkCount[NodeB][NodeA] = 1;
}
}
}
IDS_HDT_CONSOLE (
HT_TRACE,
((PairCount != 0) ?
"Node %d applying %d link pair distributions.\n" :
""),
NodeA,
PairCount
);
}
}

77
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htFeatTrafficDistribution.h
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Traffic Distribution Interface.
*
* Interface to traffic distribution feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
#define _HT_FEAT_TRAFFIC_DISTRIBUTION_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* Identify Links which can have traffic distribution.
*
*/
VOID
TrafficDistribution (
IN STATE_DATA *State
);
#endif /* _HT_FEAT_TRAFFIC_DISTRIBUTION_H_ */

153
src/vendorcode/amd/agesa/f14/Proc/HT/Features/htIds.c
View File

@ -1,153 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Implementation.
*
* Contains AMD AGESA Integrated Debug HT related support.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "IdsHt.h"
#include "htInterface.h"
#include "htInterfaceGeneral.h"
#include "htNb.h"
#include "heapManager.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_FEATURES_HTIDS_FILECODE
/*-------------------------------------------------------------------------------------*/
/**
* Apply an IDS port override to the desired HT link.
*
* The IDS port override allows absolute control of a link's frequency and width, such as
* would be used for board characterization and test. The IDS backend code is responsible
* for handling the NV items and building them into a port override list. Here we search
* that list for any overrides which apply, and update the data used by the HT feature code.
*
* @param[in] IsSourcePort Since we handle both ports on a match, only do that if TRUE.
* @param[in,out] Port0 The PORTLIST item for the first endpoint of a link.
* @param[in,out] Port1 The PORTLIST item for the second endpoint of a link.
* @param[in,out] PortOverrideList IN: A pointer to the port override list or NULL,
* OUT: A pointer to the port override list.
* @param[in] State access to ht interface and nb support methods.
*
*/
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
)
{
LOCATE_HEAP_PTR LocHeapParams;
UINT8 SocketA;
UINT8 SocketB;
UINT8 PackageLinkA;
UINT8 PackageLinkB;
HTIDS_PORT_OVERRIDE_LIST p;
if (IsSourcePort) {
ASSERT (PortOverrideList != NULL);
// The caller can cache the override list by providing the pointer (to the heap buffer).
// If the pointer to the port override list is null, then check if it is on the heap,
// and update the caller's pointer so it is cached.
// If the buffer is not in heap, call the IDS backend to get the NV data (which is likely also
// in heap).
if (*PortOverrideList == NULL) {
// locate the table in heap
LocHeapParams.BufferHandle = IDS_HT_DATA_HANDLE;
if (HeapLocateBuffer (&LocHeapParams, State->ConfigHandle) == AGESA_SUCCESS) {
*PortOverrideList = (HTIDS_PORT_OVERRIDE_LIST)LocHeapParams.BufferPtr;
} else {
// Ask IDS backend code for the list
IDS_OPTION_HOOK (IDS_HT_CONTROL, PortOverrideList, State->ConfigHandle);
}
}
ASSERT (*PortOverrideList != NULL);
// Search the port override list to see if there is an override that applies to this link.
// The match criteria are if either endpoint of the current port list item matches
// port override.
p = *PortOverrideList;
SocketA = State->HtInterface->GetSocketFromMap (Port0->NodeID, State);
PackageLinkA = State->Nb->GetPackageLink (Port0->NodeID, Port0->Link, State->Nb);
SocketB = State->HtInterface->GetSocketFromMap (Port1->NodeID, State);
PackageLinkB = State->Nb->GetPackageLink (Port1->NodeID, Port1->Link, State->Nb);
while ((p != NULL) && (p->Socket != HT_LIST_TERMINAL)) {
if (((p->Socket == SocketA) || (p->Socket == HT_LIST_MATCH_ANY)) &&
((p->Link == PackageLinkA) ||
((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkA)))) ||
((p->Socket == SocketB) || (p->Socket == HT_LIST_MATCH_ANY)) &&
((p->Link == PackageLinkB) ||
((p->Link == HT_LIST_MATCH_ANY) && (!IsPackageLinkInternal (PackageLinkA))) ||
((p->Link == HT_LIST_MATCH_INTERNAL_LINK) && (IsPackageLinkInternal (PackageLinkB))))) {
// Found a match, update width and frequency of both endpoints.
if (p->WidthIn != HT_LIST_TERMINAL) {
Port0->SelWidthIn = p->WidthIn;
Port1->SelWidthOut = p->WidthIn;
}
if (p->WidthOut != HT_LIST_TERMINAL) {
Port0->SelWidthOut = p->WidthOut;
Port1->SelWidthIn = p->WidthOut;
}
if (p->Frequency != HT_LIST_TERMINAL) {
Port0->SelFrequency = p->Frequency;
Port1->SelFrequency = p->Frequency;
}
break;
} else {
p++;
}
}
}
}

492
src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbCoherent.c
View File

@ -1,492 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Feature Northbridge routines.
*
* Provide access to hardware for routing, coherent discovery.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbCoherent.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_NBCOMMON_HTNBCOHERENT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** FAMILY/NORTHBRIDGE SPECIFIC FUNCTIONS ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Establish a Temporary route from one Node to another.
*
* @HtNbMethod{::F_WRITE_ROUTING_TABLE}
*
* This routine will modify the routing tables on the
* SourceNode to cause it to route both request and response traffic to the
* targetNode through the specified Link.
*
* @note: This routine is to be used for early discovery and initialization. The
* final routing tables must be loaded some other way because this
* routine does not address the issue of probes, or independent request
* response paths.
*
* @param[in] Node the Node that will have it's routing tables modified.
* @param[in] Target For routing to Node target
* @param[in] Link Link from Node to target
* @param[in] Nb this northbridge
*/
VOID
WriteRoutingTable (
IN UINT8 Node,
IN UINT8 Target,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES) && (Link < Nb->MaxLinks));
Temp = (Nb->SelfRouteResponseMask | Nb->SelfRouteRequestMask) << (Link + 1);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_ROUTE0_0X40 + (Target * 4));
LibAmdPciWrite (AccessWidth32, Reg, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Modifies the NodeID register on the target Node
*
* @HtNbMethod{::F_WRITE_NODEID}
*
* @param[in] Node the Node that will have its NodeID altered.
* @param[in] NodeID the new value for NodeID
* @param[in] Nb this northbridge
*/
VOID
WriteNodeID (
IN UINT8 Node,
IN UINT8 NodeID,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = NodeID;
ASSERT ((Node < MAX_NODES) && (NodeID < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciWriteBits (Reg, 2, 0, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read the Default Link
*
* @HtNbMethod{::F_READ_DEFAULT_LINK}
*
* Read the DefLnk (the source Link of the current packet) from Node. Since this code
* is running on the BSP, this should be the Link pointing back towards the BSP.
*
* @param[in] Node the Node that will have its NodeID altered.
* @param[in] Nb this northbridge
*
* @return The HyperTransport Link where the request to
* read the default Link came from.
*/
UINT8
ReadDefaultLink (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 DefaultLink;
PCI_ADDR Reg;
UINT32 Temp;
DefaultLink = 0;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_INIT_CONTROL_0X6C);
ASSERT ((Node < MAX_NODES));
LibAmdPciReadBits (Reg, 3, 2, &DefaultLink, Nb->ConfigHandle);
LibAmdPciReadBits (Reg, 8, 8, &Temp, Nb->ConfigHandle);
DefaultLink |= (Temp << 2);
return (UINT8)DefaultLink;
}
/*----------------------------------------------------------------------------------------*/
/**
* Turns routing tables on for a given Node
*
* @HtNbMethod{::F_ENABLE_ROUTING_TABLES}
*
* @param[in] Node the Node that will have it's routing tables enabled
* @param[in] Nb this northbridge
*/
VOID
EnableRoutingTables (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = 0;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_INIT_CONTROL_0X6C);
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Turns routing tables off for a given Node
*
* @HtNbMethod{::F_DISABLE_ROUTING_TABLES}
*
* @param[in] Node the Node that will have it's routing tables disabled
* @param[in] Nb this northbridge
*/
VOID
DisableRoutingTables (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = 1;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_INIT_CONTROL_0X6C);
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Verify that the Link is coherent, connected, and ready
*
* @HtNbMethod{::F_VERIFY_LINK_IS_COHERENT}
*
* @param[in] Node the Node that will be examined
* @param[in] Link the Link on that Node to examine
* @param[in] Nb this northbridge
*
* @retval TRUE The Link has the following status
* - LinkCon=1, Link is connected
* - InitComplete=1, Link initialization is complete
* - NC=0, Link is coherent
* - UniP-cLDT=0, Link is not Uniprocessor cLDT
* - LinkConPend=0 Link connection is not pending
* @retval FALSE The Link has some other status
*/
BOOLEAN
VerifyLinkIsCoherent (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
UINT32 LinkType;
PCI_ADDR LinkBase;
ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
// FN0_98/A4/C4 = LDT Type Register
LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
// Verify LinkCon = 1, InitComplete = 1, NC = 0, UniP-cLDT = 0, LinkConPend = 0
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT);
}
/*----------------------------------------------------------------------------------------*/
/**
* Read the token stored in the scratchpad register field.
*
* @HtNbMethod{::F_READ_TOKEN}
*
* Use the CPU core count as a scratch pad.
*
* @note The location used to store the token is arbitrary. The only requirement is
* that the location warm resets to zero, and that using it will have no ill-effects
* during HyperTransport initialization.
*
* @param[in] Node the Node that will be examined
* @param[in] Nb this northbridge
*
* @return the Token read from the Node
*/
UINT8
ReadToken (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES));
// Use CpuCnt as a scratch register
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciReadBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
return (UINT8)Temp;
}
/*----------------------------------------------------------------------------------------*/
/**
* Write the token stored in the scratchpad register
*
* @HtNbMethod{::F_WRITE_TOKEN}
*
* Use the CPU core count as a scratch pad.
*
* @note The location used to store the token is arbitrary. The only requirement is
* that the location warm resets to zero, and that using it will have no ill-effects
* during HyperTransport initialization.
*
* @param[in] Node the Node that marked with token
* @param[in] Value the token Value
* @param[in] Nb this northbridge
*/
VOID
WriteToken (
IN UINT8 Node,
IN UINT8 Value,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = Value;
ASSERT ((Node < MAX_NODES));
// Use CpuCnt as a scratch register
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciWriteBits (Reg, 19, 16, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Full Routing Table Register initialization
*
* @HtNbMethod{::F_WRITE_FULL_ROUTING_TABLE}
*
* Write the routing table entry for Node to target, using the request Link, response
* Link, and broadcast Links provided.
*
* @param[in] Node the Node that will be examined
* @param[in] Target the Target Node for these routes
* @param[in] ReqLink the Link for requests to Target
* @param[in] RspLink the Link for responses to Target
* @param[in] BroadcastLinks the broadcast Links
* @param[in] Nb this northbridge
*/
VOID
WriteFullRoutingTable (
IN UINT8 Node,
IN UINT8 Target,
IN UINT8 ReqLink,
IN UINT8 RspLink,
IN UINT32 BroadcastLinks,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Value;
Value = 0;
ASSERT ((Node < MAX_NODES) && (Target < MAX_NODES));
if (ReqLink == ROUTE_TO_SELF) {
Value |= Nb->SelfRouteRequestMask;
} else {
Value |= Nb->SelfRouteRequestMask << (ReqLink + 1);
}
if (RspLink == ROUTE_TO_SELF) {
Value |= Nb->SelfRouteResponseMask;
} else {
Value |= Nb->SelfRouteResponseMask << (RspLink + 1);
}
// Allow us to accept a Broadcast ourselves, then set broadcasts for routes
Value |= (UINT32)1 << Nb->BroadcastSelfBit;
Value |= (UINT32)BroadcastLinks << (Nb->BroadcastSelfBit + 1);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_ROUTE0_0X40 + (Target * 4));
LibAmdPciWrite (AccessWidth32, Reg, &Value, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
* @HtNbMethod{::F_IS_ILLEGAL_TYPE_MIX}.
*
* Currently, that means the family, extended family of the new Node are the
* same as the BSP's.
*
* @param[in] Node the Node
* @param[in] Nb this northbridge
*
* @retval TRUE the new node is not compatible
* @retval FALSE the new node is compatible
*/
BOOLEAN
IsIllegalTypeMix (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
return ((BOOLEAN) ((Nb->MakeKey (Node, Nb) & Nb->CompatibleKey) == 0));
}
/*----------------------------------------------------------------------------------------*/
/**
* Fix (hopefully) exceptional conditions.
*
* @HtNbMethod{::F_HANDLE_SPECIAL_NODE_CASE}.
*
* Currently, this routine is implemented for all coherent HT families to check
* vendor ID of coherent Node. If the vendor ID is 0x1022 then return FALSE,
* or return TRUE.
*
* @param[in] Node The Node which need to be checked.
* @param[in] Link The link to check for special conditions.
* @param[in] State our global state.
* @param[in] Nb this northbridge.
*
* @retval TRUE This node received special handling.
* @retval FALSE This node was not handled specially, handle it normally.
*
*/
BOOLEAN
HandleSpecialNodeCase (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
BOOLEAN Result;
PCI_ADDR Reg;
UINT32 VendorID;
Result = TRUE;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
0,
0);
LibAmdPciReadBits (Reg, 15, 0, &VendorID, Nb->ConfigHandle);
if (VendorID == 0x1022) {
Result = FALSE;
}
return Result;
}

178
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@ -1,178 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Coherent Feature Northbridge common routines.
*
* Provide access to hardware for routing, coherent discovery.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** FAMILY/NORTHBRIDGE GENERIC FUNCTIONS ***
***************************************************************************/
/**
* Establish a Temporary route from one Node to another.
*
*/
VOID
WriteRoutingTable (
IN UINT8 Node,
IN UINT8 Target,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);
/**
* Modifies the NodeID register on the target Node
*
*/
VOID
WriteNodeID (
IN UINT8 Node,
IN UINT8 NodeID,
IN NORTHBRIDGE *Nb
);
/**
* Read the Default Link
*
*/
UINT8
ReadDefaultLink (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Turns routing tables on for a given Node
*
*/
VOID
EnableRoutingTables (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Turns routing tables off for a given Node
*
*/
VOID
DisableRoutingTables (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Verify that the Link is coherent, connected, and ready
*
*/
BOOLEAN
VerifyLinkIsCoherent (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);
/**
* Read the token stored in the scratchpad register field.
*
*/
UINT8
ReadToken (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Write the token stored in the scratchpad register
*
*/
VOID
WriteToken (
IN UINT8 Node,
IN UINT8 Value,
IN NORTHBRIDGE *Nb
);
/**
* Full Routing Table Register initialization
*
*/
VOID
WriteFullRoutingTable (
IN UINT8 Node,
IN UINT8 Target,
IN UINT8 ReqLink,
IN UINT8 RspLink,
IN UINT32 BroadcastLinks,
IN NORTHBRIDGE *Nb
);
/**
* Determine whether a Node is compatible with the discovered configuration so far.
*
*/
BOOLEAN
IsIllegalTypeMix (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Fix (hopefully) exceptional conditions.
*
*/
BOOLEAN
HandleSpecialNodeCase (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);

142
src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbNonCoherent.c
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@ -1,142 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge generic non-coherent support routines.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbNonCoherent.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_NBCOMMON_HTNBNONCOHERENT_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Non-coherent init code ***
*** Northbridge access routines ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Return the Link to the Southbridge
*
* @HtNbMethod{::F_READ_SB_LINK}
*
* @param[in] Nb this northbridge
*
* @return the Link to the southbridge
*/
UINT8
ReadSouthbridgeLink (
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
MakePciBusFromNode (0),
MakePciDeviceFromNode (0),
CPU_HTNB_FUNC_00,
REG_UNIT_ID_0X64);
LibAmdPciReadBits (Reg, 10, 8, &Temp, Nb->ConfigHandle);
return (UINT8)Temp;
}
/*----------------------------------------------------------------------------------------*/
/**
* Verify that the Link is non-coherent, connected, and ready
*
* @HtNbMethod{::F_VERIFY_LINK_IS_NON_COHERENT}
*
* @param[in] Node the Node that will be examined
* @param[in] Link the Link on that Node to examine
* @param[in] Nb this northbridge
*
* @retval TRUE The Link has the following status
* - LinkCon=1, Link is connected
* - InitComplete=1, Link initialization is complete
* - NC=1, Link is noncoherent
* - UniP-cLDT=0, Link is not Uniprocessor cLDT
* - LinkConPend=0 Link connection is not pending
* @retval FALSE The Link has some other status
*/
BOOLEAN
VerifyLinkIsNonCoherent (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
UINT32 LinkType;
PCI_ADDR LinkBase;
ASSERT ((Node < MAX_NODES) && (Link < MAX_NODES));
LinkBase = Nb->MakeLinkBase (Node, Link, Nb);
LinkBase.Address.Register += HTHOST_LINK_TYPE_REG;
// FN0_98/A4/C4 = LDT Type Register
LibAmdPciRead (AccessWidth32, LinkBase, &LinkType, Nb->ConfigHandle);
// Verify LinkCon = 1, InitComplete = 1, NC = 1, UniP-cLDT = 0, LinkConPend = 0
return (BOOLEAN) ((LinkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_NONCOHERENT);
}

62
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@ -1,62 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge generic non-coherent support routines.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Return the Link to the Southbridge
*/
UINT8
ReadSouthbridgeLink (
IN NORTHBRIDGE *Nb
);
/**
* Verify that the Link is non-coherent, connected, and ready
*
*/
BOOLEAN
VerifyLinkIsNonCoherent (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);

258
src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbOptimization.c
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@ -1,258 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link optimization support.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "IdsHt.h"
#include "htInterface.h"
#include "htInterfaceGeneral.h"
#include "htNotify.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbOptimization.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_NBCOMMON_HTNBOPTIMIZATION_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/***************************************************************************
*** Link Optimization ***
***************************************************************************/
/*----------------------------------------------------------------------------------------*/
/**
* Get Link features into system data structure.
*
* @HtNbMethod{::F_GATHER_LINK_FEATURES}
*
* For a specific discovered CPU Link, populate the port list with the frequency
* capabilities. Support for other link oriented capabilities, currently:
* - Unit ID Clumping. Set to disabled. This doesn't mean the CPU doesn't support clumping,
* it just means:
* - The CPU doesn't clump its host unit ids, and
* - We don't have to check as carefully in SetLinkData whether the port is an IO host link.
*
* @param[in,out] ThisPort The PortList structure entry for this link's port
* @param[in] Interface Access to non-HT support functions.
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[in] Nb this northbridge
*/
VOID
GatherLinkFeatures (
IN OUT PORT_DESCRIPTOR *ThisPort,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Frequency;
UINT32 ExtendedFrequency;
Reg = ThisPort->Pointer;
Reg.Address.Register += HTHOST_FREQ_REV_REG;
LibAmdPciReadBits (Reg, 30, 16, &Frequency, Nb->ConfigHandle);
Reg = ThisPort->Pointer;
Reg.Address.Register += HTHOST_FREQ_EXTENSION;
LibAmdPciReadBits (Reg, 15, 1, &ExtendedFrequency, Nb->ConfigHandle);
ThisPort->PrvFrequencyCap = ((Frequency | (ExtendedFrequency << HT_FREQUENCY_2800M)) &
Nb->NorthBridgeFreqMask (ThisPort->NodeID, Interface, PlatformConfig, Nb));
// Check for Internal link restriction not to run at 1000 MHz (but allow lower)
if (IsPackageLinkInternal (Nb->GetPackageLink (ThisPort->NodeID, ThisPort->Link, Nb))) {
ThisPort->PrvFrequencyCap &= ~(HT_FREQUENCY_LIMIT_1000M & ~HT_FREQUENCY_LIMIT_800M);
}
ThisPort->ClumpingSupport = HT_CLUMPING_DISABLE;
}
/*----------------------------------------------------------------------------------------*/
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link reganging.
*
* @HtNbMethod{::F_SET_LINK_REGANG}
*
* @param[in] Node the node on which to regang a link
* @param[in] Link the sublink 0 of the sublink pair to regang
* @param[in] Nb this northbridge
*/
VOID
SetLinkRegang (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
UINT32 Temp;
Temp = 1;
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for Unit Id Clumping.
*
* @HtNbMethod{::F_SET_LINK_UNITID_CLUMPING}
*
* This applies to the host root of a non-coherent chain.
*
* @param[in] Node the node on which to enable clumping
* @param[in] Link the link for which to enable clumping
* @param[in] ClumpingEnables the unit id clumping enables
* @param[in] Nb this northbridge
*/
VOID
SetLinkUnitIdClumping (
IN UINT8 Node,
IN UINT8 Link,
IN UINT32 ClumpingEnables,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR Reg;
// Host Unit Ids are not clumped.
ASSERT ((ClumpingEnables & 0x3) == 0);
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_CLUMPING0_0X110 + (4 * Link));
LibAmdPciWriteBits (Reg, 31, 0, &ClumpingEnables, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure for link frequency.
*
* @HtNbMethod{::F_SET_LINK_FREQUENCY}
*
* Handle extended frequencies. For HT3 frequencies, ensure Retry and Scrambling are
* set. For HT1, clear them.
*
* @param[in] Node the node on which to set frequency for a link
* @param[in] Link the link to set frequency
* @param[in] Frequency the frequency to set
* @param[in] Nb this northbridge
*/
VOID
SetLinkFrequency (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Frequency,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
ASSERT ((Frequency >= HT_FREQUENCY_600M && Frequency <= HT_FREQUENCY_3200M)
|| (Frequency == HT_FREQUENCY_200M) || (Frequency == HT_FREQUENCY_400M));
// Handle extended frequencies, 2800 MHz and above. 31 > Frequency > 16 in this case.
if (Frequency > HT_FREQUENCY_2600M) {
Temp = 1;
} else {
// Clear it if not extended.
Temp = 0;
}
Reg = Nb->MakeLinkBase (Node, Link, Nb);
Reg.Address.Register += HTHOST_FREQ_EXTENSION;
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
Reg = Nb->MakeLinkBase (Node, Link, Nb);
Reg.Address.Register += HTHOST_FREQ_REV_REG;
Temp = (Frequency & 0x0F);
LibAmdPciWriteBits (Reg, 11, 8, &Temp, Nb->ConfigHandle);
// Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
if (Frequency > HT_FREQUENCY_1000M) {
// Enable for Gen3 frequencies
Temp = 1;
} else {
// Disable for Gen1 frequencies
Temp = 0;
}
// HT3 retry mode enable / disable
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_RETRY0_0X130 + (4 * Link));
LibAmdPciWriteBits (Reg, 0, 0, &Temp, Nb->ConfigHandle);
// and Scrambling enable / disable
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_LINK_EXT_CONTROL0_0X170 + (4 * Link));
LibAmdPciWriteBits (Reg, 3, 3, &Temp, Nb->ConfigHandle);
}

91
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@ -1,91 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Link optimization generic support.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Get Link features into system data structure.
*
*/
VOID
GatherLinkFeatures (
IN OUT PORT_DESCRIPTOR *ThisPort,
IN HT_INTERFACE *Interface,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN NORTHBRIDGE *Nb
);
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
*
*/
VOID
SetLinkRegang (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);
/**
* Set the link's Unit Id Clumping enable.
*
*/
VOID
SetLinkUnitIdClumping (
IN UINT8 Node,
IN UINT8 Link,
IN UINT32 ClumpingEnables,
IN NORTHBRIDGE *Nb
);
/**
* Change the hardware state for all Links according to the now optimized data in the
* port list data structure.
*/
VOID
SetLinkFrequency (
IN UINT8 Node,
IN UINT8 Link,
IN UINT8 Frequency,
IN NORTHBRIDGE *Nb
);

335
src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.c
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@ -1,335 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge utility routines.
*
* These routines are needed for support of more than one feature area.
* Collect them in this file so build options don't remove them.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "Topology.h"
#include "htFeat.h"
#include "htNotify.h"
#include "htNb.h"
#include "htNbHardwareFam10.h"
#include "htNbUtilities.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_NBCOMMON_HTNBUTILITIES_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Return the HT Host capability base PCI config address for a Link.
*
* @HtNbMethod{::F_MAKE_LINK_BASE}
*
* @param[in] Node the Node this Link is on
* @param[in] Link the Link
* @param[in] Nb this northbridge
*
* @return the pci config address
*/
PCI_ADDR
MakeLinkBase (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR LinkBase;
ASSERT (Nb != NULL);
if (Link < 4) {
LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_HT_CAP_BASE_0X80 + Link*HT_HOST_CAP_SIZE);
} else {
LinkBase.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_04,
REG_HT_CAP_BASE_0X80 + (Link - 4)*HT_HOST_CAP_SIZE);
}
return LinkBase;
}
/*----------------------------------------------------------------------------------------*/
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
* @HtNbMethod{::F_READ_TRUE_LINK_FAIL_STATUS}
*
* Dependency!: HT_FEATURES::SetHtControlRegisterBits
*
* Also, call event notify if a Hardware Fault caused a sync flood on a previous boot.
*
* The table below summarizes correct responses of this routine.
* <TABLE>
* <TR><TD> Family </TD> <TD> before </TD> <TD> after </TD> <TD> unconnected </TD> <TD> Notify? </TD> <TD> return </TD></TR>
* <TR><TD> 10 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> No </TD> <TD> FALSE </TD></TR>
* <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 0 </TD> <TD> Yes </TD> <TD> FALSE </TD></TR>
* <TR><TD> 10 </TD> <TD> 1 </TD> <TD> 0 </TD> <TD> 3 </TD> <TD> No </TD> <TD> TRUE </TD></TR>
* </TABLE>
*
* @param[in] Node the Node that will be examined
* @param[in] Link the Link on that Node to examine
* @param[in] State access to call back routine
* @param[in] Nb this northbridge
*
* @retval TRUE the Link is not connected or has hard error
* @retval FALSE the Link is connected
*/
BOOLEAN
ReadTrueLinkFailStatus (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
)
{
UINT32 Before;
UINT32 After;
UINT32 Unconnected;
UINT32 Crc;
PCI_ADDR Reg;
ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
Reg = Nb->MakeLinkBase (Node, Link, Nb);
Reg.Address.Register += HTHOST_LINK_CONTROL_REG;
// Save the CRC status before doing anything else.
// Read, Clear, re-read the error bits in the Link Control Register
// (FN0_84/A4/C4[4] = LinkFail bit),
// and check the connection status, TransOff and EndOfChain.
//
LibAmdPciReadBits (Reg, 9, 8, &Crc, Nb->ConfigHandle);
LibAmdPciReadBits (Reg, 4, 4, &Before, Nb->ConfigHandle);
State->HtFeatures->SetHtControlRegisterBits (Reg, 4, 4, &Before, State);
LibAmdPciReadBits (Reg, 4, 4, &After, Nb->ConfigHandle);
LibAmdPciReadBits (Reg, 7, 6, &Unconnected, Nb->ConfigHandle);
if (Before != After) {
if (Unconnected == 0) {
if (Crc != 0) {
// A sync flood occurred due to HT CRC
// Pass the Node and Link on which the generic sync flood event occurred.
NotifyAlertHwHtCrc (Node, Link, (UINT8)Crc, State);
} else {
// Some sync flood occurred
// Pass the Node and Link on which the generic sync flood event occurred.
NotifyAlertHwSyncFlood (Node, Link, State);
}
}
}
return (BOOLEAN) ((After != 0) || (Unconnected != 0));
}
/*----------------------------------------------------------------------------------------*/
/**
* Write the total number of cores and Nodes to the Node
*
* @HtNbMethod{::F_SET_TOTAL_NODES_AND_CORES}
*
* @param[in] Node the Node that will be examined
* @param[in] TotalNodes the total number of Nodes
* @param[in] TotalCores the total number of cores
* @param[in] Nb this northbridge
*/
VOID
SetTotalNodesAndCores (
IN UINT8 Node,
IN UINT8 TotalNodes,
IN UINT8 TotalCores,
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR NodeIDReg;
UINT32 Temp;
ASSERT ((Node < MAX_NODES) && (TotalNodes <= MAX_NODES));
NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
Temp = ((TotalCores - 1) & HTREG_NODE_CPUCNT_4_0);
LibAmdPciWriteBits (NodeIDReg, 20, 16, &Temp, Nb->ConfigHandle);
Temp = TotalNodes - 1;
LibAmdPciWriteBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
NodeIDReg.Address.Register = REG_HT_EXTENDED_NODE_ID_F0X160;
Temp = (((TotalCores - 1) & HTREG_EXTNODE_CPUCNT_7_5) >> 5);
LibAmdPciWriteBits (NodeIDReg, 18, 16, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Get the Count (1 based) of Nodes in the system.
*
* @HtNbMethod{::F_GET_NODE_COUNT}
*
* This is intended to support AP Core HT init, since the Discovery State data is not
* available (State->NodesDiscovered), there needs to be this way to find the number
* of Nodes. The Node count can be read from the BSP.
*
* @param[in] Nb this northbridge
*
* @return The number of nodes
*/
UINT8
GetNodeCount (
IN NORTHBRIDGE *Nb
)
{
PCI_ADDR NodeIDReg;
UINT32 Temp;
NodeIDReg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (0),
MakePciBusFromNode (0),
MakePciDeviceFromNode (0),
CPU_HTNB_FUNC_00,
REG_NODE_ID_0X60);
LibAmdPciReadBits (NodeIDReg, 6, 4, &Temp, Nb->ConfigHandle);
return ((UINT8) (++Temp));
}
/*----------------------------------------------------------------------------------------*/
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
* @HtNbMethod{::F_LIMIT_NODES}
*
* @param[in] Node the Node that will be examined
* @param[in] Nb this northbridge
*/
VOID
LimitNodes (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
)
{
UINT32 Temp;
PCI_ADDR Reg;
Temp = 1;
ASSERT ((Node < MAX_NODES));
Reg.AddressValue = MAKE_SBDFO (MakePciSegmentFromNode (Node),
MakePciBusFromNode (Node),
MakePciDeviceFromNode (Node),
CPU_HTNB_FUNC_00,
REG_LINK_TRANS_CONTROL_0X68);
LibAmdPciWriteBits (Reg, 15, 15, &Temp, Nb->ConfigHandle);
}
/*----------------------------------------------------------------------------------------*/
/**
* Get the Package Link number, given the node and real link number.
*
* @HtNbMethod{::F_GET_PACKAGE_LINK}
*
* Based on the link to package link mapping from BKDG, look up package link for
* the input link on the internal node number corresponding to Node id.
*
* @param[in] Node the node which has this link
* @param[in] Link the link on that node
* @param[in] Nb this northbridge
*
* @return the Package Link, HT_LIST_TERMINAL Not connected in package, HT_LIST_MATCH_INTERNAL_LINK package internal link.
*
*/
UINT8
GetPackageLink (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
)
{
UINT8 ModuleType;
UINT8 Module;
UINTN PackageLinkMapItem;
UINT8 PackageLink;
ASSERT ((Node < MAX_NODES) && (Link < Nb->MaxLinks));
PackageLink = HT_LIST_TERMINAL;
Nb->GetModuleInfo (Node, &ModuleType, &Module, Nb);
if (ModuleType != 0) {
ASSERT (Nb->PackageLinkMap != NULL);
// Use table to find this module's package link
PackageLinkMapItem = 0;
while ((*Nb->PackageLinkMap)[PackageLinkMapItem].Link != HT_LIST_TERMINAL) {
if (((*Nb->PackageLinkMap)[PackageLinkMapItem].Module == Module) &&
((*Nb->PackageLinkMap)[PackageLinkMapItem].Link == Link)) {
PackageLink = (*Nb->PackageLinkMap)[PackageLinkMapItem].PackageLink;
break;
}
PackageLinkMapItem++;
}
} else {
PackageLink = Link;
}
return PackageLink;
}

108
src/vendorcode/amd/agesa/f14/Proc/HT/NbCommon/htNbUtilities.h
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@ -1,108 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Northbridge utility routines.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/**
* Return the HT Host capability base PCI config address for a Link.
*
*/
PCI_ADDR
MakeLinkBase (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);
/**
* Return the LinkFailed status AFTER an attempt is made to clear the bit.
*
*/
BOOLEAN
ReadTrueLinkFailStatus (
IN UINT8 Node,
IN UINT8 Link,
IN STATE_DATA *State,
IN NORTHBRIDGE *Nb
);
/**
* Write the total number of cores and Nodes to the Node
*
*/
VOID
SetTotalNodesAndCores (
IN UINT8 Node,
IN UINT8 TotalNodes,
IN UINT8 TotalCores,
IN NORTHBRIDGE *Nb
);
/**
* Get the Count (1 based) of Nodes in the system.
*
*/
UINT8
GetNodeCount (
IN NORTHBRIDGE *Nb
);
/**
* Limit coherent config accesses to cpus as indicated by Nodecnt.
*
*/
VOID
LimitNodes (
IN UINT8 Node,
IN NORTHBRIDGE *Nb
);
/**
* Get the Package Link number, given the node and real link number.
*
*/
UINT8
GetPackageLink (
IN UINT8 Node,
IN UINT8 Link,
IN NORTHBRIDGE *Nb
);

199
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph.c
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@ -1,199 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Routines to deal with topology data.
*
* Access the topologies and information about a topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "AGESA.h"
#include "Ids.h"
#include "htGraph.h"
#include "OptionsHt.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_HT_HTGRAPH_HTGRAPH_FILECODE
extern OPTION_HT_CONFIGURATION OptionHtConfiguration;
/*----------------------------------------------------------------------------------------*/
/**
* Returns the AGESA built in topology list
*
* @param[out] List a pointer to the built in topology list
*/
VOID
GetAmdTopolist (
OUT UINT8 ***List
)
{
// Cast below to hush CONST warning. The built in list must be CONST to be in ROM statically.
// The caller of this routine may get a topolist pointer from the interface, however, and
// that is not CONST, since it could be on the stack.
//
*List = (UINT8 **)OptionHtConfiguration.HtOptionBuiltinTopologies;
}
/*----------------------------------------------------------------------------------------*/
/**
* Returns the number of Nodes in the compressed graph
*
* @param[in] Graph a compressed graph
*
* @return the number of Nodes in the graph
*/
UINT8
GraphHowManyNodes (
IN UINT8 *Graph
)
{
return Graph[0];
}
/*----------------------------------------------------------------------------------------*/
/**
* Returns true if NodeA is directly connected to NodeB, false otherwise
*
* if NodeA == NodeB also returns false.
* Relies on rule that directly connected Nodes always route requests directly.
*
* @param[in] Graph the graph to examine
* @param[in] NodeA the Node number of the first Node
* @param[in] NodeB the Node number of the second Node
*
* @retval TRUE NodeA connects to NodeB
* @retval FALSE NodeA does not connect to NodeB
*/
BOOLEAN
GraphIsAdjacent (
IN UINT8 *Graph,
IN UINT8 NodeA,
IN UINT8 NodeB
)
{
UINT8 size;
size = Graph[0];
ASSERT ((NodeA < size) && (NodeB < size));
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F) == NodeB;
}
/*----------------------------------------------------------------------------------------*/
/**
* Returns the graph Node used by NodeA to route responses targeted at NodeB.
*
* This will be a Node directly connected to NodeA (possibly NodeB itself),
* or "Route to Self" if NodeA and NodeB are the same Node.
* Note that all Node numbers are abstract Node numbers of the topology graph,
* it is the responsibility of the caller to apply any permutation needed.
*
* @param[in] Graph the graph to examine
* @param[in] NodeA the Node number of the first Node
* @param[in] NodeB the Node number of the second Node
*
* @return The response route Node
*/
UINT8
GraphGetRsp (
IN UINT8 *Graph,
IN UINT8 NodeA,
IN UINT8 NodeB
)
{
UINT8 size;
size = Graph[0];
ASSERT ((NodeA < size) && (NodeB < size));
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0xF0) >> 4;
}
/*----------------------------------------------------------------------------------------*/
/**
* Returns the graph Node used by NodeA to route requests targeted at NodeB.
*
* This will be a Node directly connected to NodeA (possibly NodeB itself),
* or "Route to Self" if NodeA and NodeB are the same Node.
* Note that all Node numbers are abstract Node numbers of the topology graph,
* it is the responsibility of the caller to apply any permutation needed.
*
* @param[in] Graph the graph to examine
* @param[in] NodeA the Node number of the first Node
* @param[in] NodeB the Node number of the second Node
*
* @return The request route Node
*/
UINT8
GraphGetReq (
IN UINT8 *Graph,
IN UINT8 NodeA,
IN UINT8 NodeB
)
{
UINT8 size;
size = Graph[0];
ASSERT ((NodeA < size) && (NodeB < size));
return (Graph[1 + (NodeA*size + NodeB)*2 + 1] & 0x0F);
}
/*----------------------------------------------------------------------------------------*/
/**
* Returns a bit vector of Nodes that NodeA should forward a broadcast from
* NodeB towards
*
* @param[in] Graph the graph to examine
* @param[in] NodeA the Node number of the first Node
* @param[in] NodeB the Node number of the second Node
*
* @return the broadcast routes for NodeA from NodeB
*/
UINT8
GraphGetBc (
IN UINT8 *Graph,
IN UINT8 NodeA,
IN UINT8 NodeB
)
{
UINT8 size;
size = Graph[0];
ASSERT ((NodeA < size) && (NodeB < size));
return Graph[1 + (NodeA*size + NodeB)*2];
}

70
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@ -1,70 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Single node topology
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 0
*/
/**
* single node
*/
/**
* @dot
strict graph one {
node [shape="plaintext"];
0;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySingleNode[] =
{
0x01,
0x00, 0xFF // Node 0
};

71
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph2.c
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@ -1,71 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Two nodes.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 0---1
*/
/**
* Two Nodes.
*/
/**
* @dot
strict graph two {
node [shape="plaintext"];
0 -- 1 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyDualNode[] =
{
0x02,
0x02, 0xFF, 0x00, 0x11, // Node 0
0x00, 0x00, 0x01, 0xFF // Node 1
};

76
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph3Line.c
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@ -1,76 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Three Line.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2
* |
* |
* 0---1
*/
/**
* Three Line
*/
/**
* @dot
strict graph three {
node [shape="plaintext"];
0 -- 1 ;
0 -- 2 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyThreeLine[] =
{
0x03,
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, // Node 0
0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 1
0x00, 0x00, 0x00, 0x00, 0x01, 0xFF // Node 2
};

77
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph3Triangle.c
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@ -1,77 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Three Triangle Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2
* |\
* | \
* 0---1
*/
/**
* Three triangle
*/
/**
* @dot
strict graph triangle {
node [shape="plaintext"];
0 -- 1 ;
0 -- 2 ;
1 -- 2 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyTriangle[] =
{
0x03,
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, // Node 0
0x00, 0x00, 0x05, 0xFF, 0x00, 0x22, // Node 1
0x00, 0x00, 0x00, 0x11, 0x03, 0xFF // Node 2
};

80
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4Degenerate.c
View File

@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node degenerate.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2 3
* |\ |
* | \|
* 0---1
*/
/**
* Four Node degenerate
*/
/**
* @dot
strict graph degen4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 1 ;
0 -- 2 ;
1 -- 2 ;
1 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourDegenerate[] =
{
0x04,
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
0x08, 0x00, 0x0D, 0xFF, 0x08, 0x22, 0x05, 0x33, // Node 1
0x00, 0x00, 0x00, 0x11, 0x03, 0xFF, 0x00, 0x11, // Node 2
0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
};

83
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4FullyConnected.c
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@ -1,83 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node fully connected.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2---3
* |\ /|
* |/ \|
* 0---1
*/
/**
* Four Node Fully
*/
/**
* @dot
strict graph full4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 1 ;
0 -- 2 ;
0 -- 3 ;
1 -- 2 ;
1 -- 3 ;
2 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourFully[] =
{
0x04,
0x0E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, // Node 0
0x00, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x00, 0x33, // Node 2
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x07, 0xFF // Node 3
};

81
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4Kite.c
View File

@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node kite Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2---3
* |\ |
* | \|
* 0---1
*/
/**
* Four Node kite
*/
/**
* @dot
strict graph kite4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 1 ;
0 -- 2 ;
1 -- 2 ;
1 -- 3 ;
2 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourKite[] =
{
0x04,
0x06, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x11, // Node 0
0x08, 0x00, 0x0D, 0xFF, 0x00, 0x22, 0x00, 0x33, // Node 1
0x00, 0x00, 0x00, 0x11, 0x0B, 0xFF, 0x01, 0x33, // Node 2
0x00, 0x22, 0x00, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
};

80
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4Line.c
View File

@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node Line Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2 3
* | |
* | |
* 0---1
*/
/**
* Four Node line
*/
/**
* @dot
strict graph line4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourLine[] =
{
0x04,
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x04, 0x11, // Node 0
0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, // Node 1
0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0x00, 0x00, // Node 2
0x00, 0x11, 0x00, 0x11, 0x00, 0x11, 0x02, 0xFF // Node 3
};

80
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4Square.c
View File

@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node Square Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2---3
* | |
* | |
* 0---1
*/
/**
* Four Node square
*/
/**
* @dot
strict graph square4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourSquare[] =
{
0x04,
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, // Node 0
0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, // Node 1
0x08, 0x00, 0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, // Node 2
0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x06, 0xFF // Node 3
};

80
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph4Star.c
View File

@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Four node Star Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
* 2---3
* |\
* | \
* 0 1
*/
/**
* Four Node Star
*/
/**
* @dot
strict graph star4 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
0 -- 2 ;
1 -- 2 ;
2 -- 3 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFourStar[] =
{
0x04,
0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node 0
0x00, 0x22, 0x04, 0xFF, 0x00, 0x22, 0x00, 0x22, // Node 1
0x0A, 0x00, 0x09, 0x11, 0x0B, 0xFF, 0x03, 0x33, // Node 2
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x04, 0xFF // Node 3
};

80
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph5FullyConnected.c
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Five node Fully Connected Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* Five node fully connected
*/
/**
* @dot
strict graph full5 {
node [shape="plaintext"];
0 -- 1 ;
0 -- 2 ;
0 -- 3 ;
0 -- 4 ;
1 -- 2 ;
1 -- 3 ;
1 -- 4 ;
2 -- 3 ;
2 -- 4 ;
3 -- 4 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFiveFully[] =
{
0x05,
0x1E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 0
0x00, 0x00, 0x1D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, // Node 1
0x00, 0x00, 0x00, 0x11, 0x1B, 0xFF, 0x00, 0x33, 0x00, 0x44, // Node 2
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x17, 0xFF, 0x00, 0x44, // Node 3
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x0F, 0xFF // Node 4
};

89
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph5TwistedLadder.c
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@ -1,89 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Five node pop order twisted ladder Topology.
*
* The population order fall back to five nodes on a twisted ladder.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
*
* 4
* |\
* | \
* 2 3
* | |
* 0---1
*/
/**
* Five node twisted ladder
*/
/**
* @dot
strict graph twl5 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
{rank=same; 4}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 4 ;
3 -- 4 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyFiveTwistedLadder[] =
{
0x05,
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x00, 0x22, // Node0
0x08, 0x00, 0x09, 0xFF, 0x08, 0x00, 0x01, 0x33, 0x00, 0x30, // Node1
0x10, 0x00, 0x10, 0x00, 0x11, 0xFF, 0x00, 0x40, 0x01, 0x44, // Node2
0x00, 0x11, 0x00, 0x11, 0x00, 0x14, 0x12, 0xFF, 0x02, 0x44, // Node3
0x00, 0x22, 0x00, 0x23, 0x00, 0x22, 0x04, 0x33, 0x0C, 0xFF // Node4
};

75
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph6DoubloonLower.c
View File

@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Six node hydra Topology using "Doubloon/Drachma", Lower nodes remain.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 6 node hydra doubloon lower nodes, 3 MCM processors.
* For partial populations, note nodes are removed in pairs.
*/
/**
* @dot
strict graph doubloon8lower {
node [shape="plaintext"];
0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
0 -- 4 ; 1 -- 5 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySixDoubloonLower[] =
{
0x06,
0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
0x08, 0x00, 0x08, 0x11, 0x19, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x24, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
};

75
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph6DoubloonUpper.c
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@ -1,75 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Six node hydra Topology using "Doubloon/Drachma", Upper nodes remain.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 6 node hydra drachma, upper nodes remain, 3 MCM processors.
* For partial population cases, note that nodes are removed in pairs.
*/
/**
* @dot
strict graph doubloon6upper {
node [shape="plaintext"];
0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ;
0 -- 4 ; 1 -- 5 ; 2 -- 5 ; 3 -- 4 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySixDoubloonUpper[] =
{
0x06,
0x16, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
0x00, 0x00, 0x25, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, // Node 1
0x08, 0x00, 0x08, 0x11, 0x3B, 0xFF, 0x03, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x34, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
0x20, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x2D, 0xFF, 0x00, 0x55, // Node 4
0x00, 0x11, 0x10, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1E, 0xFF, // Node 5
};

86
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph6FullyConnected.c
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@ -1,86 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Six node Fully Connected Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 6 node fully connected
*/
/**
* @dot
strict graph full6 {
node [shape="plaintext"];
0 -- 1 ;
0 -- 2 ;
0 -- 3 ;
0 -- 4 ;
0 -- 5 ;
1 -- 2 ;
1 -- 3 ;
1 -- 4 ;
1 -- 5 ;
2 -- 3 ;
2 -- 4 ;
2 -- 5 ;
3 -- 4 ;
3 -- 5 ;
4 -- 5 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySixFully[] =
{
0x06,
0x3E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 0
0x00, 0x00, 0x3D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 1
0x00, 0x00, 0x00, 0x11, 0x3B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, // Node 2
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x37, 0xFF, 0x00, 0x44, 0x00, 0x55, // Node 3
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x2F, 0xFF, 0x00, 0x55, // Node 4
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x1F, 0xFF // Node 5
};

92
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph6TwinTriangles.c
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@ -1,92 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* A six node Topology of three MCMs.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* (2 fully connected three ways connected at the 'corners')
*
* 5
* /| \
* / 1 - 3
* / / /
* 4 / /
* | \ /
* 0 - 2-
*/
/**
* Six Node hydra
*/
/**
* @dot
strict graph hmcm6 {
node [shape="plaintext"];
subgraph even {
0 -- 2 ; 2 -- 4 ;
0 -- 4 ;
}
subgraph odd {
1 -- 3 ; 3 -- 5
1 -- 5 ;
}
{rank=same; 0; 2; 1; 3}
{rank=same; 4; 5}
0 -- 1 ; 2 -- 3 ; 4 -- 5 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySixTwinTriangles[] =
{
0x06,
0x16, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, // Node 0
0x00, 0x00, 0x29, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, // Node 1
0x08, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, // Node 2
0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x04, 0x55, // Node 3
0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x25, 0xFF, 0x00, 0x55, // Node 4
0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x1A, 0xFF, // Node 5
};

92
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph6TwistedLadder.c
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@ -1,92 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Six node pop order twisted ladder Topology.
*
* The population order fall back to Six nodes on a twisted ladder.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/*
*
* 4 5
* |\ /|
* |/ \|
* 2 3
* | |
* 0---1
*/
/**
* 6 node twisted ladder
*/
/**
* @dot
strict graph twl6 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
{rank=same; 4; 5}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 4 ;
2 -- 5 ;
3 -- 4 ;
3 -- 5 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySixTwistedLadder[] =
{
0x06,
0x06, 0xFF, 0x04, 0x11, 0x02, 0x22, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, // Node0
0x08, 0x00, 0x09, 0xFF, 0x00, 0x00, 0x01, 0x33, 0x00, 0x03, 0x01, 0x33, // Node1
0x30, 0x00, 0x00, 0x00, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x00, 0x55, // Node2
0x00, 0x11, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x00, 0x44, 0x12, 0x55, // Node3
0x00, 0x22, 0x00, 0x32, 0x08, 0x22, 0x00, 0x33, 0x0C, 0xFF, 0x00, 0x32, // Node4
0x00, 0x23, 0x00, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF // Node5
};

78
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph7FullyConnected.c
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@ -1,78 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Seven node Fully Connected Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 7 node fully connected
*/
/**
* @dot
strict graph full7 {
node [shape="plaintext"];
0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ;
0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ;
0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ;
0 -- 4 ; 1 -- 5 ; 2 -- 6 ;
0 -- 5 ; 1 -- 6 ;
0 -- 6 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySevenFully[] =
{
0x07,
0x7E, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 0
0x00, 0x00, 0x7D, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 1
0x00, 0x00, 0x00, 0x11, 0x7B, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 2
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x77, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, // Node 3
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x6F, 0xFF, 0x00, 0x55, 0x00, 0x66, // Node 4
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x5F, 0xFF, 0x00, 0x66, // Node 5
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x3F, 0xFF // Node 6
};

95
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph7TwistedLadder.c
View File

@ -1,95 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Seven node pop order twisted ladder Topology.
*
* The population order fall back to Seven nodes on a twisted ladder.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* 6
* |
* 4 5
* |\ /|
* |/ \|
* 2 3
* | |
* 0---1
*/
/**
* 7 node twisted ladder
*/
/**
* @dot
strict graph twl7 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
{rank=same; 4; 5}
{rank=same; 6}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 4 ;
2 -- 5 ;
3 -- 4 ;
3 -- 5 ;
4 -- 6 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologySevenTwistedLadder[] =
{
0x07,
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, // Node2
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
};

76
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8DoubloonM.c
View File

@ -1,76 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Eight node hydra Topology using "Doubloon/Drachma".
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 8 node hydra doubloon, 4 MCM processors.
*/
/**
* @dot
strict graph doubloon8 {
node [shape="plaintext"];
0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
0 -- 2 ; 1 -- 2 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 6 ;
0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
0 -- 6 ; 1 -- 7 ; 2 -- 7 ; 3 -- 6
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyEightDoubloon[] =
{
0x08,
0x56, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
0x00, 0x00, 0xA5, 0xFF, 0x00, 0x22, 0x00, 0x22, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
0x08, 0x00, 0x08, 0x11, 0xDB, 0xFF, 0x03, 0x33, 0x08, 0x44, 0x00, 0x44, 0x00, 0x66, 0x00, 0x77, // Node 2
0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0xE4, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x66, // Node 4
0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x5A, 0xFF, 0x00, 0x66, 0x00, 0x66, // Node 5
0x80, 0x00, 0x00, 0x00, 0x00, 0x22, 0x00, 0x33, 0x80, 0x44, 0x80, 0x55, 0xBD, 0xFF, 0x30, 0x77, // Node 6
0x00, 0x11, 0x40, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x66, 0x00, 0x66, 0x00, 0x66, 0x4E, 0xFF // Node 7
};

79
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8FullyConnected.c
View File

@ -1,79 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Eight node Fully Connected Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/**
* 8 node fully connected
*/
/**
* @dot
strict graph full8 {
node [shape="plaintext"];
0 -- 1 ; 1 -- 2 ; 2 -- 3 ; 3 -- 4 ; 4 -- 5 ; 5 -- 6 ; 6 -- 7 ;
0 -- 2 ; 1 -- 3 ; 2 -- 4 ; 3 -- 5 ; 4 -- 6 ; 5 -- 7 ;
0 -- 3 ; 1 -- 4 ; 2 -- 5 ; 3 -- 6 ; 4 -- 7 ;
0 -- 4 ; 1 -- 5 ; 2 -- 6 ; 3 -- 7 ;
0 -- 5 ; 1 -- 6 ; 2 -- 7 ;
0 -- 6 ; 1 -- 7 ;
0 -- 7 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyEightFully[] =
{
0x08,
0xFE, 0xFF, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 0
0x00, 0x00, 0xFD, 0xFF, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 1
0x00, 0x00, 0x00, 0x11, 0xFB, 0xFF, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 2
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0xF7, 0xFF, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 3
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0xEF, 0xFF, 0x00, 0x55, 0x00, 0x66, 0x00, 0x77, // Node 4
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0xDF, 0xFF, 0x00, 0x66, 0x00, 0x77, // Node 5
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0xBF, 0xFF, 0x00, 0x77, // Node 6
0x00, 0x00, 0x00, 0x11, 0x00, 0x22, 0x00, 0x33, 0x00, 0x44, 0x00, 0x55, 0x00, 0x66, 0x7F, 0xFF // Node 7
};

96
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8Ladder.c
View File

@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Eight node Ladder Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* 6---7
* | |
* 4---5
* | |
* 2---3
* | |
* 0---1
*/
/**
* 8 node ladder
*/
/**
* @dot
strict graph ladder8 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
{rank=same; 4; 5}
{rank=same; 6; 7}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 4 ;
2 -- 3 ;
3 -- 5 ;
4 -- 5 ;
4 -- 6 ;
5 -- 7 ;
6 -- 7 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyEightStraightLadder[] =
{
0x08,
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, 0x02, 0x22, 0x00, 0x22, // Node0
0x00, 0x00, 0x09, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, 0x00, 0x33, 0x01, 0x33, // Node1
0x18, 0x00, 0x00, 0x00, 0x19, 0xFF, 0x00, 0x33, 0x09, 0x44, 0x00, 0x44, 0x09, 0x44, 0x00, 0x44, // Node2
0x00, 0x11, 0x24, 0x11, 0x00, 0x22, 0x26, 0xFF, 0x00, 0x55, 0x06, 0x55, 0x00, 0x55, 0x06, 0x55, // Node3
0x60, 0x22, 0x00, 0x22, 0x60, 0x22, 0x00, 0x22, 0x64, 0xFF, 0x00, 0x55, 0x24, 0x66, 0x00, 0x66, // Node4
0x00, 0x33, 0x90, 0x33, 0x00, 0x33, 0x90, 0x33, 0x00, 0x44, 0x98, 0xFF, 0x00, 0x77, 0x18, 0x77, // Node5
0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x44, 0x90, 0xFF, 0x00, 0x77, // Node6
0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
};

96
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8TwinFullyFourWays.c
View File

@ -1,96 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Eight node Topology of two fully connected four ways.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* (2 fully connected four ways connected at the 'corners')
*
* 5 - 7
* /| X |
* / 1 - 3
* / / / /
* 4 - 6 /
* | X | /
* 0 - 2-
*/
/**
* 8 node twin fully connected four ways, connected by the MCM internal links.
*/
/**
* @dot
strict graph hydra8 {
node [shape="plaintext"];
subgraph even {
0 -- 2 ; 2 -- 4 ; 4 -- 6 ;
0 -- 4 ; 2 -- 6 ;
0 -- 6 ;
}
subgraph odd {
1 -- 3 ; 3 -- 5 ; 5 -- 7 ;
1 -- 5 ; 3 -- 7 ;
1 -- 7 ;
}
{rank=same; 0; 2; 1; 3}
{rank=same; 4; 6; 5; 7}
0 -- 1 ; 2 -- 3 ; 4 -- 5 ; 6 -- 7 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyEightTwinFullyFourWays[] =
{
0x08,
0x56, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x22, 0x02, 0x44, 0x00, 0x44, 0x02, 0x66, 0x00, 0x66, // Node 0
0x00, 0x00, 0xA9, 0xFF, 0x00, 0x33, 0x01, 0x33, 0x00, 0x55, 0x01, 0x55, 0x00, 0x77, 0x01, 0x77, // Node 1
0x08, 0x00, 0x00, 0x00, 0x59, 0xFF, 0x00, 0x33, 0x08, 0x44, 0x00, 0x44, 0x08, 0x66, 0x00, 0x66, // Node 2
0x00, 0x11, 0x04, 0x11, 0x00, 0x22, 0xA6, 0xFF, 0x00, 0x55, 0x04, 0x55, 0x00, 0x77, 0x04, 0x77, // Node 3
0x20, 0x00, 0x00, 0x00, 0x20, 0x22, 0x00, 0x22, 0x65, 0xFF, 0x00, 0x55, 0x20, 0x66, 0x00, 0x66, // Node 4
0x00, 0x11, 0x10, 0x11, 0x00, 0x33, 0x10, 0x33, 0x00, 0x44, 0x9A, 0xFF, 0x00, 0x77, 0x10, 0x77, // Node 5
0x80, 0x00, 0x00, 0x00, 0x80, 0x22, 0x00, 0x22, 0x80, 0x44, 0x00, 0x44, 0x95, 0xFF, 0x00, 0x77, // Node 6
0x00, 0x11, 0x40, 0x11, 0x00, 0x33, 0x40, 0x33, 0x00, 0x55, 0x40, 0x55, 0x00, 0x66, 0x6A, 0xFF // Node 7
};

95
src/vendorcode/amd/agesa/f14/Proc/HT/htGraph/htGraph8TwistedLadder.c
View File

@ -1,95 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* Eight node twisted ladder Topology.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: HyperTransport
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#include "Porting.h"
#include "htTopologies.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* 6---7
* | |
* 4 5
* |\ /|
* |/ \|
* 2 3
* | |
* 0---1
*/
/**
* 8 node twisted ladder
*/
/**
* @dot
strict graph twl8 {
node [shape="plaintext"];
{rank=same; 0; 1}
{rank=same; 2; 3}
{rank=same; 4; 5}
{rank=same; 6; 7}
0 -- 1 ;
0 -- 2 ;
1 -- 3 ;
2 -- 4 ;
2 -- 5 ;
3 -- 4 ;
3 -- 5 ;
4 -- 6 ;
5 -- 7 ;
6 -- 7 ;
}
@enddot
*
*/
CONST UINT8 ROMDATA amdHtTopologyEightTwistedLadder[] =
{
0x08,
0x06, 0xFF, 0x00, 0x11, 0x02, 0x22, 0x00, 0x12, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, 0x00, 0x22, // Node0
0x00, 0x00, 0x09, 0xFF, 0x00, 0x03, 0x01, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, 0x00, 0x33, // Node1
0x30, 0x00, 0x00, 0x50, 0x31, 0xFF, 0x00, 0x54, 0x21, 0x44, 0x01, 0x55, 0x21, 0x44, 0x01, 0x55, // Node2
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, 0x12, 0x55, // Node3
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x00, 0x32, 0x0C, 0x66, 0x00, 0x36, // Node4
0x80, 0x22, 0x84, 0x33, 0x80, 0x22, 0x84, 0x33, 0x00, 0x23, 0x8C, 0xFF, 0x00, 0x27, 0x0C, 0x77, // Node5
0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x80, 0x44, 0x00, 0x74, 0x90, 0xFF, 0x00, 0x77, // Node6
0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x55, 0x00, 0x65, 0x40, 0x55, 0x00, 0x66, 0x60, 0xFF // Node7
};

218
src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.c
View File

@ -1,218 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mfndi.c
*
* Feature applies Node memory interleaving
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Feat/Ndintlv)
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "mm.h"
#include "mn.h"
#include "mfndi.h"
#include "Ids.h"
#include "Filecode.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
#define _4GB_ (0x10000)
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* Perform a check to see if node interleaving can be enabled on each node.
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
* @return TRUE - Node interleaving can be enabled.
* @return FALSE - Node interleaving cannot be enabled.
*/
BOOLEAN
MemFCheckInterleaveNodes (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
DIE_STRUCT *MCTPtr;
ASSERT (NBPtr != NULL);
MCTPtr = NBPtr->MCTPtr;
if (MCTPtr->NodeMemSize != 0) {
if (!NBPtr->SharedPtr->NodeIntlv.IsValid) {
NBPtr->SharedPtr->NodeIntlv.NodeMemSize = MCTPtr->NodeMemSize;
NBPtr->SharedPtr->NodeIntlv.Dct0MemSize = MCTPtr->DctData[0].Timings.DctMemSize;
NBPtr->SharedPtr->NodeIntlv.IsValid = TRUE;
} else {
if ((NBPtr->SharedPtr->NodeIntlv.NodeMemSize != MCTPtr->NodeMemSize) ||
(NBPtr->SharedPtr->NodeIntlv.Dct0MemSize != MCTPtr->DctData[0].Timings.DctMemSize)) {
return FALSE;
}
}
}
return TRUE;
}
/* -----------------------------------------------------------------------------*/
/**
*
* Applies Node memory interleaving for each node.
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
* @return TRUE - This feature is enabled.
* @return FALSE - This feature is not enabled.
*/
BOOLEAN
MemFInterleaveNodes (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
UINT8 NodeCnt;
UINT8 BitShift;
UINT32 MemSize;
UINT32 Dct0MemSize;
UINT32 NodeSysBase;
UINT32 NodeSysLimit;
UINT32 HoleBase;
UINT32 HoleSize;
UINT32 HoleOffset;
MEM_PARAMETER_STRUCT *RefPtr;
DIE_STRUCT *MCTPtr;
ASSERT (NBPtr != NULL);
RefPtr = NBPtr->RefPtr;
MCTPtr = NBPtr->MCTPtr;
if (RefPtr->GStatus[GsbSoftHole] || RefPtr->GStatus[GsbHWHole]) {
HoleBase = RefPtr->HoleBase;
HoleSize = _4GB_ - HoleBase;
} else {
HoleBase = 0;
HoleSize = 0;
}
NodeCnt = NBPtr->SharedPtr->NodeIntlv.NodeCnt;
Dct0MemSize = NBPtr->SharedPtr->NodeIntlv.Dct0MemSize;
MemSize = NBPtr->SharedPtr->NodeIntlv.NodeMemSize;
BitShift = LibAmdBitScanForward (NodeCnt);
Dct0MemSize <<= BitShift;
if (HoleSize != 0) {
RefPtr->GStatus[GsbHWHole] = TRUE;
HoleOffset = HoleSize;
if (Dct0MemSize >= HoleBase) {
Dct0MemSize += HoleSize;
} else {
HoleOffset += Dct0MemSize;
}
} else {
HoleOffset = 0;
}
MemSize = (MemSize << BitShift) + HoleSize;
MCTPtr->NodeSysBase = 0;
MCTPtr->NodeSysLimit = MemSize - 1;
NBPtr->SetBitField (NBPtr, BFDramIntlvSel, NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel);
NBPtr->SetBitField (NBPtr, BFDramBaseAddr, 0);
NBPtr->SetBitField (NBPtr, BFDramIntlvEn, NodeCnt - 1);
NBPtr->SetBitField (NBPtr, BFDramLimitAddr, (MemSize - 1) >> (27 - 16));
if (HoleSize != 0) {
MCTPtr->Status[SbHWHole] = TRUE;
// DramHoleBase will be set when sync address map to other nodes.
NBPtr->SetBitField (NBPtr, BFDramHoleOffset, HoleOffset >> (23 - 16));
NBPtr->SetBitField (NBPtr, BFDramHoleValid, 1);
}
if ((MCTPtr->DctData[1].Timings.DctMemSize != 0) && (!NBPtr->Ganged)) {
NBPtr->SetBitField (NBPtr, BFDctSelBaseAddr, Dct0MemSize >> (27 - 16));
NBPtr->SetBitField (NBPtr, BFDctSelBaseOffset, Dct0MemSize >> (26 - 16));
}
NodeSysBase = NodeCnt - 1;
NodeSysLimit = ((MemSize - 1)& 0xFFFFFF00) | NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel;
NBPtr->SharedPtr->NodeMap[NBPtr->Node].IsValid = TRUE;
NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysBase = NodeSysBase;
NBPtr->SharedPtr->NodeMap[NBPtr->Node].SysLimit = NodeSysLimit;
NBPtr->SharedPtr->NodeIntlv.NodeIntlvSel++;
return TRUE;
}

80
src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/NDINTLV/mfndi.h
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@ -1,80 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mfndi.h
*
* Feature node interleaving
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem)
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _MFNDI_H_
#define _MFNDI_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
BOOLEAN
MemFInterleaveNodes (
IN OUT MEM_NB_BLOCK *NBPtr
);
#endif /* _MFNDI_H_ */

171
src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.c
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@ -1,171 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mfspr.c
*
* Feature enable online spare
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Feat/Olspare)
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "mm.h"
#include "mn.h"
#include "mfspr.h"
#include "Ids.h"
#include "amdlib.h"
#include "Filecode.h"
#include "GeneralServices.h"
CODE_GROUP (G2_PEI)
RDATA_GROUP (G2_PEI)
#define FILECODE PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* Enable online spare on current node if it is requested.
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
*
* @return TRUE - This feature is enabled.
* @return FALSE - This feature is not enabled.
*/
BOOLEAN
MemFOnlineSpare (
IN OUT MEM_NB_BLOCK *NBPtr
)
{
UINT8 Dct;
UINT8 q;
UINT8 Value8;
BOOLEAN Flag;
BOOLEAN OnlineSprEnabled[MAX_CHANNELS_PER_SOCKET];
MEM_PARAMETER_STRUCT *RefPtr;
DIE_STRUCT *MCTPtr;
ASSERT (NBPtr != NULL);
RefPtr = NBPtr->RefPtr;
Flag = FALSE;
if (RefPtr->EnableOnLineSpareCtl != 0) {
RefPtr->GStatus[GsbEnDIMMSpareNW] = TRUE;
MCTPtr = NBPtr->MCTPtr;
// Check if online spare can be enabled on current node
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
ASSERT (Dct < sizeof (OnlineSprEnabled));
NBPtr->SwitchDCT (NBPtr, Dct);
OnlineSprEnabled[Dct] = FALSE;
if ((MCTPtr->GangedMode == 0) || (MCTPtr->Dct == 0)) {
if (NBPtr->DCTPtr->Timings.DctMemSize != 0) {
// Make sure at least two chip-selects are available
Value8 = LibAmdBitScanReverse (NBPtr->DCTPtr->Timings.CsEnabled);
if (Value8 > LibAmdBitScanForward (NBPtr->DCTPtr->Timings.CsEnabled)) {
OnlineSprEnabled[Dct] = TRUE;
Flag = TRUE;
} else {
PutEventLog (AGESA_ERROR, MEM_ERROR_DIMM_SPARING_NOT_ENABLED, NBPtr->Node, NBPtr->Dct, NBPtr->Channel, 0, &NBPtr->MemPtr->StdHeader);
MCTPtr->ErrStatus[EsbSpareDis] = TRUE;
}
}
}
}
// If we don't have spared rank on any DCT, we don't run the rest part of the code.
if (!Flag) {
return FALSE;
}
MCTPtr->NodeMemSize = 0;
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
NBPtr->SwitchDCT (NBPtr, Dct);
if (OnlineSprEnabled[Dct]) {
// Only run StitchMemory if we need to set a spare rank.
NBPtr->DCTPtr->Timings.DctMemSize = 0;
for (q = 0; q < MAX_CS_PER_CHANNEL; q++) {
NBPtr->SetBitField (NBPtr, BFCSBaseAddr0Reg + q, 0);
}
Flag = NBPtr->StitchMemory (NBPtr);
ASSERT (Flag == TRUE);
} else if ((MCTPtr->GangedMode == 0) && (NBPtr->DCTPtr->Timings.DctMemSize != 0)) {
// Otherwise, need to adjust the memory size on the node.
MCTPtr->NodeMemSize += NBPtr->DCTPtr->Timings.DctMemSize;
MCTPtr->NodeSysLimit = MCTPtr->NodeMemSize - 1;
}
}
return TRUE;
} else {
return FALSE;
}
}

81
src/vendorcode/amd/agesa/f14/Proc/Mem/Feat/OLSPARE/mfspr.h
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@ -1,81 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mfspr.h
*
* Feature enable Online spare
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem)
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _MFSPR_H_
#define _MFSPR_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
BOOLEAN
MemFOnlineSpare (
IN OUT MEM_NB_BLOCK *NBPtr
);
#endif /* _MFSPR_H_ */

234
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.c
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@ -1,234 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mt2.c
*
* Common Technology functions for DDR2
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Tech/DDR2)
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "Ids.h"
#include "AdvancedApi.h"
#include "mm.h"
#include "mn.h"
#include "mu.h"
#include "mt.h"
#include "mt2.h"
#include "mtspd2.h"
#include "mtot2.h"
#include "OptionMemory.h"
#include "PlatformMemoryConfiguration.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
/* features */
#include "mftds.h"
#define FILECODE PROC_MEM_TECH_DDR2_MT2_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* This function Constructs the technology block
*
* @param[in,out] *NBPtr - Pointer to the MEM_NB_BLOCK
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
*
*/
BOOLEAN
MemConstructTechBlock2 (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
)
{
TECHNOLOGY_TYPE *TechTypePtr;
UINT8 Dct;
UINT8 Channel;
UINT8 i;
DIE_STRUCT *MCTPtr;
DCT_STRUCT *DCTPtr;
CH_DEF_STRUCT *ChannelPtr;
UINT8 DimmSlots;
TechTypePtr = (TECHNOLOGY_TYPE *) FindPSOverrideEntry (NBPtr->RefPtr->PlatformMemoryConfiguration, PSO_MEM_TECH, NBPtr->MCTPtr->SocketId, 0);
if (TechTypePtr != NULL) {
// Ensure the platform override value is valid
ASSERT ((*TechTypePtr == DDR3_TECHNOLOGY) || (*TechTypePtr == DDR2_TECHNOLOGY));
if (*TechTypePtr != DDR2_TECHNOLOGY) {
return FALSE;
}
}
TechPtr->NBPtr = NBPtr;
TechPtr->RefPtr = NBPtr->RefPtr;
MCTPtr = NBPtr->MCTPtr;
TechPtr->NBPtr = NBPtr;
TechPtr->RefPtr = NBPtr->RefPtr;
TechPtr->SetDramMode = MemTSetDramMode2;
TechPtr->DimmPresence = MemTDIMMPresence2;
TechPtr->SpdCalcWidth = MemTSPDCalcWidth2;
TechPtr->SpdGetTargetSpeed = MemTSPDGetTargetSpeed2;
TechPtr->AutoCycTiming = MemTAutoCycTiming2;
TechPtr->SpdSetBanks = MemTSPDSetBanks2;
TechPtr->SetDqsEccTmgs = MemTSetDQSEccTmgs;
TechPtr->GetCSIntLvAddr = MemTGetCSIntLvAddr2;
TechPtr->AdjustTwrwr = MemTAdjustTwrwr2;
TechPtr->AdjustTwrrd = MemTAdjustTwrrd2;
TechPtr->GetDimmSpdBuffer = MemTGetDimmSpdBuffer2;
TechPtr->GetLD = MemTGetLD2;
TechPtr->MaxFilterDly = 0;
//
// Map the Logical Dimms on this channel to the SPD that should be used for that logical DIMM.
// The pointers to the DIMM SPD information is as follows (2 Dimm/Ch and 3 Dimm/Ch examples).
//
// DIMM Spd Buffer Current Channel DimmSpdPtr[MAX_DIMMS_PER_CHANNEL] array
// (Number of dimms varies by platform) (Array size is determined in AGESA.H) Dimm operations loop
// on this array only)
// 2 DIMMS PER CHANNEL
//
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
// DimmSpdPtr[2]------->NULL
// DimmSpdPtr[3]------->NULL
//
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
// | DimmSpdPtr[2]------->NULL
// +----DimmSpdPtr[3]
//
// Socket N Channel N Dimm 0 QR DIMM <-----+--------DimmSpdPtr[0]
// Dimm 1 QR DIMM <-----|---+----DimmSpdPtr[1]
// +-- | ---DimmSpdPtr[2]
// +----DimmSpdPtr[3]
//
// 3 DIMMS PER CHANNEL
//
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
// Dimm 1 SR/DR DIMM <--------------DimmSpdPtr[1]
// Dimm 3 SR/DR DIMM <--------------DimmSpdPtr[2]
// DimmSpdPtr[3]------->NULL
//
// Socket N Channel N Dimm 0 SR/DR DIMM <--------------DimmSpdPtr[0]
// Dimm 1 QR DIMM <---------+----DimmSpdPtr[1]
// Dimm 3 SR/DR DIMM <-------- | ---DimmSpdPtr[2]
// +----DimmSpdPtr[3]
//
//
for (Dct = 0; Dct < NBPtr->DctCount; Dct++) {
NBPtr->SwitchDCT (NBPtr, Dct);
DCTPtr = NBPtr->DCTPtr;
for (Channel = 0; Channel < NBPtr->ChannelCount; Channel++) {
NBPtr->SwitchChannel (NBPtr, Channel);
ChannelPtr = NBPtr->ChannelPtr;
ChannelPtr->TechType = DDR2_TECHNOLOGY;
ChannelPtr->MCTPtr = MCTPtr;
ChannelPtr->DCTPtr = DCTPtr;
DimmSlots = GetMaxDimmsPerChannel (NBPtr->RefPtr->PlatformMemoryConfiguration,
MCTPtr->SocketId,
NBPtr->GetSocketRelativeChannel (NBPtr, Dct, Channel)
);
//
// Initialize the SPD pointers for each Dimm
//
for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
ChannelPtr->DimmSpdPtr[i] = NULL;
}
for (i = 0 ; i < DimmSlots; i++) {
ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_DM_BANKS] >> 3) & 0x07) + 1) > 2) {
ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);
}
}
}
}
}
}
return TRUE;
}
/*----------------------------------------------------------------------------
* LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/

126
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mt2.h
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@ -1,126 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mt2.h
*
* Common Technology
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Tech/DDR2)
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _MT2_H_
#define _MT2_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
BOOLEAN
MemConstructTechBlock2 (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN
MemTSetDramMode2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
BOOLEAN
MemTDIMMPresence2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
BOOLEAN
MemTSPDCalcWidth2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
BOOLEAN
MemTSPDGetTargetSpeed2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
BOOLEAN
MemTAutoCycTiming2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
BOOLEAN
MemTSPDSetBanks2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
VOID
MemTGetCSIntLvAddr2 (
IN UINT8 BankEnc,
OUT UINT8 *LowBit,
OUT UINT8 *HiBit
);
BOOLEAN
MemTGetDimmSpdBuffer2 (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT UINT8 **SpdBuffer,
IN UINT8 Dimm
);
#endif /* _MT2_H_ */

164
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@ -1,164 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mtot2.c
*
* Technology Non-SPD Timings for DDR2
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Tech/DDR2)
* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
/*
*----------------------------------------------------------------------------
* MODULES USED
*
*----------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "mm.h"
#include "mn.h"
#include "mu.h"
#include "mt.h"
#include "mtot2.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_MEM_TECH_DDR2_MTOT2_FILECODE
/*----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS AND STRUCTURES
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* PROTOTYPES OF LOCAL FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* EXPORTED FUNCTIONS
*
*----------------------------------------------------------------------------
*/
/* -----------------------------------------------------------------------------*/
/**
*
* This function adjusts the Twrwr value for DDR2.
*
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
*
*/
VOID
MemTAdjustTwrwr2 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
DCT_STRUCT *DCTPtr;
DCTPtr = TechPtr->NBPtr->DCTPtr;
// For DDR2, 1 clock has encoded value of 0.
// Need to transfer clk value to encoded value.
if (DCTPtr->Timings.Twrwr >= 1) {
DCTPtr->Timings.Twrwr -= 1;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* This function adjusts the Twrrd value for DDR2.
*
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
*
*/
VOID
MemTAdjustTwrrd2 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
DCT_STRUCT *DCTPtr;
DCTPtr = TechPtr->NBPtr->DCTPtr;
// For DDR2, 1 clock has encoded value of 0.
// Need to transfer clk value to encoded value.
if (DCTPtr->Timings.Twrrd >= 1) {
DCTPtr->Timings.Twrrd -= 1;
}
}
/* -----------------------------------------------------------------------------*/
/**
*
* This function gets the LD value for DDR2
*
* @param[in,out] *TechPtr - Pointer to the MEM_TECH_BLOCK
*
* @return value of LD
*/
INT8
MemTGetLD2 (
IN OUT MEM_TECH_BLOCK *TechPtr
)
{
INT8 LD;
// For DDR2, LD is always one clock (For DDR2, Tcwl is always Tcl minus 1).
LD = 1;
return LD;
}

90
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtot2.h
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@ -1,90 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mtot2.h
*
* Technology Non-SPD timings for DDR2
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Tech/DDR2)
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _MTOT2_H_
#define _MTOT2_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
VOID
MemTAdjustTwrwr2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
VOID
MemTAdjustTwrrd2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
INT8
MemTGetLD2 (
IN OUT MEM_TECH_BLOCK *TechPtr
);
#endif /* _MTOT2_H_ */

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src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.c
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184
src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR2/mtspd2.h
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@ -1,184 +0,0 @@
/* $NoKeywords:$ */
/**
* @file
*
* mtspd2.h
*
* Technology SPD support for DDR2
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: (Mem/Tech/DDR2)
* @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
*
**/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _MTSPD2_H_
#define _MTSPD2_H_
/*----------------------------------------------------------------------------
* Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
*
*----------------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------------
* DEFINITIONS AND MACROS
*
*-----------------------------------------------------------------------------
*/
/*===============================================================================
* Jedec DDR II
*===============================================================================
*/
#define SPD_TYPE 2 /* SPD byte read location */
#define JED_DDR_SDRAM 7 /* Jedec defined bit field */
#define JED_DDR2_SDRAM 8 /* Jedec defined bit field */
#define SPD_DIMM_TYPE 20
#define SPD_ATTRIB 21
#define JED_DIF_CK_MSK 0x20 /* Differential Clock Input */
#define JED_REG_ADC_MSK 0x11 /* Registered Address/Control */
#define JED_PROBE_MSK 0x40 /* Analysis Probe installed */
#define JED_SODIMM 0x04 /* SO-DIMM */
#define SPD_DEV_ATTRIB 22
#define SPD_EDC_TYPE 11
#define JED_ECC 2
#define JED_ADRC_PAR 4
#define SPD_ROW_SZ 3
#define SPD_COL_SZ 4
#define SPD_L_BANKS 17 /* number of [logical] banks on each device */
#define SPD_DM_BANKS 5 /* number of physical banks on dimm */
#define SP_DPL_BIT 4 /* Dram package bit */
#define SPD_BANK_SZ 31 /* capacity of physical bank */
#define SPD_DEV_WIDTH 13
#define SPD_CAS_LAT 18
#define SPD_TRP 27
#define SPD_TRRD 28
#define SPD_TRCD 29
#define SPD_TRAS 30
#define SPD_TWR 36
#define SPD_TWTR 37
#define SPD_TRTP 38
#define SPD_TRC 41
#define SPD_TRFC 42
#define SPD_CHECKSUM 63
#define SPD_MAN_DATE_YR 93 /* Module Manufacturing Year (BCD) */
#define SPD_MAN_DATE_WK 94 /* Module Manufacturing Week (BCD) */
/*-----------------------------
* Jedec DDR II related equates
*-----------------------------
*/
#define M_YEAR_06 0x06 /* Manufacturing Year BCD encoding of 2006 - 06d */
#define M_WEEK_24 0x24 /* Manufacturing Week BCD encoding of June - 24d */
#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T */
#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T */
#define K_MIN 1 /* k loop constraint. 1=200 MHz */
#define K_MAX 5 /* k loop constraint. 5=533 MHz */
#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T */
#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time) */
#define BIAS_TCL_T 1
#define BIAS_TRP_T 3 /* bias to convert bus clocks to bit field value */
#define BIAS_TRRD_T 2
#define BIAS_TRCD_T 3
#define BIAS_TRAS_T 3
#define BIAS_TRC_T 11
#define BIAS_TRTP_T 1
#define BIAS_TWR_T 3
#define BIAS_TWTR_T 0
#define BIAS_TFAW_T 7
#define MIN_TRP_T 3 /* min programmable value in busclocks */
#define MAX_TRP_T 6 /* max programmable value in busclocks */
#define MIN_TRRD_T 2
#define MAX_TRRD_T 5
#define MIN_TRCD_T 3
#define MAX_TRCD_T 6
#define MIN_TRAS_T 5
#define MAX_TRAS_T 18
#define MIN_TRC_T 11
#define MAX_TRC_T 26
#define MIN_TRTP_T 2
#define MAX_TRTP_T 4
#define MIN_TWR_T 3
#define MAX_TWR_T 6
#define MIN_TWTR_T 1
#define MAX_TWTR_T 3
/* DDR2-1066 support */
#define BIAS_TRCD_T_1066 5
#define BIAS_TRAS_T_1066 15
#define BIAS_TRRD_T_1066 4
#define BIAS_TWR_T_1066 4
#define BIAS_TRP_T_1066 5
#define BIAS_TWTR_T_1066 4
#define MIN_TRCD_T_1066 5
#define MAX_TRCD_T_1066 12
#define MIN_TRAS_T_1066 15
#define MAX_TRAS_T_1066 30
#define MIN_TRC_T_1066 11
#define MAX_TRC_T_1066 42
#define MIN_TRRD_T_1066 4
#define MAX_TRRD_T_1066 7
#define MIN_TWR_T_1066 5
#define MAX_TWR_T_1066 8
#define MIN_TRP_T_1066 5
#define MAX_TRP_T_1066 12
#define MIN_TWTR_T_1066 4
#define MAX_TWTR_T_1066 7
/*----------------------------------------------------------------------------
* TYPEDEFS, STRUCTURES, ENUMS
*
*----------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------
* FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
#endif /* _MTSPD2_H_ */