diff --git a/Documentation/gfx/display-panel.md b/Documentation/gfx/display-panel.md new file mode 100644 index 0000000000..3bab0896fd --- /dev/null +++ b/Documentation/gfx/display-panel.md @@ -0,0 +1,64 @@ +Display Panel Specifics +======================= + +Timing Parameters +----------------- + +From the binary file `edid` in the sys filesystem on Linux, the panel can be +identified. The exact path may differ slightly. Here is an example: + +```sh +$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid +@0 5 +LG Display +LP140WF3-SPD1 +``` + +To figure out the timing parameters, refer to the [Intel Programmer's Reference +Manuals](https://01.org/linuxgraphics/documentation/hardware-specification-prms) +and try to find the datasheet of the panel using the information from `edid`. +In the example above, you would search for `LP140WF3-SPD1`. Find a table listing +the power sequence timing parameters, which are usually named T[N] and also +referenced in Intel's respective registers listing. You need the values for +`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`: + +```eval_rst ++-----------------------------+---------------------------------------+-----+ +| Intel docs | devicetree.cb | eDP | ++-----------------------------+---------------------------------------+-----+ +| Power up delay | `gpu_panel_power_up_delay` | T3 | ++-----------------------------+---------------------------------------+-----+ +| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | ++-----------------------------+---------------------------------------+-----+ +| Power Down delay | `gpu_panel_power_down_delay` | T10 | ++-----------------------------+---------------------------------------+-----+ +| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | ++-----------------------------+---------------------------------------+-----+ +| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | ++-----------------------------+---------------------------------------+-----+ +``` + +Intel GPU Tools and VBT +----------------------- + +The Intel GPU tools are in a package called either `intel-gpu-tools` or +`igt-gpu-tools` in most distributions of Linux-based operating systems. +In the coreboot `util/` directory, you can find `intelvbttool`. + +From a running system, you can dump the register values directly: +```sh +$ intel_reg dump --all | grep PCH_PP + PCH_PP_STATUS (0x000c7200): 0x80000008 + PCH_PP_CONTROL (0x000c7204): 0x00000007 + PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001 + PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001 + PCH_PP_DIVISOR (0x000c7210): 0x0004af06 +``` + +You can obtain the timing values from a VBT (Video BIOS Table), which you can +dump from a vendor UEFI image: +```sh +$ intel_vbt_decode data.vbt | grep T3 + Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000 + T3 optimization: no +``` diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md index c50761a14e..c000f27d60 100644 --- a/Documentation/gfx/libgfxinit.md +++ b/Documentation/gfx/libgfxinit.md @@ -55,6 +55,9 @@ follows: GMA: Per Board Configuration ---------------------------- +In order to set up the display panel, see the +[display panel-specific documentation](/gfx/display-panel.md). + There are a few Kconfig symbols to consider. To indicate that a board can initialize graphics through *libgfxinit*: diff --git a/Documentation/index.md b/Documentation/index.md index 6dbbf4d91f..76faffa497 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -173,6 +173,7 @@ Contents: * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md) * [GPIO toggling in ACPI AML](acpi/gpio.md) * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md) +* [Display panel-specific documentation](gfx/display-panel.md) * [Architecture-specific documentation](arch/index.md) * [Northbridge-specific documentation](northbridge/index.md) * [System on Chip-specific documentation](soc/index.md) diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md new file mode 100644 index 0000000000..0dfa653937 --- /dev/null +++ b/Documentation/mainboard/hp/z220_sff.md @@ -0,0 +1,70 @@ +# HP Z220 SFF Workstation + +This page describes how to run coreboot on the [HP Z220 SFF Workstation] desktop +from [HP]. + +## TODO + +The following things are still missing from this coreboot port: + +- Extended HWM reporting +- Advanced LED control +- Advanced power configuration in S3 + +## Flashing coreboot + +```eval_rst ++---------------------+-------------+ +| Type | Value | ++=====================+=============+ +| Socketed flash | no | ++---------------------+-------------+ +| Model | N25Q128..3E | ++---------------------+-------------+ +| Size | 16 MiB | ++---------------------+-------------+ +| In circuit flashing | yes | ++---------------------+-------------+ +| Package | SOIC-16 | ++---------------------+-------------+ +| Write protection | No | ++---------------------+-------------+ +| Dual BIOS feature | No | ++---------------------+-------------+ +| Internal flashing | yes | ++---------------------+-------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. + +### External programming + +External programming with an SPI adapter and [flashrom] does work, but it powers the +whole southbridge complex. You need to supply enough current through the programming adapter. + +If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, +as otherwise there's not enough space near the flash. + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` | ++------------------+--------------------------------------------------+ +| Southbridge | bd82x6x | ++------------------+--------------------------------------------------+ +| CPU | model_206ax | ++------------------+--------------------------------------------------+ +| SuperIO | :doc:`../../superio/nuvoton/npcd378` | ++------------------+--------------------------------------------------+ +| EC | | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel ME | ++------------------+--------------------------------------------------+ +``` + +[HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950 +[HP]: https://www.hp.com/ +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index f63ef763fb..03af2c338c 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ The boards in this section are not real mainboards, but emulators. ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) +- [Z220 Workstation SFF](hp/z220_sff.md) ### EliteBook series diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md new file mode 100755 index 0000000000..dc3de13ffe --- /dev/null +++ b/Documentation/soc/amd/family17h.md @@ -0,0 +1,224 @@ +# AMD Family 17h in coreboot + +## Abstract + +Beginning with Family 17h products (a.k.a. “Zen” cores), AMD +changed their paradigm for initializing the system and this requires +major modifications to the execution flow of coreboot. This file +discusses the new boot flow, and challenges, and the tradeoffs of the +initial port into coreboot. + +## Introduction + +Family 17h products are x86-based designs. This documentation assumes +familiarity with x86, its reset state and its early initialization +requirements. + +To the extent necessary, the role of the Platform Security Processor +(a.k.a. PSP) in system initialization is addressed here. AMD has +historically required an NDA for access to the PSP +specification1. coreboot relies on util/amdfwtool to build +the structures and add various other firmware to the final image. The +Family 17h PSP design guide adds a new BIOS Directory Table, similar to +the PSP Directory Table. + +Support in coreboot for modern AMD products is based on AMD’s +reference code: AMD Generic Encapsulated Software Architecture +(AGESATM). AGESA contains the technology for enabling DRAM, +configuring proprietary core logic, assistance with generating ACPI +tables, and other features. + +AGESA for products earlier than Family 17h is known as v5 or +Arch20082. Also note that coreboot currently contains both +open source AGESA and closed source implementations (binaryPI) compiled +from AGESA. + +The first AMD Family 17h device ported to coreboot is codenamed +“Picasso”3, and will be added to soc/amd/picasso. + +## Additional Definitions + +* PSP, Platform Security Processor: Onboard ARM processor that runs +alongside the main x86 processor; may be viewed as analogous to the +IntelR Management Engine +* FCH, Fusion Control Hub, the logical southbridge within the SOC +* ABL - AGESA Bootloader - Processor initialization code that runs on +the PSP +* PSP Directory Table - A structured list of pointers to PSP firmware +and other controller binaries +* BIOS Directory Table - A structured list of pointers to BIOS +related firmware images +* Embedded Firmware Structure - Signature and pointers used by the +PSP to locate the PSP Directory Table and BIOS Directory Table; these +items are generated during coreboot build and are located in the SPI ROM +* Verstage - The code to verify the firmware contained in the +writable section of the SPI ROM +* APCB - AMD PSP Customization Block - A binary containing PSP and +system configuration preferences (analogous to v5 BUILDOPT_ options), +and generated by APCBTool to be added to coreboot/utils later +* APOB - AGESA PSP Output Buffer - A buffer in main memory for +storing AGESA BootLoader output. There are no plans for this to be +parsed by coreboot + +## Problem Statements + +AMD has ported early AGESA features to the PSP, which now discovers, +enables and trains DRAM. Unlike any other x86 device in coreboot, a +Picasso system has DRAM online prior to the first instruction fetch. + +Cache-as-RAM (CAR) is no longer a supportable feature in AMD hardware. +Early code expecting CAR behavior must account for writes +escaping the L2 cache and going to DRAM. + +Without any practical need for CAR, or DRAM initialization, coreboot +should arguably skip bootblock and romstage, and possibly use ramstage +as the BIOS image. This approach presents a number of challenges: + +* At the entry of ramstage, x86 processors are in flat protected +mode. Picasso’s initial state is nearly identical to any other x86 +at reset, except its CS shadow register’s base and limit put its +execution within DRAM, not at 0xfffffff0. Picasso requires initial +programming and entry into protected mode prior to ramstage. +* coreboot expects cbmem initialization during romstage. + +AGESA supporting Picasso is now at v9. Unlike Arch2008, which defines +granular entry points for easy inclusion to a legacy BIOS, v9 is +rewritten for compilation into a UEFI. The source follows UEFI +standards, i.e. assumes the presence of UEFI phases, implements +dependency expressions, much functionality is rewritten as libraries, +etc. It would, in no way, fit into the v5 model used in coreboot. + +* For the foreseeable future, AGESA source will distributed only +under NDA. + +## Basic Pre-x86 Boot Flow + +The following steps occur prior to x86 processor operation. + +* System power on +* PSP executes immutable on-chip boot ROM +* PSP locates the Embedded Firmware Table and PSP Directory Table in +the SPI ROM +* PSP verifies and executes the PSP off-chip bootloader +* ChromeOS systems: + * Off-chip bootloader attempts to locate verstage via the RO BIOS +Directory Table + * If verstage is not found, booting continues with ABLs below + * Verstage initializes, setting up GPIOs, UART if needed, +communication path to the EC, and the SPI controller for direct access +to the flash device. + * Verstage verifies the RW sections (as is typically performed by +the main processor) + * Verstage locates the Embedded Firmware Directory within the +verified FMAP section and passes a pointer to the PSP bootloader. If +the verification fails, it passes a pointer to the RO header to the +bootloader. +* PSP parses the PSP Directory Table to find the ABLs and executes +them +* An ABL parses the APCB for system configuration preferences +* An ABL initializes system main memory, locates the compressed BIOS +image in the SPI ROM, and decompresses it into DRAM +* An ABL writes the APOB to DRAM for consumption by the x86-based +AGESA +* PSP releases the x86 processor from reset. The x86 core fetches +and executes instructions from the reset vector + +## Picasso Reset Vector and First Instructions + +As mentioned above, prior to releasing the x86 main core from reset, +the PSP decompresses a BIOS image into DRAM. The PSP uses a specific +BIOS Directory Table entry type to determine the source address (in +flash), the destination address (in DRAM), and the destination size. +The decompressed image is at the top of the destination region. The +PSP then + +Calculates the x86 reset vector as + + reset_vector = dest_addr + dest_size - 0x10 + +Sets x86 CS descriptor shadow register to + + base = dest_addr + dest_size - 0x10000 + limit = 0xffff + +Like all x86 devices, the main core is allowed to begin executing +instructions with + + CS:IP = 0xf000:0xfff0 + +For example, assume the BIOS Directory Table indicates + + destination = 0x9b00000 + size = 0x300000 + +… then the BIOS image is placed at the topmost position the region +0x9b00000-0x9dfffff and + + reset_vector = 0x9dffff0 + CS_shdw_base = 0x9df0000 + CS:IP = 0xf000:0xfff0 + +Although the x86 behaves as though it began executing at 0xfffffff0 +i.e. 0xf000:0xfff0, the initial GDT load must use the physical address +of the table and not the typical CS-centric address. And, the first +jump to protected mode must jump to the physical address in DRAM. Any +code that is position-dependent must be linked to run at the final +destination. + +## Initial coreboot Implementation + +Supporting Picasso doesn’t fit well with many of the coreboot +assumptions. Initial porting shall attempt to fit within existing +coreboot paradigms and make minimal changes to common code. + +### CAR and bootblock + +The coreboot bootblock contains features Picasso doesn’t require or +can’t use, and is assumed to execute in an unusable location. +Picasso’s requirement for bootblock in coreboot will be eliminated. + +### Hybrid romstage + +Picasso’s x86 reset state doesn’t meet the coreboot expectations +for jumping directly to ramstage. The primary feature of romstage is +also not needed, however there are other important features that are +typically in romstage that Picasso does need. + +The romstage architecture is designed around the presence of CAR. +Several features implement ROMSTAGE_CBMEM_INIT_HOOK, expecting to move +data from CAR to cbmem. The hybrid romstage consumes DRAM for the +purpose of implementing the expected CAR storage. This region as well +as the DRAM where romstage is decompressed must be reserved and +unavailable to the OS. + +The initial Picasso port implements a hybrid romstage that contains the +first instruction fetched at the reset vector. It minimally configures +flat protected mode, initializes cbmem, then loads the next stage. +Future work will consider breaking the dependencies mentioned above +and/or potentially loading ramstage directly from the PSP. + +## AGESA v9 on Picasso + +Due to the current inability to publish AGESA source, a pre-built +binary solution remains a requirement. The rewrite from v5 to v9 for +direct inclusion into UEFI source makes modifying it for conforming to +the existing v5 interface impractical. + +Given the UEFI nature of modern AGESA, and the existing open source +work from Intel, Picasso shall support AGESA via an FSP-like prebuilt +image. The Intel Firmware Support Package4 combines +reference code with EDK II source to create a modular image with +discoverable entry points. coreboot source already contains knowledge +of FSP, how to parse it, integrate it, and how to communicate with it. + +## Footnotes + +1. “AMD Platform Security Processor BIOS Architecture Design Guide +for AMD Family 17h Processors” (PID #55758) and “AMD Platform +Security Processor BIOS Architecture Design Guide” (PID #54267) for +earlier products +2. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) +3. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso) +4. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html) + diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md new file mode 100644 index 0000000000..7945b488f5 --- /dev/null +++ b/Documentation/soc/amd/index.md @@ -0,0 +1,8 @@ +# AMD SOC-specific documentation + +This section contains documentation about coreboot on specific AMD SOCs. + +## Technology + +- [Family 17h](family17h.md) + diff --git a/Documentation/soc/index.md b/Documentation/soc/index.md index 04e2b2f2eb..fccddbd025 100644 --- a/Documentation/soc/index.md +++ b/Documentation/soc/index.md @@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific SOCs. ## Vendor +- [AMD](amd/index.md) - [Cavium](cavium/index.md) - [Intel](intel/index.md) diff --git a/Makefile.inc b/Makefile.inc index d4f7597e82..14cd50c79d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1058,7 +1058,14 @@ ifneq ($(FIT_ENTRY),) FIT_OPTIONS += -q $(FIT_ENTRY) endif -$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) +ifeq ($(CONFIG_HAVE_RAMSTAGE),y) +RAMSTAGE=$(objcbfs)/ramstage.elf +else +RAMSTAGE= +endif + +$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE) + @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty # file (filled with \377 = 0xff) and copy the CBFS image over it. @@ -1128,8 +1135,8 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 -cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage -$(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf +cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage +$(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) $(CONFIG_CBFS_PREFIX)/ramstage-type := stage $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG) diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral index e305fb6700..23bf54e811 100644 --- a/payloads/libpayload/configs/config.mistral +++ b/payloads/libpayload/configs/config.mistral @@ -3,3 +3,6 @@ CONFIG_LP_ARCH_ARM64=y CONFIG_LP_TIMER_ARM64_ARCH=y CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_QCS405_SERIAL_CONSOLE=y +CONFIG_LP_USB=y +CONFIG_LP_USB_EHCI=y +CONFIG_LP_USB_XHCI=y diff --git a/payloads/libpayload/drivers/i8042/i8042.h b/payloads/libpayload/drivers/i8042/i8042.h index e864ac9263..643167ef40 100644 --- a/payloads/libpayload/drivers/i8042/i8042.h +++ b/payloads/libpayload/drivers/i8042/i8042.h @@ -63,7 +63,6 @@ #define I8042_KBCMD_EN 0xf4 #define I8042_KBCMD_DEFAULT_DIS 0xf5 #define I8042_KBCMD_SET_DEFAULT 0xf6 -#define I8042_KBCMD_ACK 0xfa #define I8042_KBCMD_RESEND 0xfe #define I8042_KBCMD_RESET 0xff diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 240385ce6d..3e5f988c48 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -172,7 +172,7 @@ static unsigned char keyboard_cmd(unsigned char cmd) { i8042_write_data(cmd); - return i8042_wait_read_ps2() == I8042_KBCMD_ACK; + return i8042_wait_read_ps2() == 0xfa; } int keyboard_havechar(void) @@ -317,42 +317,27 @@ void keyboard_init(void) /* Enable first PS/2 port */ i8042_cmd(I8042_CMD_EN_KB); - /* Reset keyboard and self test (keyboard side) */ - ret = keyboard_cmd(I8042_KBCMD_RESET); - if (!ret) { - printf("ERROR: Keyboard reset failed!\n"); - return; - } - /* Set scancode set 1 */ ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard set scancode failed!\n"); + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; - } ret = keyboard_cmd(I8042_SCANCODE_SET_1); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard scancode set#1 failed!\n"); + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; - } /* * Set default parameters. * Fix for broken QEMU ps/2 make scancodes. */ ret = keyboard_cmd(0xf6); - if (!ret) { - printf("ERROR: Keyboard set default params failed!\n"); + if (!ret) return; - } /* Enable scanning */ ret = keyboard_cmd(I8042_KBCMD_EN); - if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) { - printf("ERROR: Keyboard enable scanning failed!\n"); + if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) return; - } console_add_input_driver(&cons); } diff --git a/src/Kconfig b/src/Kconfig index d30aa99f06..5d74d671b2 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -129,6 +129,7 @@ config STATIC_OPTION_TABLE config COMPRESS_RAMSTAGE bool "Compress ramstage with LZMA" + depends on HAVE_RAMSTAGE # Default value set at the end of the file help Compress ramstage to save memory in the flash image. Note @@ -137,7 +138,7 @@ config COMPRESS_RAMSTAGE config COMPRESS_PRERAM_STAGES bool "Compress romstage and verstage with LZ4" - depends on !ARCH_X86 + depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE) # Default value set at the end of the file help Compress romstage and (if it exists) verstage with LZ4 to save flash @@ -148,6 +149,7 @@ config COMPRESS_PRERAM_STAGES config COMPRESS_BOOTBLOCK bool + depends on HAVE_BOOTBLOCK help This option can be used to compress the bootblock with LZ4 and attach a small self-decompression stub to its front. This can drastically @@ -234,6 +236,7 @@ config NO_RELOCATABLE_RAMSTAGE config RELOCATABLE_RAMSTAGE bool + depends on HAVE_RAMSTAGE default !NO_RELOCATABLE_RAMSTAGE select RELOCATABLE_MODULES help @@ -277,10 +280,13 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. +config HAVE_RAMPAYLOAD + bool + config RAMPAYLOAD bool "Enable coreboot flow without executing ramstage" default n - depends on ARCH_X86 + depends on HAVE_RAMPAYLOAD help If this option is enabled, coreboot flow will skip ramstage loading and execution of ramstage to load payload. @@ -1188,3 +1194,26 @@ config BOOTSPLASH_FILE config CBFS_SIZE default ROM_SIZE + +config HAVE_BOOTBLOCK + bool + default y + +config HAVE_VERSTAGE + bool + depends on VBOOT_SEPARATE_VERSTAGE + default y + +config HAVE_ROMSTAGE + bool + default y + +config HAVE_POSTCAR + bool + depends on POSTCAR_STAGE + default y + +config HAVE_RAMSTAGE + bool + default n if RAMPAYLOAD + default y diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 7e518d8c93..025b933dba 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -336,13 +336,6 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S -smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c -smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S -smm-y += memcpy.c -smm-y += memmove.c -smm-y += memset.c -smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c - ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove.c @@ -379,11 +372,6 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c endif endif # CONFIG_GENERATE_ACPI_TABLES -ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) -smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c -endif -endif ramstage-libs ?= @@ -408,3 +396,16 @@ else endif endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 + +smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c +smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S +smm-y += memcpy.c +smm-y += memmove.c +smm-y += memset.c +smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c + +ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) +ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),) +smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c +endif +endif diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e283f4da31..74cd25a858 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -514,6 +514,63 @@ void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, acpigen_pop_len(); } +/* + * Generate ACPI AML code for IndexField + * Arg0: region name + * Arg1: Pointer to struct fieldlist. + * Arg2: no. of entries in Arg1 + * Arg3: flags which indicate filed access type, lock rule & update rule. + * Example with fieldlist + * struct fieldlist l[] = { + * FIELDLIST_OFFSET(0x84), + * FIELDLIST_NAMESTR("PMCS", 2), + * }; + * acpigen_write_field("IDX", "DATA" l, ARRAY_SIZE(l), FIELD_ANYACC | + * FIELD_NOLOCK | + * FIELD_PRESERVE); + * Output: + * IndexField (IDX, DATA, AnyAcc, NoLock, Preserve) + * { + * Offset (0x84), + * PMCS, 2 + * } + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags) +{ + uint16_t i; + uint32_t current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(INDEX_FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(idx); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(data); + /* Field Flag */ + acpigen_emit_byte(flags); + + for (i = 0; i < count; i++) { + switch (l[i].type) { + case NAME_STRING: + acpigen_write_field_name(l[i].name, l[i].bits); + current_bit_pos += l[i].bits; + break; + case OFFSET: + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + break; + default: + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" + , __func__, l[i].type); + break; + } + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6114667c6c..db003fe113 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -420,6 +420,12 @@ void acpigen_write_opregion(struct opregion *opreg); */ void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, uint8_t flags); +/* + * Generate ACPI AML code for IndexField + * This function takes input index name, data name, fieldlist, count & flags. + */ +void acpigen_write_indexfield(const char *idx, const char *data, + struct fieldlist *l, size_t count, uint8_t flags); int get_cst_entries(acpi_cstate_t **); diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index e5d0ceab4d..732b767bf6 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -154,8 +154,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) finalize_load(rsl.params, pcf->stack); - if (!CONFIG(NO_STAGE_CACHE)) - stage_cache_add(STAGE_POSTCAR, prog); + stage_cache_add(STAGE_POSTCAR, prog); } void run_postcar_phase(struct postcar_frame *pcf) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index bf627f280f..54c2b09c4a 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -372,6 +372,11 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm, dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; smbios_fill_dimm_part_number((char *)dimm->module_part_number, t); + /* Voltage Levels */ + t->configured_voltage = dimm->vdd_voltage; + t->minimum_voltage = dimm->vdd_voltage; + t->maximum_voltage = dimm->vdd_voltage; + /* Synchronous = 1 */ t->type_detail = 0x0080; /* no handle for error information */ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 535ba3394c..2236c95b8f 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -19,6 +19,7 @@ #define CBMEM_ID_ACPI 0x41435049 #define CBMEM_ID_ACPI_GNVS 0x474e5653 +#define CBMEM_ID_ACPI_UCSI 0x55435349 #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E @@ -82,6 +83,7 @@ #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ { CBMEM_ID_ACPI_GNVS, "ACPI GNVS " }, \ + { CBMEM_ID_ACPI_UCSI, "ACPI UCSI " }, \ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ diff --git a/src/console/die.c b/src/console/die.c index 513d1c4097..3a17126264 100644 --- a/src/console/die.c +++ b/src/console/die.c @@ -30,17 +30,15 @@ __weak void die_notify(void) } /* Report a fatal error */ -void __noreturn die(const char *msg) +void __noreturn die(const char *fmt, ...) { - printk(BIOS_EMERG, "%s", msg); + va_list args; + + va_start(args, fmt); + vprintk(BIOS_EMERG, fmt, args); + va_end(args); + die_notify(); halt(); } - -/* Report a fatal error with a post code */ -void __noreturn die_with_post_code(uint8_t value, const char *msg) -{ - post_code(value); - die(msg); -} #endif diff --git a/src/console/printk.c b/src/console/printk.c index 09522158a7..8606bbb5c9 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -45,7 +45,7 @@ static void wrap_putchar_cbmemc(unsigned char byte, void *data) __cbmemc_tx_byte(byte); } -int vprintk(int msg_level, const char *fmt, va_list args) +int do_vprintk(int msg_level, const char *fmt, va_list args) { int i, log_this; @@ -91,7 +91,7 @@ int do_printk(int msg_level, const char *fmt, ...) int i; va_start(args, fmt); - i = vprintk(msg_level, fmt, args); + i = do_vprintk(msg_level, fmt, args); va_end(args); return i; diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 3e8a6648f4..65c092133f 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -17,23 +17,27 @@ SIPI_RMOD=$(SIPI_ELF).rmod SIPI_BIN=$(SIPI_ELF:.elf=) SIPI_DOTO=$(SIPI_ELF:.elf=.o) -ifeq ($(CONFIG_PARALLEL_MP),y) -ramstage-srcs += $(SIPI_BIN).manual -endif -rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S - -$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-ramstage-y),src/cpu/x86/sipi_vector.S) - $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ - -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) +ifeq ($(CONFIG_HAVE_RAMSTAGE),y) +TARGET_STAGE=ramstage +else ifeq ($(CONFIG_RAMPAYLOAD),y) +TARGET_STAGE=postcar else -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) +$(error Halting the build due to unknown TARGET_STAGE select) endif +ifeq ($(CONFIG_PARALLEL_MP),y) +$(TARGET_STAGE)-srcs += $(SIPI_BIN).manual +endif +rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S + +$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) + $(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ + +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) + $(SIPI_BIN): $(SIPI_RMOD) - $(OBJCOPY_ramstage) -O binary $< $@ + $(OBJCOPY_$(TARGET_STAGE)) -O binary $< $@ -$(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) +$(call src-to-obj,$(TARGET_STAGE),$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 93f3b59d4b..10877b9482 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -21,6 +21,7 @@ verstage-y += fsp_util.c verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c bootblock-y += bootblock.c +bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c romstage-y += car.c @@ -42,8 +43,6 @@ ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include -cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc - postcar-y += stage_cache.c ifneq ($(CONFIG_SKIP_FSP_CAR),y) postcar-y += temp_ram_exit.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.S similarity index 93% rename from src/drivers/intel/fsp1_1/cache_as_ram.inc rename to src/drivers/intel/fsp1_1/cache_as_ram.S index 493dbc8d04..3460b9da34 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -5,6 +5,7 @@ * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018-2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,6 +17,8 @@ * GNU General Public License for more details. */ +#include + /* * Replacement for cache_as_ram.inc when using the FSP binary. This code * locates the FSP binary, initializes the cache as RAM and performs the @@ -24,8 +27,10 @@ * performs the final stage of initialization. */ -/* I/O delay between post codes on failure */ -#define LHLT_DELAY 0x50000 +#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: /* * Per FSP1.1 specs, following registers are preserved: * EBX, EDI, ESI, EBP, MM0, MM1 @@ -129,10 +134,9 @@ CAR_init_done: /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp - subl $4, %esp + subl $8, %esp - /* Push BIST and initial timestamp on the stack */ - pushl %ebx /* bist */ + /* Push initial timestamp on the stack */ movd %mm1, %eax pushl %eax /* tsc[63:32] */ movd %mm0, %eax @@ -141,12 +145,10 @@ CAR_init_done: before_romstage: post_code(0x2A) - /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) - in cpu/intel/car/romstage.c */ - call bootblock_c_entry_bist + /* Call bootblock_c_entry(uint64_t base_timestamp) */ + call bootblock_c_entry - movb $0x69, %ah - jmp .Lhlt + /* Never reached */ halt1: /* diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index dd17664036..67ed099695 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -101,18 +101,6 @@ void mainboard_romstage_entry(unsigned long bist) * is still enabled. We can directly access work buffer here. */ struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); - if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { - /* Call into pre-console init code then initialize console. */ - car_soc_pre_console_init(); - car_mainboard_pre_console_init(); - console_init(); - - display_mtrrs(); - - car_soc_post_console_init(); - car_mainboard_post_console_init(); - } - if (prog_locate(&fsp)) die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); @@ -125,19 +113,3 @@ void mainboard_romstage_entry(unsigned long bist) cache_as_ram_stage_main(fih); } - -void __weak car_mainboard_pre_console_init(void) -{ -} - -void __weak car_soc_pre_console_init(void) -{ -} - -void __weak car_mainboard_post_console_init(void) -{ -} - -void __weak car_soc_post_console_init(void) -{ -} diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h index 8d7a683672..3d99fa6dc9 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/car.h +++ b/src/drivers/intel/fsp1_1/include/fsp/car.h @@ -24,12 +24,4 @@ * cache_as_ram_stage_main() is the stack pointer to use in RAM after * exiting cache-as-ram mode. */ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih); - -/* Mainboard and SoC initialization prior to console. */ -void car_mainboard_pre_console_init(void); -void car_soc_pre_console_init(void); -/* Mainboard and SoC initialization post console initialization. */ -void car_mainboard_post_console_init(void); -void car_soc_post_console_init(void); - #endif diff --git a/src/drivers/lenovo/hybrid_graphics/Kconfig b/src/drivers/lenovo/hybrid_graphics/Kconfig index 389dfb919f..222d4fd2f2 100644 --- a/src/drivers/lenovo/hybrid_graphics/Kconfig +++ b/src/drivers/lenovo/hybrid_graphics/Kconfig @@ -1,3 +1,5 @@ config DRIVERS_LENOVO_HYBRID_GRAPHICS bool default n + # for dual graphics we need to set this + select ONBOARD_VGA_IS_PRIMARY diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index a805609c5e..4e1043edb7 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -201,11 +201,6 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = adesto_write, .erase = spi_flash_cmd_erase, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif }; int spi_flash_probe_adesto(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 64c91cc79f..b580dc3df0 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -176,11 +176,6 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = amic_write, .erase = spi_flash_cmd_erase, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif }; int spi_flash_probe_amic(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 7d6e172755..58a2862eeb 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -157,11 +157,6 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = atmel_write, .erase = spi_flash_cmd_erase, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif }; int spi_flash_probe_atmel(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index e311752dee..ad282c695b 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -31,21 +31,18 @@ static struct spi_flash spi_flash_info; static bool spi_flash_init_done; /* - * Set this to 1 to debug SPI speed, 0 to disable it - * The format is: + * SPI speed logging for big transfers available with BIOS_DEBUG. The format is: * - * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps + * read SPI 0x62854 0x7db7: 10416 us, 3089 KB/s, 24.712 Mbps * * The important number is the last one. It should roughly match your SPI * clock. If it doesn't, your driver might need a little tuning. */ -#define SPI_SPEED_DEBUG 0 - static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { struct stopwatch sw; - bool show = SPI_SPEED_DEBUG && size >= 4 * KiB; + bool show = size >= 4 * KiB && console_log_level(BIOS_DEBUG); if (show) stopwatch_init(&sw); @@ -58,7 +55,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b, u64 speed; /* KiB/s */ int bps; /* Bits per second */ - speed = (u64)size * 1000 / usecs; + speed = size * 1000 / usecs; bps = speed * 8; printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 33e12a000f..f3cf70ef1b 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -292,7 +292,6 @@ static const struct spi_flash_ops spi_flash_ops = { .write = eon_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, - .read = spi_flash_cmd_read_fast, }; int spi_flash_probe_eon(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 83216c06d1..1ff594a24a 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -41,118 +41,131 @@ struct gigadevice_spi_flash_params { uint16_t id; - /* Log2 of page size in power-of-two mode */ - uint8_t l2_page_size; - uint16_t pages_per_sector; - uint16_t sectors_per_block; - uint16_t nr_blocks; - const char *name; + uint8_t dual_spi : 1; + uint8_t _reserved_for_flags : 3; + uint8_t l2_page_size_shift : 4; + uint8_t pages_per_sector_shift : 4; + uint8_t sectors_per_block_shift : 4; + uint8_t nr_blocks_shift; + const char name[10]; }; static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = { { - .id = 0x3114, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 16, - .name = "GD25T80", + .id = 0x3114, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .name = "GD25T80", }, { - .id = 0x4014, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 16, - .name = "GD25Q80(B)", + .id = 0x4014, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .dual_spi = 1, + .name = "GD25Q80", + }, /* also GD25Q80B */ + { + .id = 0x4015, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 5, + .dual_spi = 1, + .name = "GD25Q16", + }, /* also GD25Q16B */ + { + .id = 0x4016, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 6, + .dual_spi = 1, + .name = "GD25Q32B", + }, /* also GD25Q32B */ + { + .id = 0x4017, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 7, + .dual_spi = 1, + .name = "GD25Q64", + }, /* also GD25Q64B, GD25B64C */ + { + .id = 0x4018, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 8, + .dual_spi = 1, + .name = "GD25Q128", + }, /* also GD25Q128B */ + { + .id = 0x4214, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .dual_spi = 1, + .name = "GD25VQ80C", }, { - .id = 0x4015, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 32, - .name = "GD25Q16(B)", + .id = 0x4215, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 5, + .dual_spi = 1, + .name = "GD25VQ16C", }, { - .id = 0x4016, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 64, - .name = "GD25Q32(B)", + .id = 0x6014, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 4, + .dual_spi = 1, + .name = "GD25LQ80", }, { - .id = 0x4017, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 128, - .name = "GD25Q64(B)/GD25B64C", + .id = 0x6015, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 5, + .dual_spi = 1, + .name = "GD25LQ16", }, { - .id = 0x4018, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 256, - .name = "GD25Q128(B)", + .id = 0x6016, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 6, + .dual_spi = 1, + .name = "GD25LQ32", }, { - .id = 0x4214, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 16, - .name = "GD25VQ80C", - }, + .id = 0x6017, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 7, + .dual_spi = 1, + .name = "GD25LQ64C", + }, /* also GD25LB64C */ { - .id = 0x4215, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 32, - .name = "GD25VQ16C", - }, - { - .id = 0x6014, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 16, - .name = "GD25LQ80", - }, - { - .id = 0x6015, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 32, - .name = "GD25LQ16", - }, - { - .id = 0x6016, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 64, - .name = "GD25LQ32", - }, - { - .id = 0x6017, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 128, - .name = "GD25LQ64C/GD25LB64C", - }, - { - .id = 0x6018, - .l2_page_size = 8, - .pages_per_sector = 16, - .sectors_per_block = 16, - .nr_blocks = 256, - .name = "GD25LQ128", + .id = 0x6018, + .l2_page_size_shift = 8, + .pages_per_sector_shift = 4, + .sectors_per_block_shift = 4, + .nr_blocks_shift = 8, + .dual_spi = 1, + .name = "GD25LQ128", }, }; @@ -222,11 +235,6 @@ static const struct spi_flash_ops spi_flash_ops = { .write = gigadevice_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif }; int spi_flash_probe_gigadevice(const struct spi_slave *spi, u8 *idcode, @@ -252,10 +260,12 @@ int spi_flash_probe_gigadevice(const struct spi_slave *spi, u8 *idcode, flash->name = params->name; /* Assuming power-of-two page size initially. */ - flash->page_size = 1 << params->l2_page_size; - flash->sector_size = flash->page_size * params->pages_per_sector; - flash->size = flash->sector_size * params->sectors_per_block * - params->nr_blocks; + flash->page_size = 1 << params->l2_page_size_shift; + flash->sector_size = flash->page_size * + (1 << params->pages_per_sector_shift); + flash->size = flash->sector_size * + (1 << params->sectors_per_block_shift) * + (1 << params->nr_blocks_shift); flash->erase_cmd = CMD_GD25_SE; flash->status_cmd = CMD_GD25_RDSR; diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 1610ca18c8..5a97b8f794 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -268,11 +268,6 @@ static const struct spi_flash_ops spi_flash_ops = { .write = macronix_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif }; int spi_flash_probe_macronix(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index e687bf8471..4a241baf09 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -282,7 +282,6 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len, static const struct spi_flash_ops spi_flash_ops = { .write = spansion_write, .erase = spi_flash_cmd_erase, - .read = spi_flash_cmd_read_slow, .status = spi_flash_cmd_status, }; diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index ae1d2efb22..a81306e386 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -31,7 +31,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd) static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, size_t bytes_out, void *din, size_t bytes_in) { - int ret = 1; + int ret; /* * SPI flash requires command-response kind of behavior. Thus, two * separate SPI vectors are required -- first to transmit dout and other @@ -49,11 +49,39 @@ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout, if (!bytes_in) count = 1; - if (spi_claim_bus(spi)) + ret = spi_claim_bus(spi); + if (ret) return ret; - if (spi_xfer_vector(spi, vectors, count) == 0) - ret = 0; + ret = spi_xfer_vector(spi, vectors, count); + + spi_release_bus(spi); + return ret; +} + +static int do_dual_read_cmd(const struct spi_slave *spi, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + int ret; + + /* + * spi_xfer_vector() will automatically fall back to .xfer() if + * .xfer_vector() is unimplemented. So using vector API here is more + * flexible, even though a controller that implements .xfer_vector() + * and (the non-vector based) .xfer_dual() but not .xfer() would be + * pretty odd. + */ + struct spi_op vector = { .dout = dout, .bytesout = bytes_out, + .din = NULL, .bytesin = 0 }; + + ret = spi_claim_bus(spi); + if (ret) + return ret; + + ret = spi_xfer_vector(spi, &vector, 1); + + if (!ret) + ret = spi->ctrlr->xfer_dual(spi, NULL, 0, din, bytes_in); spi_release_bus(spi); return ret; @@ -68,18 +96,6 @@ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t le return ret; } -static int spi_flash_cmd_read(const struct spi_slave *spi, const u8 *cmd, - size_t cmd_len, void *data, size_t data_len) -{ - int ret = do_spi_flash_cmd(spi, cmd, cmd_len, data, data_len); - if (ret) { - printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n", - data_len, ret); - } - - return ret; -} - /* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ #pragma GCC diagnostic push #if defined(__GNUC__) && !defined(__clang__) @@ -103,34 +119,43 @@ int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, } #pragma GCC diagnostic pop -static int spi_flash_cmd_read_array(const struct spi_slave *spi, u8 *cmd, - size_t cmd_len, u32 offset, - size_t len, void *data) -{ - spi_flash_addr(offset, cmd); - return spi_flash_cmd_read(spi, cmd, cmd_len, data, len); -} - /* Perform the read operation honoring spi controller fifo size, reissuing * the read command until the full request completed. */ -static int spi_flash_cmd_read_array_wrapped(const struct spi_slave *spi, - u8 *cmd, size_t cmd_len, u32 offset, - size_t len, void *buf) +static int spi_flash_read_chunked(const struct spi_flash *flash, u32 offset, + size_t len, void *buf) { - int ret; - size_t xfer_len; + u8 cmd[5]; + int ret, cmd_len; + int (*do_cmd)(const struct spi_slave *spi, const void *din, + size_t in_bytes, void *out, size_t out_bytes); + + if (CONFIG(SPI_FLASH_NO_FAST_READ)) { + cmd_len = 4; + cmd[0] = CMD_READ_ARRAY_SLOW; + do_cmd = do_spi_flash_cmd; + } else if (flash->flags.dual_spi && flash->spi.ctrlr->xfer_dual) { + cmd_len = 5; + cmd[0] = CMD_READ_FAST_DUAL_OUTPUT; + cmd[4] = 0; + do_cmd = do_dual_read_cmd; + } else { + cmd_len = 5; + cmd[0] = CMD_READ_ARRAY_FAST; + cmd[4] = 0; + do_cmd = do_spi_flash_cmd; + } + uint8_t *data = buf; - while (len) { - xfer_len = spi_crop_chunk(spi, cmd_len, len); - - /* Perform the read. */ - ret = spi_flash_cmd_read_array(spi, cmd, cmd_len, - offset, xfer_len, data); - - if (ret) + size_t xfer_len = spi_crop_chunk(&flash->spi, cmd_len, len); + spi_flash_addr(offset, cmd); + ret = do_cmd(&flash->spi, cmd, cmd_len, data, xfer_len); + if (ret) { + printk(BIOS_WARNING, + "SF: Failed to send read command %#.2x(%#x, %#zx): %d\n", + cmd[0], offset, xfer_len, ret); return ret; - + } offset += xfer_len; data += xfer_len; len -= xfer_len; @@ -139,28 +164,6 @@ static int spi_flash_cmd_read_array_wrapped(const struct spi_slave *spi, return 0; } -int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, - size_t len, void *data) -{ - u8 cmd[5]; - - cmd[0] = CMD_READ_ARRAY_FAST; - cmd[4] = 0x00; - - return spi_flash_cmd_read_array_wrapped(&flash->spi, cmd, sizeof(cmd), - offset, len, data); -} - -int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, - size_t len, void *data) -{ - u8 cmd[4]; - - cmd[0] = CMD_READ_ARRAY_SLOW; - return spi_flash_cmd_read_array_wrapped(&flash->spi, cmd, sizeof(cmd), - offset, len, data); -} - int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, u8 cmd, u8 poll_bit) { @@ -174,7 +177,7 @@ int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout, mono_time_add_msecs(&end, timeout); do { - ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1); + ret = do_spi_flash_cmd(spi, &cmd, 1, &status, 1); if (ret) return -1; if ((status & poll_bit) == 0) @@ -377,8 +380,12 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) return -1; } - printk(BIOS_INFO, "SF: Detected %s with sector size 0x%x, total 0x%x\n", - flash->name, flash->sector_size, flash->size); + const char *mode_string = ""; + if (flash->flags.dual_spi && spi.ctrlr->xfer_dual) + mode_string = " (Dual SPI mode)"; + printk(BIOS_INFO, + "SF: Detected %s with sector size 0x%x, total 0x%x%s\n", + flash->name, flash->sector_size, flash->size, mode_string); if (bus == CONFIG_BOOT_DEVICE_SPI_FLASH_BUS && flash->size != CONFIG_ROM_SIZE) { printk(BIOS_ERR, "SF size 0x%x does not correspond to" @@ -391,7 +398,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) int spi_flash_read(const struct spi_flash *flash, u32 offset, size_t len, void *buf) { - return flash->ops->read(flash, offset, len, buf); + if (flash->ops->read) + return flash->ops->read(flash, offset, len, buf); + + return spi_flash_read_chunked(flash, offset, len, buf); } int spi_flash_write(const struct spi_flash *flash, u32 offset, size_t len, diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index a89610a7bc..4a9e289029 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -23,6 +23,8 @@ #define CMD_READ_ARRAY_FAST 0x0b #define CMD_READ_ARRAY_LEGACY 0xe8 +#define CMD_READ_FAST_DUAL_OUTPUT 0x3b + #define CMD_READ_STATUS 0x05 #define CMD_WRITE_ENABLE 0x06 @@ -34,12 +36,6 @@ /* Send a single-byte command to the device and read the response */ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len); -int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset, - size_t len, void *data); - -int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset, - size_t len, void *data); - /* * Send a multi-byte command to the device followed by (optional) * data. Used for programming the flash array, etc. diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index e4ea7805dd..abe3f2ace6 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -55,14 +55,12 @@ static const struct spi_flash_ops spi_flash_ops_write_ai = { .write = sst_write_ai, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, - .read = spi_flash_cmd_read_fast, }; static const struct spi_flash_ops spi_flash_ops_write_256 = { .write = sst_write_256, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, - .read = spi_flash_cmd_read_fast, }; #define SST_SECTOR_SIZE (4 * 1024) diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index fb24b27266..6625764268 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -351,7 +351,6 @@ out: static const struct spi_flash_ops spi_flash_ops = { .write = stmicro_write, .erase = spi_flash_cmd_erase, - .read = spi_flash_cmd_read_fast, }; int spi_flash_probe_stmicro(const struct spi_slave *spi, u8 *idcode, diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 11a518746c..9e9bb00464 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -26,7 +26,9 @@ struct winbond_spi_flash_params { uint16_t id; - uint8_t l2_page_size_shift; + uint8_t dual_spi : 1; + uint8_t _reserved_for_flags : 3; + uint8_t l2_page_size_shift : 4; uint8_t pages_per_sector_shift : 4; uint8_t sectors_per_block_shift : 4; uint8_t nr_blocks_shift; @@ -123,6 +125,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 4, .name = "W25X80", + .dual_spi = 1, }, { .id = 0x3015, @@ -131,6 +134,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 5, .name = "W25X16", + .dual_spi = 1, }, { .id = 0x3016, @@ -139,6 +143,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 6, .name = "W25X32", + .dual_spi = 1, }, { .id = 0x3017, @@ -147,6 +152,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 7, .name = "W25X64", + .dual_spi = 1, }, { .id = 0x4014, @@ -155,6 +161,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 4, .name = "W25Q80_V", + .dual_spi = 1, }, { .id = 0x4015, @@ -163,6 +170,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 5, .name = "W25Q16_V", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -173,6 +181,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 5, .name = "W25Q16DW", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -183,6 +192,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 6, .name = "W25Q32_V", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -193,6 +203,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 6, .name = "W25Q32DW", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, @@ -203,6 +214,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 7, .name = "W25Q64_V", + .dual_spi = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -213,6 +225,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 7, .name = "W25Q64DW", + .dual_spi = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, @@ -223,6 +236,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 8, .name = "W25Q128_V", + .dual_spi = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -233,6 +247,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 8, .name = "W25Q128FW", + .dual_spi = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -243,6 +258,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 8, .name = "W25Q128J", + .dual_spi = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, @@ -253,6 +269,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 9, .name = "W25Q256_V", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, @@ -263,6 +280,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .sectors_per_block_shift = 4, .nr_blocks_shift = 9, .name = "W25Q256J", + .dual_spi = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, @@ -646,11 +664,6 @@ static const struct spi_flash_ops spi_flash_ops = { .write = winbond_write, .erase = spi_flash_cmd_erase, .status = spi_flash_cmd_status, -#if CONFIG(SPI_FLASH_NO_FAST_READ) - .read = spi_flash_cmd_read_slow, -#else - .read = spi_flash_cmd_read_fast, -#endif .get_write_protection = winbond_get_write_protection, .set_write_protection = winbond_set_write_protection, }; @@ -686,6 +699,8 @@ int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode, flash->erase_cmd = CMD_W25_SE; flash->status_cmd = CMD_W25_RDSR; + flash->flags.dual_spi = params->dual_spi; + flash->ops = &spi_flash_ops; flash->driver_private = params; diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 675ee3778e..4fa887b1b4 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -57,6 +57,9 @@ Device (EC0) If (\DPTE == One) { W (DWST, Arg1) } + + /* Initialize UCSI */ + ^UCSI.INIT () } /* @@ -165,6 +168,7 @@ Device (EC0) #include "lid.asl" #include "platform.asl" #include "vbtn.asl" + #include "ucsi.asl" #ifdef EC_ENABLE_DPTF #include "dptf.asl" #endif diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 0de39475bc..47e9072dcb 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -143,3 +143,54 @@ Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */ Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */ Name (CSOS, Package () { 0xb8, 0xff, WR }) /* OS support for S0ix */ Name (CSEX, Package () { 0xb9, 0xff, WR }) /* OS enter(1)/exit(0) S0ix */ + +/* + * EC UCSI + */ +Name (UVR0, Package () { 0x80, 0xff, RD }) /* UCSI Version */ +Name (UVR1, Package () { 0x81, 0xff, RD }) /* UCSI Version */ +Name (UCI0, Package () { 0x84, 0xff, RD }) /* UCSI Change Indicator */ +Name (UCI1, Package () { 0x85, 0xff, RD }) /* UCSI Change Indicator */ +Name (UCI2, Package () { 0x86, 0xff, RD }) /* UCSI Change Indicator */ +Name (UCI3, Package () { 0x87, 0xff, RD }) /* UCSI Change Indicator */ +Name (UCL0, Package () { 0x88, 0xff, WR }) /* UCSI Control */ +Name (UCL1, Package () { 0x89, 0xff, WR }) /* UCSI Control */ +Name (UCL2, Package () { 0x8a, 0xff, WR }) /* UCSI Control */ +Name (UCL3, Package () { 0x8b, 0xff, WR }) /* UCSI Control */ +Name (UCL4, Package () { 0x8c, 0xff, WR }) /* UCSI Control */ +Name (UCL5, Package () { 0x8d, 0xff, WR }) /* UCSI Control */ +Name (UCL6, Package () { 0x8e, 0xff, WR }) /* UCSI Control */ +Name (UCL7, Package () { 0x8f, 0xff, WR }) /* UCSI Control */ +Name (UMI0, Package () { 0x90, 0xff, RD }) /* UCSI Message In */ +Name (UMI1, Package () { 0x91, 0xff, RD }) /* UCSI Message In */ +Name (UMI2, Package () { 0x92, 0xff, RD }) /* UCSI Message In */ +Name (UMI3, Package () { 0x93, 0xff, RD }) /* UCSI Message In */ +Name (UMI4, Package () { 0x94, 0xff, RD }) /* UCSI Message In */ +Name (UMI5, Package () { 0x95, 0xff, RD }) /* UCSI Message In */ +Name (UMI6, Package () { 0x96, 0xff, RD }) /* UCSI Message In */ +Name (UMI7, Package () { 0x97, 0xff, RD }) /* UCSI Message In */ +Name (UMI8, Package () { 0x98, 0xff, RD }) /* UCSI Message In */ +Name (UMI9, Package () { 0x99, 0xff, RD }) /* UCSI Message In */ +Name (UMIA, Package () { 0x9a, 0xff, RD }) /* UCSI Message In */ +Name (UMIB, Package () { 0x9b, 0xff, RD }) /* UCSI Message In */ +Name (UMIC, Package () { 0x9c, 0xff, RD }) /* UCSI Message In */ +Name (UMID, Package () { 0x9d, 0xff, RD }) /* UCSI Message In */ +Name (UMIE, Package () { 0x9e, 0xff, RD }) /* UCSI Message In */ +Name (UMIF, Package () { 0x9f, 0xff, RD }) /* UCSI Message In */ +Name (UMO0, Package () { 0xa0, 0xff, WR }) /* UCSI Message Out */ +Name (UMO1, Package () { 0xa1, 0xff, WR }) /* UCSI Message Out */ +Name (UMO2, Package () { 0xa2, 0xff, WR }) /* UCSI Message Out */ +Name (UMO3, Package () { 0xa3, 0xff, WR }) /* UCSI Message Out */ +Name (UMO4, Package () { 0xa4, 0xff, WR }) /* UCSI Message Out */ +Name (UMO5, Package () { 0xa5, 0xff, WR }) /* UCSI Message Out */ +Name (UMO6, Package () { 0xa6, 0xff, WR }) /* UCSI Message Out */ +Name (UMO7, Package () { 0xa7, 0xff, WR }) /* UCSI Message Out */ +Name (UMO8, Package () { 0xa8, 0xff, WR }) /* UCSI Message Out */ +Name (UMO9, Package () { 0xa9, 0xff, WR }) /* UCSI Message Out */ +Name (UMOA, Package () { 0xaa, 0xff, WR }) /* UCSI Message Out */ +Name (UMOB, Package () { 0xab, 0xff, WR }) /* UCSI Message Out */ +Name (UMOC, Package () { 0xac, 0xff, WR }) /* UCSI Message Out */ +Name (UMOD, Package () { 0xad, 0xff, WR }) /* UCSI Message Out */ +Name (UMOE, Package () { 0xae, 0xff, WR }) /* UCSI Message Out */ +Name (UMOF, Package () { 0xaf, 0xff, WR }) /* UCSI Message Out */ +Name (UCTL, Package () { 0xb0, 0xff, WR }) /* UCSI Control Register */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index fab4fc46c3..f6534d3773 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -145,3 +145,10 @@ Method (_Q66, 0, Serialized) ECQ4 (Local0) } } + +/* UCSI SCI uses a unique event code */ +Method (_Q79, 0, Serialized) +{ + Printf ("EC _Q79 UCSI Event") + Notify (^UCSI, 0x80) +} diff --git a/src/ec/google/wilco/acpi/ucsi.asl b/src/ec/google/wilco/acpi/ucsi.asl new file mode 100644 index 0000000000..f69e5924e7 --- /dev/null +++ b/src/ec/google/wilco/acpi/ucsi.asl @@ -0,0 +1,157 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (UCSI) +{ + Name (_HID, "GOOG000E") + Name (_CID, EisaId ("PNP0CA0")) + Name (_DDN, "Wilco EC UCSI") + Name (_UID, One) + Name (_ADR, Zero) + Name (_STA, 0xf) + + /* Value written to EC control register to start UCSI command */ + Name (UCMD, 0xE0) + + /* Shared memory fields are defined in the SSDT */ + External (VER0, FieldUnitObj) + External (VER1, FieldUnitObj) + External (CCI0, FieldUnitObj) + External (CCI1, FieldUnitObj) + External (CCI2, FieldUnitObj) + External (CCI3, FieldUnitObj) + External (CTL0, FieldUnitObj) + External (CTL1, FieldUnitObj) + External (CTL2, FieldUnitObj) + External (CTL3, FieldUnitObj) + External (CTL4, FieldUnitObj) + External (CTL5, FieldUnitObj) + External (CTL6, FieldUnitObj) + External (CTL7, FieldUnitObj) + External (MGI0, FieldUnitObj) + External (MGI1, FieldUnitObj) + External (MGI2, FieldUnitObj) + External (MGI3, FieldUnitObj) + External (MGI4, FieldUnitObj) + External (MGI5, FieldUnitObj) + External (MGI6, FieldUnitObj) + External (MGI7, FieldUnitObj) + External (MGI8, FieldUnitObj) + External (MGI9, FieldUnitObj) + External (MGIA, FieldUnitObj) + External (MGIB, FieldUnitObj) + External (MGIC, FieldUnitObj) + External (MGID, FieldUnitObj) + External (MGIE, FieldUnitObj) + External (MGIF, FieldUnitObj) + External (MGO0, FieldUnitObj) + External (MGO1, FieldUnitObj) + External (MGO2, FieldUnitObj) + External (MGO3, FieldUnitObj) + External (MGO4, FieldUnitObj) + External (MGO5, FieldUnitObj) + External (MGO6, FieldUnitObj) + External (MGO7, FieldUnitObj) + External (MGO8, FieldUnitObj) + External (MGO9, FieldUnitObj) + External (MGOA, FieldUnitObj) + External (MGOB, FieldUnitObj) + External (MGOC, FieldUnitObj) + External (MGOD, FieldUnitObj) + External (MGOE, FieldUnitObj) + External (MGOF, FieldUnitObj) + + Method (INIT) + { + /* Read UCSI version from EC into shared memory */ + ^VER0 = R (^^UVR0) + ^VER1 = R (^^UVR1) + } + + Method (_DSM, 4, Serialized) + { + If (Arg0 != ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f")) { + Return (Buffer (One) { Zero }) + } + + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) { 0x07 }) + } + Case (One) + { + /* Write Message Out */ + W (^^UMO0, ^MGO0) + W (^^UMO1, ^MGO1) + W (^^UMO2, ^MGO2) + W (^^UMO3, ^MGO3) + W (^^UMO4, ^MGO4) + W (^^UMO5, ^MGO5) + W (^^UMO6, ^MGO6) + W (^^UMO7, ^MGO7) + W (^^UMO8, ^MGO8) + W (^^UMO9, ^MGO9) + W (^^UMOA, ^MGOA) + W (^^UMOB, ^MGOB) + W (^^UMOC, ^MGOC) + W (^^UMOD, ^MGOD) + W (^^UMOE, ^MGOE) + W (^^UMOF, ^MGOF) + + /* Write Control */ + W (^^UCL0, ^CTL0) + W (^^UCL1, ^CTL1) + W (^^UCL2, ^CTL2) + W (^^UCL3, ^CTL3) + W (^^UCL4, ^CTL4) + W (^^UCL5, ^CTL5) + W (^^UCL6, ^CTL6) + W (^^UCL7, ^CTL7) + + /* Start EC Command */ + W (^^UCTL, ^UCMD) + } + Case (2) + { + /* Read Message In */ + ^MGI0 = R (^^UMI0) + ^MGI1 = R (^^UMI1) + ^MGI2 = R (^^UMI2) + ^MGI3 = R (^^UMI3) + ^MGI4 = R (^^UMI4) + ^MGI5 = R (^^UMI5) + ^MGI6 = R (^^UMI6) + ^MGI7 = R (^^UMI7) + ^MGI8 = R (^^UMI8) + ^MGI9 = R (^^UMI9) + ^MGIA = R (^^UMIA) + ^MGIB = R (^^UMIB) + ^MGIC = R (^^UMIC) + ^MGID = R (^^UMID) + ^MGIE = R (^^UMIE) + ^MGIF = R (^^UMIF) + + /* Read Status */ + ^CCI0 = R (^^UCI0) + ^CCI1 = R (^^UCI1) + ^CCI2 = R (^^UCI2) + ^CCI3 = R (^^UCI3) + } + } + Return (Buffer (One) { Zero }) + } +} diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 9b0be19f9a..09211f82ab 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -14,7 +14,10 @@ */ #include +#include +#include #include +#include #include #include #include @@ -25,6 +28,64 @@ #include "ec.h" #include "chip.h" +/* + * The UCSI fields are defined in the UCSI specification at + * https://www.intel.com/content/www/us/en/io/universal-serial-bus/usb-type-c-ucsi-spec.html + * https://www.intel.com/content/www/us/en/io/universal-serial-bus/bios-implementation-of-ucsi.html + */ + +static struct fieldlist ucsi_region_fields[] = { + FIELDLIST_NAMESTR("VER0", 8), + FIELDLIST_NAMESTR("VER1", 8), + FIELDLIST_NAMESTR("RSV0", 8), + FIELDLIST_NAMESTR("RSV1", 8), + FIELDLIST_NAMESTR("CCI0", 8), + FIELDLIST_NAMESTR("CCI1", 8), + FIELDLIST_NAMESTR("CCI2", 8), + FIELDLIST_NAMESTR("CCI3", 8), + FIELDLIST_NAMESTR("CTL0", 8), + FIELDLIST_NAMESTR("CTL1", 8), + FIELDLIST_NAMESTR("CTL2", 8), + FIELDLIST_NAMESTR("CTL3", 8), + FIELDLIST_NAMESTR("CTL4", 8), + FIELDLIST_NAMESTR("CTL5", 8), + FIELDLIST_NAMESTR("CTL6", 8), + FIELDLIST_NAMESTR("CTL7", 8), + FIELDLIST_NAMESTR("MGI0", 8), + FIELDLIST_NAMESTR("MGI1", 8), + FIELDLIST_NAMESTR("MGI2", 8), + FIELDLIST_NAMESTR("MGI3", 8), + FIELDLIST_NAMESTR("MGI4", 8), + FIELDLIST_NAMESTR("MGI5", 8), + FIELDLIST_NAMESTR("MGI6", 8), + FIELDLIST_NAMESTR("MGI7", 8), + FIELDLIST_NAMESTR("MGI8", 8), + FIELDLIST_NAMESTR("MGI9", 8), + FIELDLIST_NAMESTR("MGIA", 8), + FIELDLIST_NAMESTR("MGIB", 8), + FIELDLIST_NAMESTR("MGIC", 8), + FIELDLIST_NAMESTR("MGID", 8), + FIELDLIST_NAMESTR("MGIE", 8), + FIELDLIST_NAMESTR("MGIF", 8), + FIELDLIST_NAMESTR("MGO0", 8), + FIELDLIST_NAMESTR("MGO1", 8), + FIELDLIST_NAMESTR("MGO2", 8), + FIELDLIST_NAMESTR("MGO3", 8), + FIELDLIST_NAMESTR("MGO4", 8), + FIELDLIST_NAMESTR("MGO5", 8), + FIELDLIST_NAMESTR("MGO6", 8), + FIELDLIST_NAMESTR("MGO7", 8), + FIELDLIST_NAMESTR("MGO8", 8), + FIELDLIST_NAMESTR("MGO9", 8), + FIELDLIST_NAMESTR("MGOA", 8), + FIELDLIST_NAMESTR("MGOB", 8), + FIELDLIST_NAMESTR("MGOC", 8), + FIELDLIST_NAMESTR("MGOD", 8), + FIELDLIST_NAMESTR("MGOE", 8), + FIELDLIST_NAMESTR("MGOF", 8), +}; +static const size_t ucsi_region_len = ARRAY_SIZE(ucsi_region_fields); + static void wilco_ec_post_complete(void *unused) { wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_POST_COMPLETE); @@ -111,11 +172,47 @@ static void wilco_ec_read_resources(struct device *dev) wilco_ec_resource(dev, 2, CONFIG_EC_BASE_PACKET, 16); } +static void wilco_ec_fill_ssdt_generator(struct device *dev) +{ + struct opregion opreg; + void *region_ptr; + + if (!dev->enabled) + return; + + region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_region_len); + if (!region_ptr) + return; + memset(region_ptr, 0, ucsi_region_len); + + opreg.name = "UCSM"; + opreg.regionspace = SYSTEMMEMORY; + opreg.regionoffset = (uintptr_t)region_ptr; + opreg.regionlen = ucsi_region_len; + + acpigen_write_scope(acpi_device_path_join(dev, "UCSI")); + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpigen_write_mem32fixed(1, (uintptr_t)region_ptr, ucsi_region_len); + acpigen_write_resourcetemplate_footer(); + acpigen_write_opregion(&opreg); + acpigen_write_field(opreg.name, ucsi_region_fields, ucsi_region_len, + FIELD_ANYACC | FIELD_LOCK | FIELD_PRESERVE); + acpigen_pop_len(); /* Scope */ +} + +static const char *wilco_ec_acpi_name(const struct device *dev) +{ + return "EC0"; +} + static struct device_operations ops = { - .init = wilco_ec_init, - .read_resources = wilco_ec_read_resources, - .enable_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, + .init = wilco_ec_init, + .read_resources = wilco_ec_read_resources, + .enable_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .acpi_fill_ssdt_generator = wilco_ec_fill_ssdt_generator, + .acpi_name = wilco_ec_acpi_name, }; static struct pnp_info info[] = { diff --git a/src/include/console/console.h b/src/include/console/console.h index 082ba29be8..e5b753e8b6 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -42,8 +42,9 @@ void post_log_clear(void); #endif /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); -void __noreturn die(const char *msg); -void __noreturn die_with_post_code(uint8_t value, const char *msg); +void __noreturn die(const char *fmt, ...); +#define die_with_post_code(value, fmt, ...) \ + do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0) /* * This function is weak and can be overridden to provide additional @@ -62,8 +63,8 @@ asmlinkage void console_init(void); int console_log_level(int msg_level); void do_putchar(unsigned char byte); -#define printk(LEVEL, fmt, args...) \ - do { do_printk(LEVEL, fmt, ##args); } while (0) +#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args) +#define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args) enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL }; @@ -83,14 +84,15 @@ static inline int get_console_loglevel(void) static inline void console_init(void) {} static inline int console_log_level(int msg_level) { return 0; } static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void vprintk(int LEVEL, const char *fmt, va_list args) {} static inline void do_putchar(unsigned char byte) {} #endif -int vprintk(int msg_level, const char *fmt, va_list args); - int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +int do_vprintk(int msg_level, const char *fmt, va_list args); + #endif /* !__ROMCC__ */ #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a35e134dc9..2c8fadcc6f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2696,8 +2696,8 @@ #define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146 #define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147 #define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148 -#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa149 -#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150 +#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa149 +#define PCI_DEVICE_ID_INTEL_SPT_H_CM236 0xa150 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e #define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143 #define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d @@ -2723,13 +2723,13 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480 -#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481 -#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483 -#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484 -#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487 -#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 +#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 +#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483 +#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484 +#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487 +#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 @@ -3076,7 +3076,10 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_U 0x1904 #define PCI_DEVICE_ID_INTEL_SKL_ID_Y 0x190c #define PCI_DEVICE_ID_INTEL_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2 0x1900 #define PCI_DEVICE_ID_INTEL_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2 0x190f +#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 #define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f diff --git a/src/include/memory_info.h b/src/include/memory_info.h index 93c7b6bfc9..ad3c1775f9 100644 --- a/src/include/memory_info.h +++ b/src/include/memory_info.h @@ -86,6 +86,10 @@ struct dimm_info { * See the smbios.h smbios_memory_bus_width enum. */ uint8_t bus_width; + /* + * Voltage Level + */ + uint16_t vdd_voltage; } __packed; struct memory_info { diff --git a/src/include/rules.h b/src/include/rules.h index ce968f0dd9..fcb827df90 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -257,9 +257,14 @@ #endif +#if CONFIG(RAMPAYLOAD) +/* ENV_PAYLOAD_LOADER is set to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enabled */ +#define ENV_PAYLOAD_LOADER ENV_POSTCAR +#else /* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload. * For now, that is the ramstage. */ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE +#endif /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index c24aadd926..d0f957f1f9 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -125,6 +125,7 @@ enum { * setup: Setup given SPI device bus. * xfer: Perform one SPI transfer operation. * xfer_vector: Vector of SPI transfer operations. + * xfer_dual: (optional) Perform one SPI transfer in Dual SPI mode. * max_xfer_size: Maximum transfer size supported by the controller * (0 = invalid, * SPI_CTRLR_DEFAULT_MAX_XFER_SIZE = unlimited) @@ -145,6 +146,8 @@ struct spi_ctrlr { size_t bytesout, void *din, size_t bytesin); int (*xfer_vector)(const struct spi_slave *slave, struct spi_op vectors[], size_t count); + int (*xfer_dual)(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin); uint32_t max_xfer_size; uint32_t flags; int (*flash_probe)(const struct spi_slave *slave, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 936b0abe85..3a0c383676 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -90,6 +90,13 @@ struct spi_flash_ops { struct spi_flash { struct spi_slave spi; u8 vendor; + union { + u8 raw; + struct { + u8 dual_spi : 1; + u8 _reserved : 7; + }; + } flags; u16 model; const char *name; u32 size; diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h index 28cb85998b..192cfb9014 100644 --- a/src/include/stage_cache.h +++ b/src/include/stage_cache.h @@ -32,14 +32,21 @@ enum { STAGE_S3_DATA, }; +#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \ + || CONFIG(RELOCATABLE_RAMSTAGE) /* Cache the loaded stage provided according to the parameters. */ void stage_cache_add(int stage_id, const struct prog *stage); +/* Load the cached stage at given location returning the stage entry point. */ +void stage_cache_load_stage(int stage_id, struct prog *stage); +#else /* CONFIG_NO_STAGE_CACHE */ +static inline void stage_cache_add(int stage_id, const struct prog *stage) {} +static inline void stage_cache_load_stage(int stage_id, struct prog *stage) {} +#endif + /* Cache non-specific data or code. */ void stage_cache_add_raw(int stage_id, const void *base, const size_t size); /* Get a pointer to cached raw data and its size. */ void stage_cache_get_raw(int stage_id, void **base, size_t *size); -/* Load the cached stage at given location returning the stage entry point. */ -void stage_cache_load_stage(int stage_id, struct prog *stage); /* Fill in parameters for the external stage cache, if utilized. */ void stage_cache_external_region(void **base, size_t *size); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index a21663fc0f..81ec2ec3c4 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -74,11 +74,6 @@ fail: halt(); } -void __weak stage_cache_add(int stage_id, - const struct prog *stage) {} -void __weak stage_cache_load_stage(int stage_id, - struct prog *stage) {} - static void ramstage_cache_invalid(void) { printk(BIOS_ERR, "ramstage cache invalid.\n"); @@ -155,8 +150,7 @@ void run_ramstage(void) } else if (load_nonrelocatable_ramstage(&ramstage)) goto fail; - if (!CONFIG(NO_STAGE_CACHE)) - stage_cache_add(STAGE_RAMSTAGE, &ramstage); + stage_cache_add(STAGE_RAMSTAGE, &ramstage); timestamp_add_now(TS_END_COPYRAM); diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 363df55da2..c88d31719e 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -24,6 +24,8 @@ config BOARD_ROMSIZE_KB_2048 bool config BOARD_ROMSIZE_KB_4096 bool +config BOARD_ROMSIZE_KB_6144 + bool config BOARD_ROMSIZE_KB_8192 bool config BOARD_ROMSIZE_KB_10240 @@ -47,6 +49,7 @@ choice default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 + default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144 default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240 default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288 @@ -94,6 +97,11 @@ config COREBOOT_ROMSIZE_KB_4096 help Choose this option if you have a 4096 KB (4 MB) ROM chip. +config COREBOOT_ROMSIZE_KB_6144 + bool "6144 KB (6 MB)" + help + Choose this option if you have a 6144 KB (6 MB) ROM chip. + config COREBOOT_ROMSIZE_KB_8192 bool "8192 KB (8 MB)" help @@ -136,6 +144,7 @@ config COREBOOT_ROMSIZE_KB default 1024 if COREBOOT_ROMSIZE_KB_1024 default 2048 if COREBOOT_ROMSIZE_KB_2048 default 4096 if COREBOOT_ROMSIZE_KB_4096 + default 6144 if COREBOOT_ROMSIZE_KB_6144 default 8192 if COREBOOT_ROMSIZE_KB_8192 default 10240 if COREBOOT_ROMSIZE_KB_10240 default 12288 if COREBOOT_ROMSIZE_KB_12288 @@ -153,6 +162,7 @@ config ROM_SIZE default 0x100000 if COREBOOT_ROMSIZE_KB_1024 default 0x200000 if COREBOOT_ROMSIZE_KB_2048 default 0x400000 if COREBOOT_ROMSIZE_KB_4096 + default 0x600000 if COREBOOT_ROMSIZE_KB_6144 default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0xa00000 if COREBOOT_ROMSIZE_KB_10240 default 0xc00000 if COREBOOT_ROMSIZE_KB_12288 diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c index 140bc07529..2f4be03ddf 100644 --- a/src/mainboard/amd/gardenia/bootblock/bootblock.c +++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c @@ -23,5 +23,5 @@ void bootblock_mainboard_early_init(void) size_t num_gpios; const struct soc_amd_gpio *gpios; gpios = early_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); } diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index b3f2285ef0..3a4090cf92 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -82,7 +82,7 @@ static void mainboard_init(void *chip_info) size_t num_gpios; const struct soc_amd_gpio *gpios; gpios = gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); } /************************************************* diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 9da3891a72..5ce28a27a9 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -64,7 +64,6 @@ chip northbridge/intel/i945 register "gpi1_routing" = "2" register "gpi7_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 156fe3fd64..acb8ac6702 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -51,7 +51,6 @@ chip northbridge/intel/x4x # Northbridge register "gpi13_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index ba2f00d1ec..f4d1dc4291 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 45a20142f4..2fd6e4f649 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index b458115134..5479faf3e9 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -46,7 +46,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqh_routing" = "0x0b" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 2f7d2781d7..de63da2a5d 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -53,7 +53,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 63ae8ce3c5..bc023d24c9 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -43,7 +43,6 @@ chip northbridge/intel/x4x # Northbridge # 2 SCI (if corresponding GPIO_EN bit is also set) register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x04000440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 75df88e5c6..a611ee35c5 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -40,7 +40,6 @@ chip northbridge/intel/pineview # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x441" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index ca952ba7c6..b196e24961 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -47,7 +47,6 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x0" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" device pci 1b.0 on end # Audio diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index c0cad6a387..c99455322b 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -57,7 +57,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "docking_supported" = "1" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 7ed4d199aa..1c69613cbe 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -76,7 +76,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 8b47c4f21f..d24eb5d6ac 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -48,7 +48,6 @@ chip northbridge/intel/x4x # Northbridge register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" # AHCI does not work register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40" diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc index 92b0422279..027c49cc8f 100644 --- a/src/mainboard/google/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/Makefile.inc @@ -14,8 +14,9 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + romstage-$(CONFIG_CHROMEOS) += chromeos.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c romstage-y += spd/spd.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c index 44260bb1eb..b08dbce630 100644 --- a/src/mainboard/google/cyan/com_init.c +++ b/src/mainboard/google/cyan/com_init.c @@ -14,14 +14,14 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include -#include -void car_mainboard_pre_console_init(void) +void bootblock_mainboard_early_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/mainboard/google/dragonegg/romstage_fsp_params.c b/src/mainboard/google/dragonegg/romstage_fsp_params.c index f2c6851a3f..f1f5143ab5 100644 --- a/src/mainboard/google/dragonegg/romstage_fsp_params.c +++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c @@ -13,9 +13,74 @@ * GNU General Public License for more details. */ +#include #include +#include +#include #include +static uintptr_t mainboard_get_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + const size_t spd_len = CONFIG_DIMM_SPD_SIZE; + const char *spd_bin = "spd.bin"; + + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + + return (uintptr_t)(spd_file + spd_index); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + struct lpddr4_config mem_params; + + memset(&mem_params, 0, sizeof(mem_params)); + variant_memory_params(&mem_params); + + if (mem_params.dq_map && mem_params.dq_map_size) + memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map, + mem_params.dq_map_size); + + if (mem_params.dqs_map && mem_params.dqs_map_size) + memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map, + mem_params.dqs_map_size); + + memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor, + mem_params.rcomp_resistor_size); + + memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target, + mem_params.rcomp_target_size); + + mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; } diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb index f820924280..b3b93f55ca 100644 --- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb @@ -102,8 +102,8 @@ chip soc/intel/icelake [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" register "SerialIoGSpiMode" = "{ diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index bffcf844e6..50f9114913 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "100" + register "gpu_pp_down_delay_ms" = "500" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "1" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index f1c846e596..c1afe3d439 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "200" + # Deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb index 13dfa29bbd..cddb10d11a 100644 --- a/src/mainboard/google/glados/variants/asuka/devicetree.cb +++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb index 1a67ccea7c..aabf179b93 100644 --- a/src/mainboard/google/glados/variants/caroline/devicetree.cb +++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb index 9a2fc12fc0..993cab0cee 100644 --- a/src/mainboard/google/glados/variants/cave/devicetree.cb +++ b/src/mainboard/google/glados/variants/cave/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb index de8641c421..a3797571ff 100644 --- a/src/mainboard/google/glados/variants/chell/devicetree.cb +++ b/src/mainboard/google/glados/variants/chell/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb index 0d27a44ca2..1d9e6cdf1f 100644 --- a/src/mainboard/google/glados/variants/glados/devicetree.cb +++ b/src/mainboard/google/glados/variants/glados/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb index 204ade23b0..b8871d196d 100644 --- a/src/mainboard/google/glados/variants/lars/devicetree.cb +++ b/src/mainboard/google/glados/variants/lars/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb index 89120a3d4e..7f52586e3d 100644 --- a/src/mainboard/google/glados/variants/sentry/devicetree.cb +++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb @@ -1,5 +1,13 @@ chip soc/intel/skylake + register "gpu_pp_up_delay_ms" = "200" + register "gpu_pp_down_delay_ms" = " 50" + register "gpu_pp_cycle_delay_ms" = "500" + register "gpu_pp_backlight_on_delay_ms" = " 1" + register "gpu_pp_backlight_off_delay_ms" = "200" + + register "gpu_pch_backlight_pwm_hz" = "1000" + # Enable deep Sx states register "deep_s3_enable_ac" = "0" register "deep_s3_enable_dc" = "0" diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd index 1594ab3a52..eb92bb0a01 100644 --- a/src/mainboard/google/hatch/chromeos-16MiB.fmd +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -4,17 +4,17 @@ FLASH@0xff000000 0x1000000 { SI_ME@0x1000 0x3ff000 } SI_BIOS@0x400000 0xc00000 { - RW_SECTION_A@0x0 0x380000 { + RW_SECTION_A@0x0 0x368000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x36ffc0 - RW_FWID_A@0x37ffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x357fc0 + RW_FWID_A@0x367fc0 0x40 } - RW_SECTION_B@0x380000 0x380000 { + RW_SECTION_B@0x368000 0x368000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x36ffc0 - RW_FWID_B@0x37ffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x357fc0 + RW_FWID_B@0x367fc0 0x40 } - RW_MISC@0x700000 0x30000 { + RW_MISC@0x6D0000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -27,7 +27,8 @@ FLASH@0xff000000 0x1000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x730000 0xd0000 + # RW_LEGACY needs to be minimum of 1MB + RW_LEGACY(CBFS)@0x700000 0x100000 WP_RO@0x800000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { diff --git a/src/mainboard/google/hatch/spd/8G_3200.spd.hex b/src/mainboard/google/hatch/spd/8G_3200.spd.hex new file mode 100644 index 0000000000..7388ad60f7 --- /dev/null +++ b/src/mainboard/google/hatch/spd/8G_3200.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 D0 19 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex b/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex new file mode 100644 index 0000000000..04d640f0ae --- /dev/null +++ b/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex @@ -0,0 +1,32 @@ +24 01 0F 0E 15 1A B4 08 00 00 00 0B 0A 03 00 00 +00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0 +02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 1123d53734..112c279fcb 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" # Enable heci communication - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" # Enable Speed Shift Technology support register "speed_shift_enable" = "1" # Enable S0ix @@ -99,7 +99,9 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" - register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + # Disable clock gating on this community so that cr50's short irq + # pulses won't be missed. + register "gpio_pm[COMM_4]" = "0" device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 038cfe22c2..e403684a41 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -29,7 +30,7 @@ void bootblock_mainboard_early_init(void) mainboard_ec_init(); gpios = variant_early_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); } void bootblock_mainboard_init(void) @@ -61,5 +62,5 @@ void bootblock_mainboard_init(void) } /* Setup TPM decode before verstage */ - sb_tpm_decode_spi(); + lpc_tpm_decode_spi(); } diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c index 7164591e11..1080902702 100644 --- a/src/mainboard/google/kahlee/ec.c +++ b/src/mainboard/google/kahlee/ec.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -49,7 +50,7 @@ static void early_ec_init(void) printk(BIOS_DEBUG, "LPC Setup google_chromeec_ioport_range: %04x, %08zx\n", ec_ioport_base, ec_ioport_size); - status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size); + status = lpc_set_wideio_range(ec_ioport_base, ec_ioport_size); if (status == WIDEIO_RANGE_ERROR) printk(BIOS_WARNING, "ERROR: Failed to assign a range\n"); else diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index cfd5637633..f218f3f31b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -126,7 +127,7 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); gpios = variant_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); /* * Some platforms use SCI not generated by a GPIO pin (event above 23). diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 32f8356521..8bc766e112 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -34,7 +34,7 @@ void mainboard_romstage_entry(int s3_resume) const struct soc_amd_gpio *gpios; gpios = variant_romstage_gpio_table(&num_gpios); - sb_program_gpios(gpios, num_gpios); + program_gpios(gpios, num_gpios); variant_romstage_entry(s3_resume); } diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index c55bb8bdb4..3dc2c2aabc 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -19,7 +19,7 @@ chip soc/amd/stoneyridge }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "16 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index 5124e41dab..635b23735c 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -19,7 +19,7 @@ chip soc/amd/stoneyridge }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "16 * MiB" register "stapm_percent" = "68" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index b37e1bf0ac..d73c47c6b8 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -19,7 +19,7 @@ chip soc/amd/stoneyridge }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "16 * MiB" register "stapm_percent" = "80" register "stapm_time_ms" = "2500000" register "stapm_power_mw" = "7800" diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index a929c46704..30028275c8 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -19,7 +19,7 @@ chip soc/amd/stoneyridge }" register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" - register "uma_size" = "32 * MiB" + register "uma_size" = "16 * MiB" register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index 633df2ee42..76cdd50d91 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -22,7 +22,7 @@ FLASH@0x0 8M { GBB 0x2f00 RO_FRID 0x100 } - RO_VPD 128K + RO_VPD(PRESERVE) 128K RO_DDR_TRAINING(PRESERVE) 8K } diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index 48753ed4b1..8ca9251cfc 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -121,26 +121,18 @@ config TPM_TIS_ACPI_INTERRUPT int default 63 # GPE0_DW1_31 (GPIO_63) -config DRAM_PART_NUM_IN_CBI +config DRAM_PART_NUM_NOT_ALWAYS_IN_CBI bool - default y if BOARD_GOOGLE_PHASER - default y if BOARD_GOOGLE_MEEP - default y if BOARD_GOOGLE_AMPTON - default y if BOARD_GOOGLE_FLEEX default y if BOARD_GOOGLE_BOBBA - default y if BOARD_GOOGLE_CASTA - default y if BOARD_GOOGLE_BLOOG - -config DRAM_PART_NUM_ALWAYS_IN_CBI - bool - depends on DRAM_PART_NUM_IN_CBI - default y if BOARD_GOOGLE_AMPTON - default y if BOARD_GOOGLE_CASTA - default y if BOARD_GOOGLE_BLOOG + default y if BOARD_GOOGLE_FLEEX + default y if BOARD_GOOGLE_MEEP + default y if BOARD_GOOGLE_OCTOPUS + default y if BOARD_GOOGLE_PHASER + default y if BOARD_GOOGLE_YORP config DRAM_PART_IN_CBI_BOARD_ID_MIN int - depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI + depends on DRAM_PART_NUM_NOT_ALWAYS_IN_CBI default 255 if BOARD_GOOGLE_YORP default 2 if BOARD_GOOGLE_PHASER default 2 if BOARD_GOOGLE_FLEEX diff --git a/src/mainboard/google/octopus/romstage.c b/src/mainboard/google/octopus/romstage.c index ff0354dc10..d878d0d33f 100644 --- a/src/mainboard/google/octopus/romstage.c +++ b/src/mainboard/google/octopus/romstage.c @@ -37,12 +37,7 @@ void mainboard_save_dimm_info(void) char part_num_store[DIMM_INFO_PART_NUMBER_SIZE]; const char *part_num = NULL; - if (!CONFIG(DRAM_PART_NUM_IN_CBI)) { - save_dimm_info_by_sku_config(); - return; - } - - if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { + if (CONFIG(DRAM_PART_NUM_NOT_ALWAYS_IN_CBI)) { /* Fall back on part numbers encoded in lp4cfg array. */ if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) { save_dimm_info_by_sku_config(); diff --git a/src/mainboard/google/octopus/variants/baseboard/memory.c b/src/mainboard/google/octopus/variants/baseboard/memory.c index fc7c87dcb2..604295b283 100644 --- a/src/mainboard/google/octopus/variants/baseboard/memory.c +++ b/src/mainboard/google/octopus/variants/baseboard/memory.c @@ -205,10 +205,7 @@ static const struct lpddr4_cfg cbi_lp4cfg = { const struct lpddr4_cfg *__weak variant_lpddr4_config(void) { - if (!CONFIG(DRAM_PART_NUM_IN_CBI)) - return &non_cbi_lp4cfg; - - if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) { + if (CONFIG(DRAM_PART_NUM_NOT_ALWAYS_IN_CBI)) { /* Fall back non cbi memory config. */ if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) return &non_cbi_lp4cfg; diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 1ea28a0e5f..7fcb3b8b3e 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -155,20 +155,6 @@ chip soc/intel/skylake register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" - # PCIe Root port 5 (NVMe) - # PcieRpEnable: Enable root port - # PcieRpClkReqSupport: Enable CLKREQ# - # PcieRpClkReqNumber: Uses SRCCLKREQ4# - # PcieRpClkSrcNumber: Uses CLKOUT_PCIE_4 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting - # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpClkSrcNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - # USB 2.0 register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Empty @@ -374,7 +360,7 @@ chip soc/intel/skylake device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 (NVMe) + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 diff --git a/src/mainboard/google/poppy/variants/atlas/gpio.c b/src/mainboard/google/poppy/variants/atlas/gpio.c index 372c66a5a0..5cc1a4fc5d 100644 --- a/src/mainboard/google/poppy/variants/atlas/gpio.c +++ b/src/mainboard/google/poppy/variants/atlas/gpio.c @@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NC(GPP_B7), /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ PAD_CFG_GPO(GPP_B8, 0, RSMRST), - /* B9 : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B9 : SRCCLKREQ4# ==> NC */ + PAD_CFG_NC(GPP_B9), /* B10 : SRCCLKREQ5# ==> NC */ PAD_CFG_NC(GPP_B10), /* B11 : EXT_PWR_GATE# ==> NC */ diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index 23870175b7..adb8c00579 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -215,7 +215,6 @@ const char *mainboard_vbt_filename(void) return "vbt-bard.bin"; default: return "vbt.bin"; - break; } } diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 767df1f795..ce960a74c0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl index 4d380713e2..73e1decc1b 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl @@ -13,26 +13,26 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 90 -#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 108 /* Skin Sensor for CPU VR temperature monitor */ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "Skin" -#define DPTF_TSR0_PASSIVE 60 -#define DPTF_TSR0_CRITICAL 105 +#define DPTF_TSR0_PASSIVE 55 +#define DPTF_TSR0_CRITICAL 100 /* Memory Sensor for DDR temperature monitor */ #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "DDR" -#define DPTF_TSR1_PASSIVE 70 -#define DPTF_TSR1_CRITICAL 95 +#define DPTF_TSR1_PASSIVE 53 +#define DPTF_TSR1_CRITICAL 100 /* M.2 Sensor for Ambient temperature monitor */ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "Ambient" -#define DPTF_TSR2_PASSIVE 37 -#define DPTF_TSR2_CRITICAL 80 +#define DPTF_TSR2_PASSIVE 38 +#define DPTF_TSR2_CRITICAL 93 #undef DPTF_ENABLE_FAN_CONTROL #undef DPTF_ENABLE_CHARGER @@ -42,10 +42,10 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 100, 0, 0, 0, 0 }, /* CPU Throttle Effect on Skin (TSR0) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 500, 30, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 400, 40, 0, 0, 0, 0 }, /* CPU Throttle Effect on DDR (TSR1) */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 50, 2, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 300, 50, 2, 0, 0, 0 }, /* CPU Throttle Effect on Ambient (TSR2) */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 1000, 100, 1, 0, 0, 0 }, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c93d..739a849715 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -15,7 +15,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "1" + register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig new file mode 100644 index 0000000000..4598de2040 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -0,0 +1,60 @@ +if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM1 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select SUPERIO_NUVOTON_NPCD378 + select MAINBOARD_HAS_LIBGFXINIT + select INTEL_GMA_HAVE_VBT + +config VBOOT + select VBOOT_VBNV_CMOS + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config MAINBOARD_DIR + string + default hp/z220_sff_workstation + +config MAINBOARD_PART_NUMBER + string + default "HP Z220 SFF Workstation" + +config VGA_BIOS_FILE + string + default "pci8086,0102.rom" + +config VGA_BIOS_ID + string + default "8086,0102" + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig.name b/src/mainboard/hp/z220_sff_workstation/Kconfig.name new file mode 100644 index 0000000000..b6cfda6e9a --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC + bool "Z220 SFF Workstation" diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc new file mode 100644 index 0000000000..ebe01aea99 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/ec.asl b/src/mainboard/hp/z220_sff_workstation/acpi/ec.asl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/soc/amd/common/block/acpi/halt.c b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl similarity index 51% rename from src/soc/amd/common/block/acpi/halt.c rename to src/mainboard/hp/z220_sff_workstation/acpi/platform.asl index 200b3c12f5..02a1b54b87 100644 --- a/src/soc/amd/common/block/acpi/halt.c +++ b/src/mainboard/hp/z220_sff_workstation/acpi/platform.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Google Inc. + * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,21 +13,14 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include - -void poweroff(void) +Method(_WAK, 1, NotSerialized) { - acpi_write32(MMIO_ACPI_PM1_CNT_BLK, - (SLP_TYP_S5 << SLP_TYP_SHIFT) | SLP_EN); + \_SB.PCI0.LPCB.SIO0.SIOW (Arg0) - /* - * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM - * to transition to S5 state. If halt is called in SMM, then it prevents - * the SMI handler from being triggered and system never enters S5. - */ - if (!ENV_SMM) - halt(); + Return(Package(){0,0}) +} + +Method(_PTS, 1, NotSerialized) +{ + \_SB.PCI0.LPCB.SIO0.SIOS (Arg0) } diff --git a/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl new file mode 100644 index 0000000000..630c5e8033 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/acpi/superio.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define SUPERIO_SHOW_SP2 +#define SUPERIO_SHOW_KBC + +#include + +Scope (\_GPE) +{ + Method (_L08, 0, NotSerialized) + { + \_SB.PCI0.LPCB.SIO0.SIOH () + } + + Method (_L0D, 0, NotSerialized) + { + Notify (\_SB.PCI0.EHC1, 0x02) + Notify (\_SB.PCI0.EHC2, 0x02) + //FIXME: Add GBE device + //Notify (\_SB.PCI0.GBE, 0x02) + } + + Method (_L09, 0, NotSerialized) + { + Notify (\_SB.PCI0.RP01, 0x02) + Notify (\_SB.PCI0.RP02, 0x02) + Notify (\_SB.PCI0.RP03, 0x02) + Notify (\_SB.PCI0.RP04, 0x02) + Notify (\_SB.PCI0.RP05, 0x02) + Notify (\_SB.PCI0.RP06, 0x02) + Notify (\_SB.PCI0.RP07, 0x02) + Notify (\_SB.PCI0.RP08, 0x02) + Notify (\_SB.PCI0.PEGP, 0x02) + } +} diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c new file mode 100644 index 0000000000..084e7e5a5f --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/hp/z220_sff_workstation/board_info.txt b/src/mainboard/hp/z220_sff_workstation/board_info.txt new file mode 100644 index 0000000000..4d6f6f98b7 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://support.hp.com/de-de/product/HP-Compaq-8200-Elite-Small-Form-Factor-PC/5037931 +ROM IC: MX25L6405 +ROM package: SOIC-8 +ROM socketed: no +Flashrom support: yes +Release year: 2013 diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.default b/src/mainboard/hp/z220_sff_workstation/cmos.default new file mode 100644 index 0000000000..6d27a79c66 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/cmos.default @@ -0,0 +1,7 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Enable +nmi=Enable +sata_mode=AHCI +gfx_uma_size=32M +psu_fan_lvl=3 diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout new file mode 100644 index 0000000000..6602afad2d --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -0,0 +1,116 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## Copyright (C) 2018 Patrick Rudolph +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused +400 3 h 0 psu_fan_lvl +#403 5 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +#411 10 r 0 unused +421 1 e 9 sata_mode +#422 10 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +#435 549 r 0 unused + +448 128 r 0 vbnv + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_sff_workstation/data.vbt new file mode 100644 index 0000000000..c1fd6d1e13 Binary files /dev/null and b/src/mainboard/hp/z220_sff_workstation/data.vbt differ diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb new file mode 100644 index 0000000000..68e7c63767 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -0,0 +1,225 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Patrick Rudolph +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 7 PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0601" + register "gen2_dec" = "0x00fc0801" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0xf" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 14.0 on # xHCI + subsystemid 0x103c 0x1791 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x103c 0x1791 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 on # Management Engine KT + subsystemid 0x103c 0x1791 + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x103c 0x1791 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x103c 0x1791 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x103c 0x1791 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x103c 0x1791 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + subsystemid 0x103c 0x1791 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + subsystemid 0x103c 0x1791 + end + device pci 1c.7 on # PCIe Port #8 + subsystemid 0x103c 0x1791 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x103c 0x1791 + end + device pci 1e.0 on # PCI bridge + subsystemid 0x103c 0x1791 + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x103c 0x1791 + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + # global + + # serialice: Vendor writes: + irq 0x14 = 0x9c + irq 0x1c = 0xa8 + irq 0x1d = 0x08 + irq 0x22 = 0x3f + irq 0x1a = 0xb0 + # dumped from superiotool: + irq 0x1b = 0x1e + irq 0x27 = 0x08 + irq 0x2a = 0x20 + irq 0x2d = 0x01 + # parallel port + io 0x60 = 0x378 + irq 0x70 = 0x07 + drq 0x74 = 0x01 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x600 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0x610 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 on # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 on # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x620 + end + device pnp 2e.8 on # HWM + io 0x60 = 0x800 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector + + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 + + drq 0xf4 = 0x66 + drq 0xf5 = 0x67 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x08 + drq 0xfe = 0x80 + end + device pnp 2e.15 on # BUS ? + io 0x60 = 0x0680 + io 0x62 = 0x0690 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x640 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e on # GPIO ? + io 0x60 = 0x660 + drq 0xf4 = 0x01 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x103c 0x1791 + end + device pci 1f.3 on # SMBus + subsystemid 0x103c 0x1791 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x103c 0x1791 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x103c 0x1791 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x103c 0x1791 + end + end +end diff --git a/src/mainboard/hp/z220_sff_workstation/dsdt.asl b/src/mainboard/hp/z220_sff_workstation/dsdt.asl new file mode 100644 index 0000000000..ef67ee7477 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/dsdt.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } +} diff --git a/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads new file mode 100644 index 0000000000..6d5680d6a9 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/gma-mainboard.ads @@ -0,0 +1,29 @@ +-- +-- Copyright (C) 2018 Patrick Rudolph +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, + HDMI2, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/gpio.c new file mode 100644 index 0000000000..397f08b955 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/gpio.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/hp/z220_sff_workstation/hda_verb.c b/src/mainboard/hp/z220_sff_workstation/hda_verb.c new file mode 100644 index 0000000000..91804c187b --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c1791, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x103c1791), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x403c0000), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a11030), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x0181303f), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40400001), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x21. */ + AZALIA_PIN_CFG(0x0, 0x21, 0x0221102f), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x103c1791, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x103c1791), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/z220_sff_workstation/mainboard.c b/src/mainboard/hp/z220_sff_workstation/mainboard.c new file mode 100644 index 0000000000..2d6499f9dd --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/mainboard.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + int len = 0; + + // add IPMI Device Information + len += smbios_write_type38( + current, handle, + SMBIOS_BMC_INTERFACE_KCS, + 0x20, // IPMI Version + 0x20, // I2C address + 0xff, // no NV storage + 0, // IO port interface address + 0, + 0); // no IRQ + + return len; +} +#endif + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/hp/z220_sff_workstation/romstage.c b/src/mainboard/hp/z220_sff_workstation/romstage.c new file mode 100644 index 0000000000..0804dd0c7a --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/romstage.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2018 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2) + +void pch_enable_lpc(void) +{ + /* + * Enable SuperIO, TPM, Keyboard, LPT, COMA + * (COMB can be equip on expansion header) + */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | + COMB_LPC_EN | COMA_LPC_EN); + + /* COMA: 3F8h, COMB: 2F8h */ + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 1, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 7 }, + { 1, 0, 7 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + /* BTX mainboard: Reversed mapping */ + read_spd(&spd[3], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[0], 0x53, id_only); +} diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index f81a68b711..0c5962fea0 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -36,7 +36,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x1" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a00861043e..825611ef22 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,7 +38,6 @@ chip northbridge/intel/pineview # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index 716654c6eb..573b9c80ed 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -50,7 +50,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x0" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index be28763a00..295fbc4f38 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -63,7 +63,6 @@ chip northbridge/intel/x4x # Northbridge register "gpi15_routing" = "2" register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on # Audio diff --git a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c index b9ce3941f4..fd1638bfab 100644 --- a/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/icelake_rvp/romstage_fsp_params.c @@ -14,12 +14,55 @@ */ #include +#include #include #include #include - +#include "board_id.h" #include "spd/spd.h" void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "spd index is 0x%x\n", spd_index); + + if (spd_index > 0 && spd_index != 2) { + struct region_device spd_rdev; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + + mem_cfg->SpdAddressTable[0] = 0x0; + mem_cfg->SpdAddressTable[1] = 0x0; + mem_cfg->SpdAddressTable[2] = 0x0; + mem_cfg->SpdAddressTable[3] = 0x0; + } else { + mem_cfg->MemorySpdPtr00 = 0; + mem_cfg->MemorySpdPtr01 = 0; + mem_cfg->MemorySpdPtr10 = 0; + mem_cfg->MemorySpdPtr11 = 0; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + } + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(&mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); } diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index bbef8b956e..e6f0c9e652 100644 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,8 +14,9 @@ ## GNU General Public License for more details. ## +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c + romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c index b89d65566e..695ea9806b 100644 --- a/src/mainboard/intel/strago/com_init.c +++ b/src/mainboard/intel/strago/com_init.c @@ -14,12 +14,12 @@ * GNU General Public License for more details. */ +#include #include #include #include #include #include -#include /* * return family number and internal pad number in that community @@ -30,7 +30,7 @@ /* family number in high byte and inner pad number in lowest byte */ -void car_mainboard_pre_console_init(void) +void bootblock_mainboard_early_init(void) { uint32_t reg; uint32_t *pad_config_reg; diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 5e00109ebb..cd7929c31a 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -36,7 +36,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x1" - register "sata_ahci" = "0x0" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2bd67c28bc..2caf1d3b65 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -62,10 +62,6 @@ config CBFS_SIZE hex default 0x200000 -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config INTEL_GMA_VBT_FILE default "src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt" diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index 02bcc4f4a4..5148604a68 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -75,8 +75,4 @@ config VGA_BIOS_ID string default "8086,0126" -config ONBOARD_VGA_IS_PRIMARY - bool - default y - endif # BOARD_LENOVO_T420 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 60735b049d..190f35e4b5 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -74,8 +74,4 @@ config VGA_BIOS_ID string default "8086,0126" -config ONBOARD_VGA_IS_PRIMARY - bool - default y - endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index e847f8e39d..d4934d6685 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -84,8 +84,4 @@ config VGA_BIOS_FILE string default "pci8086,0126.rom" -config ONBOARD_VGA_IS_PRIMARY - bool - default y - endif diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 5b5b7ffa49..5fd9118e94 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -62,8 +62,4 @@ config VGA_BIOS_FILE default "pci8086,0106.rom" if BOARD_LENOVO_T530 default "pci8086,0166.rom" if BOARD_LENOVO_W530 -config ONBOARD_VGA_IS_PRIMARY - bool - default y - endif diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b4c8fb8b4f..28e0574188 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -72,7 +72,6 @@ chip northbridge/intel/i945 register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index cc3ef49f25..ace2bfbff2 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -44,7 +44,6 @@ chip northbridge/intel/x4x # Northbridge register "gpi13_routing" = "1" # ??vendor register "ide_enable_primary" = "0x1" - register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant register "gpe0_en" = "0x440" device pci 1b.0 on end # Audio diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 87cfa849ee..b3d87ccb4b 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -65,7 +65,6 @@ chip northbridge/intel/i945 register "gpi12_routing" = "1" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/lenovo/z61t/devicetree.cb b/src/mainboard/lenovo/z61t/devicetree.cb index 8519b31035..d35c62b09c 100644 --- a/src/mainboard/lenovo/z61t/devicetree.cb +++ b/src/mainboard/lenovo/z61t/devicetree.cb @@ -71,7 +71,6 @@ chip northbridge/intel/i945 register "gpi12_routing" = "2" register "gpi8_routing" = "2" - register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x01" register "gpe0_en" = "0x11000006" diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index 082a9e894c..3ba9d2c331 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -61,7 +61,6 @@ chip northbridge/intel/i945 register "ide_legacy_combined" = "0x1" register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" device pci 1b.0 off end # High Definition Audio device pci 1c.0 on end # PCIe port 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc index adf9aff0d4..03759d2633 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/Makefile.inc @@ -1,2 +1,5 @@ +romstage-y += gpio.c + +ramstage-y += gpio.c ramstage-y += mainboard.c ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c new file mode 100644 index 0000000000..7a424d131e --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/gpio.c @@ -0,0 +1,417 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include +#include + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_NF(GPIO_205, NONE, DEEP, NF1), /* PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_206, NONE, DEEP, NF1), /* PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_207, NONE, DEEP, NF1), /* PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_208, NONE, DEEP, NF1), /* PCIE_WAKE3_N */ + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, NONE, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, NONE, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, NONE, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, NONE, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, NONE, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, NONE, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, NONE, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, NONE, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, NONE, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating. */ + PAD_CFG_GPI(GPIO_168, NONE, DEEP), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, NONE, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, NONE, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, NONE, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K. */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up. */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down. */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_GPI(GPIO_186, NONE, DEEP), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus */ + PAD_CFG_GPI(SMB_ALERTB, NONE, DEEP), /* SMB_ALERT _N */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ + + /* West Community */ + + /* I2C0 - I2C Level Shifter */ + PAD_CFG_NF(GPIO_124, NONE, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, NONE, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C[1:7] -- unused */ + PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ + PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */ + PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */ + PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */ + PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */ + PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */ + PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NONE, DEEP, NF1), + + /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), + /* OSC_CLK_OUT_[1:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, NONE, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, NONE, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + /* PMU_SLP_S0_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* Northwest Community */ + + /* DDI0 SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - Display-Port */ + PAD_CFG_NF(GPIO_189, NONE, DEEP, NF1), /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_190, NONE, DEEP, NF1), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control -- unused */ + PAD_CFG_TERM_GPO(GPIO_193, 0, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_TERM_GPO(GPIO_194, 0, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_TERM_GPO(GPIO_195, 0, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_GPI(GPIO_196, DN_20K, DEEP), /* PNL1_VDDEN */ + PAD_CFG_GPI(GPIO_197, DN_20K, DEEP), /* PNL1_BKLTEN */ + PAD_CFG_GPI(GPIO_198, DN_20K, DEEP), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD -- unused */ + PAD_CFG_GPI(GPIO_199, NONE, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, NONE, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, NONE, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused. */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, NONE, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, DN_20K, DEEP), /* PMIC_RESET_B */ + PAD_CFG_TERM_GPO(GPIO_213, 0, DN_20K, DEEP), /* NFC_OUT_RESERVE */ + PAD_CFG_TERM_GPO(GPIO_214, 0, DN_20K, DEEP), /* NFC_EN */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ + /* THERMTRIP_N */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + /* Disable reset for PCIe switch. */ + PAD_CFG_GPO(PMIC_STDBY, 1, DEEP), + PAD_CFG_NF(PROCHOT_B, NONE, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, NONE, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, NONE, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 -- unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 -- unused */ + PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 -- unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI */ + /* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CS1_B -- unused */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), + /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), + /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), + + /* SIO_SPI_0 -- unused */ + PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ + PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ + PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ + PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, NONE, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */ + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */ + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */ + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */ + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */ + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */ + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_18, DN_20K, DEEP), /* TRACE_2_CLK_VNN */ + PAD_CFG_GPI(GPIO_19, DN_20K, DEEP), /* TRACE_2_DATA0_VNN */ + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ + PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ + PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */ + PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */ + PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */ + PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ + + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ + PAD_CFG_GPO(GPIO_31, 1, DEEP), /* ISH_GPIO_13 */ + PAD_CFG_GPI(GPIO_32, NONE, DEEP), /* ISH_GPIO_14 */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ + + /* PWM[0:3] -- unused */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ + PAD_CFG_GPI(GPIO_42, NONE, DEEP), /* LPSS_UART1_RXD - unused */ + PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */ + PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, DN_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */ + + /* CNV bridge described into IAFW Vol2. */ + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_BRI_RSP, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_RGI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */ + + /* Serial VID */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *__weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + + /* SMBus */ + PAD_CFG_NF(SMB_CLK, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, NONE, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, NONE, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + /* LPC_CLKOUT1 - unused */ + PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), + PAD_CFG_NF(LPC_AD0, NONE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, NONE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, NONE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, NONE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(LPC_CLKRUNB, NONE, DEEP, NF1), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, NONE, DEEP, NF1), /* LPC_FRAME_N */ + + /* Enable reset for PCIe switch. */ + PAD_CFG_GPO(PMIC_STDBY, 0, DEEP), +}; + +const struct pad_config *__weak +variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 2826d7418c..b7ccdecdad 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -1593,7 +1593,8 @@ static void jedec_init(const timings_t *const timings, int ch, r; FOR_EACH_POPULATED_RANK(dimms, ch, r) { /* We won't do this in dual-interleaved mode, - so don't care about the offset. */ + so don't care about the offset. + Mirrored ranks aren't taken into account here. */ const u32 rankaddr = raminit_get_rank_addr(ch, r); printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 282765efcc..72063cbdad 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1835,7 +1835,6 @@ static void sdram_dradrb(struct sysinfo *s) static u8 sampledqs(u32 dqshighaddr, u32 strobeaddr, u8 highlow, u8 count) { - volatile u32 strobedata; u8 dqsmatches = 1; while (count--) { MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; @@ -1843,7 +1842,7 @@ static u8 sampledqs(u32 dqshighaddr, u32 strobeaddr, u8 highlow, u8 count) MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; hpet_udelay(1); barrier(); - strobedata = read32((void *)strobeaddr); + read32((void *)strobeaddr); barrier(); hpet_udelay(1); diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index ba55466026..c77f3bac6a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -43,7 +43,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += iommu.c romstage-y += early_init.c romstage-y += ../../../arch/x86/walkcbfs.S diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index fd3d34f2de..0c6ef7ebdf 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 secunet Security Networks AG * Copyright (C) 2011 Google Inc + * Copyright (C) 2018 Patrick Rudolph * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +19,8 @@ #include #include #include +#include +#include #include #include #include @@ -25,6 +29,41 @@ #include "sandybridge.h" +static void systemagent_vtd_init(void) +{ + const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + if (capid0_a & (1 << 23)) + return; + + /* setup BARs */ + MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; + MCHBAR32(0x5400) = IOMMU_BASE1 | 1; + MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; + MCHBAR32(0x5410) = IOMMU_BASE2 | 1; + + /* lock policies */ + write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); + + const struct device *const azalia = pcidev_on_root(0x1b, 0); + if (azalia && azalia->enabled) { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); + write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); + } else { + write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); + } +} + +static void enable_pam_region(void) +{ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); +} + static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); @@ -36,15 +75,6 @@ static void sandybridge_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); - /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - printk(BIOS_DEBUG, " done\n"); } @@ -156,7 +186,7 @@ static void start_peg_link_training(void) } } -void sandybridge_early_initialization(void) +void systemagent_early_init(void) { u32 capid0_a; u32 deven; @@ -179,8 +209,11 @@ void sandybridge_early_initialization(void) /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(); + /* Set C0000-FFFFF to access RAM on both reads and writes */ + enable_pam_region(); + /* Setup IOMMU BARs */ - sandybridge_init_iommu(); + systemagent_vtd_init(); /* Device Enable, don't touch PEG bits */ deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | DEVEN_IGD; diff --git a/src/northbridge/intel/sandybridge/iommu.c b/src/northbridge/intel/sandybridge/iommu.c deleted file mode 100644 index 339397d068..0000000000 --- a/src/northbridge/intel/sandybridge/iommu.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -#include -#include -#include -#include - -#include "sandybridge.h" - -void sandybridge_init_iommu(void) -{ - const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); - if (capid0_a & (1 << 23)) - return; - - /* setup BARs */ - MCHBAR32(0x5404) = IOMMU_BASE1 >> 32; - MCHBAR32(0x5400) = IOMMU_BASE1 | 1; - MCHBAR32(0x5414) = IOMMU_BASE2 >> 32; - MCHBAR32(0x5410) = IOMMU_BASE2 | 1; - - /* lock policies */ - write32((void *)(IOMMU_BASE1 + 0xff0), 0x80000000); - - const struct device *const azalia = pcidev_on_root(0x1b, 0); - if (azalia && azalia->enabled) { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x20000000); - write32((void *)(IOMMU_BASE2 + 0xff0), 0xa0000000); - } else { - write32((void *)(IOMMU_BASE2 + 0xff0), 0x80000000); - } -} diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 76b3088388..2cef5f2605 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Perform some early chipset initialization required * before RAM initialization can work */ - sandybridge_early_initialization(); - printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + systemagent_early_init(); + printk(BIOS_DEBUG, "Back from systemagent_early_init()\n"); s3resume = southbridge_detect_s3_resume(); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 77165f6931..88b7b56864 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -216,7 +216,7 @@ static inline void barrier(void) { asm("" ::: "memory"); } void intel_sandybridge_finalize_smm(void); #else /* !__SMM__ */ int bridge_silicon_revision(void); -void sandybridge_early_initialization(void); +void systemagent_early_init(void); void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 626310010c..7b98be28e4 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -364,8 +364,7 @@ void verstage_main(void) printk(BIOS_INFO, "Recovery requested (%x)\n", rv); save_if_needed(&ctx); extend_pcrs(&ctx); /* ignore failures */ - timestamp_add_now(TS_END_VBOOT); - return; + goto verstage_main_exit; } printk(BIOS_INFO, "Reboot requested (%x)\n", rv); @@ -447,6 +446,8 @@ void verstage_main(void) printk(BIOS_INFO, "Slot %c is selected\n", is_slot_a(&ctx) ? 'A' : 'B'); vboot_set_selected_region(region_device_region(&fw_main)); + + verstage_main_exit: vboot_finalize_work_context(&ctx); timestamp_add_now(TS_END_VBOOT); } diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/common/acpi/gpio_bank_lib.asl similarity index 100% rename from src/soc/amd/stoneyridge/acpi/gpio_lib.asl rename to src/soc/amd/common/acpi/gpio_bank_lib.asl diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/common/acpi/lpc.asl similarity index 100% rename from src/soc/amd/stoneyridge/acpi/lpc.asl rename to src/soc/amd/common/acpi/lpc.asl diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig new file mode 100644 index 0000000000..2b87f186fb --- /dev/null +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_ACPI + bool + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + default n + help + Select this option to use the AcpiMmio ACPI registers. diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index b67eadab8f..708631a5e9 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,2 +1,6 @@ -ramstage-y += halt.c -smm-y += halt.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c new file mode 100644 index 0000000000..e18933bb81 --- /dev/null +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void poweroff(void) +{ + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, + (SLP_TYP_S5 << SLP_TYP_SHIFT) | SLP_EN); + + /* + * Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM + * to transition to S5 state. If halt is called in SMM, then it prevents + * the SMI handler from being triggered and system never enters S5. + */ + if (!ENV_SMM) + halt(); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); + acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); + return pm1_sts; +} + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *const bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char *const pm1_sts_bits[16] = { + [0] = "TMROF", + [4] = "BMSTATUS", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_DEBUG, "PM1_STS: "); + print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return pm1_sts; +} + +static void log_pm1_status(uint16_t pm1_sts) +{ + if (!CONFIG(ELOG)) + return; + + if (pm1_sts & WAK_STS) + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); + + if (pm1_sts & PWRBTN_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + + if (pm1_sts & RTC_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + + if (pm1_sts & PCIEXPWAK_STS) + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); +} + +static void save_sws(uint16_t pm1_status) +{ + struct soc_power_reg *sws; + uint32_t reg32; + uint16_t reg16; + + sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); + if (sws == NULL) + return; + sws->pm1_sts = pm1_status; + sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); + reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); + acpi_write32(MMIO_ACPI_GPE0_STS, reg32); + sws->gpe0_sts = reg32; + sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); + reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + reg16 &= SLP_TYP; + sws->wake_from = reg16 >> SLP_TYP_SHIFT; +} + +void acpi_clear_pm1_status(void) +{ + uint16_t pm1_sts = reset_pm1_status(); + + save_sws(pm1_sts); + log_pm1_status(pm1_sts); + print_pm1_status(pm1_sts); +} + +int acpi_get_sleep_type(void) +{ + return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); +} + +int vboot_platform_is_resuming(void) +{ + if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS)) + return 0; + + return acpi_get_sleep_type() == ACPI_S3; +} + +/* If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. */ +void set_pm1cnt_s5(void) +{ + uint16_t pm1; + + pm1 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + pm1 &= ~SLP_TYP; + pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; + acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1); +} + +void vboot_platform_prepare_reboot(void) +{ + set_pm1cnt_s5(); +} + +void acpi_enable_sci(void) +{ + uint32_t pm1; + + pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); + pm1 |= ACPI_PM1_CNT_SCIEN; + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1); +} + +void acpi_disable_sci(void) +{ + uint32_t pm1; + + pm1 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); + pm1 &= ~ACPI_PM1_CNT_SCIEN; + acpi_write32(MMIO_ACPI_PM1_CNT_BLK, pm1); +} diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 7d4c4c5df1..edb3882e6f 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -67,38 +67,41 @@ void pm_io_write32(uint8_t reg, uint32_t value) /* smbus pci read/write - access registers at 0xfed80000 - currently unused */ +#if SUPPORTS_ACPIMMIO_SMI_BASE /* smi read/write - access registers at 0xfed80200 */ -uint8_t smi_read8(uint8_t offset) +uint8_t smi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMI_BASE + offset)); + return read8((void *)(ACPIMMIO_SMI_BASE + reg)); } -uint16_t smi_read16(uint8_t offset) +uint16_t smi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMI_BASE + offset)); + return read16((void *)(ACPIMMIO_SMI_BASE + reg)); } -uint32_t smi_read32(uint8_t offset) +uint32_t smi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SMI_BASE + offset)); + return read32((void *)(ACPIMMIO_SMI_BASE + reg)); } -void smi_write8(uint8_t offset, uint8_t value) +void smi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMI_BASE + offset), value); + write8((void *)(ACPIMMIO_SMI_BASE + reg), value); } -void smi_write16(uint8_t offset, uint16_t value) +void smi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMI_BASE + offset), value); + write16((void *)(ACPIMMIO_SMI_BASE + reg), value); } -void smi_write32(uint8_t offset, uint32_t value) +void smi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SMI_BASE + offset), value); + write32((void *)(ACPIMMIO_SMI_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_SMI_BASE */ +#if SUPPORTS_ACPIMMIO_PMIO_BASE /* pm read/write - access registers at 0xfed80300 */ u8 pm_read8(u8 reg) @@ -130,58 +133,60 @@ void pm_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_PMIO_BASE */ -/* pm2 read/write - access registers at 0xfed80400 - currently unused */ +#if SUPPORTS_ACPIMMIO_PMIO2_BASE +/* pm2 read/write - access registers at 0xfed80400 - currently unused by any soc */ +#endif +#if SUPPORTS_ACPIMMIO_BIOSRAM_BASE /* biosram read/write - access registers at 0xfed80500 */ -uint8_t biosram_read8(uint8_t offset) +uint8_t biosram_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + offset)); + return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); } -uint16_t biosram_read16(uint8_t offset) /* Must be 1 byte at a time */ +uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ { - int i; - uint16_t value = 0; - for (i = sizeof(value) - 1 ; i >= 0 ; i--) - value = (value << 8) | biosram_read8(offset + i); - return value; + return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); } -uint32_t biosram_read32(uint8_t offset) +uint32_t biosram_read32(uint8_t reg) { - uint32_t value = biosram_read16(offset + sizeof(uint16_t)) << 16; - return value | biosram_read16(offset); + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); } -void biosram_write8(uint8_t offset, uint8_t value) +void biosram_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_BIOSRAM_BASE + offset), value); + write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); } -void biosram_write16(uint8_t offset, uint16_t value) +void biosram_write16(uint8_t reg, uint16_t value) { - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } + biosram_write8(reg, value & 0xff); + value >>= 8; + biosram_write8(reg + sizeof(uint8_t), value & 0xff); } -void biosram_write32(uint8_t offset, uint32_t value) +void biosram_write32(uint8_t reg, uint32_t value) { - int i; - for (i = 0 ; i < sizeof(value) ; i++) { - biosram_write8(offset + i, value & 0xff); - value >>= 8; - } + biosram_write16(reg, value & 0xffff); + value >>= 16; + biosram_write16(reg + sizeof(uint16_t), value & 0xffff); } +#endif /* SUPPORTS_ACPIMMIO_BIOSRAM_BASE */ -/* cmosram read/write - access registers at 0xfed80600 - currently unused */ +#if SUPPORTS_ACPIMMIO_CMOSRAM_BASE +/* cmosram read/write - access registers at 0xfed80600 - currently unused by any soc */ +#endif -/* cmos read/write - access registers at 0xfed80700 - currently unused */ +#if SUPPORTS_ACPIMMIO_CMOS_BASE +/* cmos read/write - access registers at 0xfed80700 - currently unused by any soc */ +#endif +#if SUPPORTS_ACPIMMIO_ACPI_BASE /* acpi read/write - access registers at 0xfed80800 */ u8 acpi_read8(u8 reg) @@ -213,8 +218,10 @@ void acpi_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_ACPI_BASE */ -/* asf read/write - access registers at 0xfed80900 - not currently used */ +#if SUPPORTS_ACPIMMIO_ASF_BASE +/* asf read/write - access registers at 0xfed80900 */ u8 asf_read8(u8 reg) { @@ -235,8 +242,10 @@ void asf_write16(u8 reg, u16 value) { write16((void *)(ACPIMMIO_ASF_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_ASF_BASE */ -/* smbus read/write - access registers at 0xfed80a00 and ASF at 0xfed80900 */ +#if SUPPORTS_ACPIMMIO_SMBUS_BASE +/* smbus read/write - access registers at 0xfed80a00 */ u8 smbus_read8(u8 reg) { @@ -257,11 +266,17 @@ void smbus_write16(u8 reg, u16 value) { write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_SMBUS_BASE */ -/* wdt read/write - access registers at 0xfed80b00 - not currently used */ +#if SUPPORTS_ACPIMMIO_WDT_BASE +/* wdt read/write - access registers at 0xfed80b00 - not currently used by any soc */ +#endif -/* hpet read/write - access registers at 0xfed80c00 - not currently used */ +#if SUPPORTS_ACPIMMIO_HPET_BASE +/* hpet read/write - access registers at 0xfed80c00 - not currently used by any soc */ +#endif +#if SUPPORTS_ACPIMMIO_IOMUX_BASE /* iomux read/write - access registers at 0xfed80d00 */ u8 iomux_read8(u8 reg) @@ -293,7 +308,9 @@ void iomux_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_IOMUX_BASE */ +#if SUPPORTS_ACPIMMIO_MISC_BASE /* misc read/write - access registers at 0xfed80e00 */ u8 misc_read8(u8 reg) @@ -325,13 +342,25 @@ void misc_write32(u8 reg, u32 value) { write32((void *)(ACPIMMIO_MISC_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_MISC_BASE */ -/* dpvga read/write - access registers at 0xfed81400 - not currently used */ +#if SUPPORTS_ACPIMMIO_DPVGA_BASE +/* dpvga read/write - access registers at 0xfed81400 - not currently used by any soc */ +#endif -/* gpio bk 0 read/write - access registers at 0xfed81500 - not currently used */ -/* gpio bk 1 read/write - access registers at 0xfed81600 - not currently used */ -/* gpio bk 2 read/write - access registers at 0xfed81700 - not currently used */ +#if SUPPORTS_ACPIMMIO_GPIO0_BASE || SUPPORTS_ACPIMMIO_GPIO1_BASE \ + || SUPPORTS_ACPIMMIO_GPIO2_BASE +/* + * No helpers are currently in use however common/block//gpio.c accesses + * the registers directly. + */ +/* gpio bk 0 read/write - access registers at 0xfed81500 */ +/* gpio bk 1 read/write - access registers at 0xfed81600 */ +/* gpio bk 2 read/write - access registers at 0xfed81700 */ +#endif + +#if SUPPORTS_ACPIMMIO_XHCIPM_BASE /* xhci_pm read/write - access registers at 0xfed81c00 */ uint8_t xhci_pm_read8(uint8_t reg) @@ -363,10 +392,14 @@ void xhci_pm_write32(uint8_t reg, uint32_t value) { write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_XHCIPM_BASE */ -/* acdc_tmr read/write - access registers at 0xfed81d00 */ +#if SUPPORTS_ACPIMMIO_ACDCTMR_BASE +/* acdc_tmr read/write - access registers at 0xfed81d00 - not currently used by any soc */ +#endif -/* aoac read/write - access registers at 0xfed81e00 - not currently used */ +#if SUPPORTS_ACPIMMIO_AOAC_BASE +/* aoac read/write - access registers at 0xfed81e00 */ u8 aoac_read8(u8 reg) { @@ -377,3 +410,4 @@ void aoac_write8(u8 reg, u8 value) { write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); } +#endif /* SUPPORTS_ACPIMMIO_AOAC_BASE */ diff --git a/src/soc/amd/common/block/alink/Kconfig b/src/soc/amd/common/block/alink/Kconfig new file mode 100644 index 0000000000..75cf66f194 --- /dev/null +++ b/src/soc/amd/common/block/alink/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_ALINK + bool + default n + help + Select this option to access the FCH A-link configuration registers. diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc new file mode 100644 index 0000000000..720a7cbd82 --- /dev/null +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c diff --git a/src/soc/amd/common/block/alink/alink.c b/src/soc/amd/common/block/alink/alink.c new file mode 100644 index 0000000000..f481f6b340 --- /dev/null +++ b/src/soc/amd/common/block/alink/alink.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, + // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + + /* probably we dont have to do it again. */ + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +/* + * space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) +{ + u32 tmp; + + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} diff --git a/src/soc/amd/common/block/gpio_banks/Kconfig b/src/soc/amd/common/block/gpio_banks/Kconfig new file mode 100644 index 0000000000..115aa2cc52 --- /dev/null +++ b/src/soc/amd/common/block/gpio_banks/Kconfig @@ -0,0 +1,8 @@ +config SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + bool + depends on SOC_AMD_COMMON_BLOCK_ACPIMMIO + default n + help + Select this option to use the newer style banks of GPIO signals. + These are at offsets +0x1500, +0x1600, and +0x1700 from the AcpiMmio + base. diff --git a/src/soc/amd/common/block/gpio_banks/Makefile.inc b/src/soc/amd/common/block/gpio_banks/Makefile.inc new file mode 100644 index 0000000000..f1555b12b8 --- /dev/null +++ b/src/soc/amd/common/block/gpio_banks/Makefile.inc @@ -0,0 +1,6 @@ +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c new file mode 100644 index 0000000000..17e3de09e3 --- /dev/null +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -0,0 +1,310 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static int get_gpio_gevent(uint8_t gpio, const struct soc_amd_event *table, + size_t items) +{ + int i; + + for (i = 0; i < items; i++) { + if ((table + i)->gpio == gpio) + return (int)(table + i)->event; + } + return -1; +} + +static void mem_read_write32(uint32_t *address, uint32_t value, uint32_t mask) +{ + uint32_t reg32; + + value &= mask; + reg32 = read32(address); + reg32 &= ~mask; + reg32 |= value; + write32(address, reg32); +} + +static void program_smi(uint32_t flag, int gevent_num) +{ + uint32_t trigger; + + trigger = flag & FLAGS_TRIGGER_MASK; + /* + * Only level trigger is allowed for SMI. Trigger values are 0 + * through 3, with 0-1 being level trigger and 2-3 being edge + * trigger. GPIO_TRIGGER_EDGE_LOW is 2, so trigger has to be + * less than GPIO_TRIGGER_EDGE_LOW. + */ + assert(trigger < GPIO_TRIGGER_EDGE_LOW); + + if (trigger == GPIO_TRIGGER_LEVEL_HIGH) + configure_gevent_smi(gevent_num, SMI_MODE_SMI, + SMI_SCI_LVL_HIGH); + if (trigger == GPIO_TRIGGER_LEVEL_LOW) + configure_gevent_smi(gevent_num, SMI_MODE_SMI, + SMI_SCI_LVL_LOW); +} + +static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level) +{ + uint32_t trigger; + + trigger = flag & FLAGS_TRIGGER_MASK; + switch (trigger) { + case GPIO_TRIGGER_LEVEL_LOW: + *edge = SCI_TRIGGER_LEVEL; + *level = 0; + break; + case GPIO_TRIGGER_LEVEL_HIGH: + *edge = SCI_TRIGGER_LEVEL; + *level = 1; + break; + case GPIO_TRIGGER_EDGE_LOW: + *edge = SCI_TRIGGER_EDGE; + *level = 0; + break; + case GPIO_TRIGGER_EDGE_HIGH: + *edge = SCI_TRIGGER_EDGE; + *level = 1; + break; + default: + break; + } +} + +uintptr_t gpio_get_address(gpio_t gpio_num) +{ + uintptr_t gpio_address; + + if (gpio_num < 64) + gpio_address = GPIO_BANK0_CONTROL(gpio_num); + else if (gpio_num < 128) + gpio_address = GPIO_BANK1_CONTROL(gpio_num); + else + gpio_address = GPIO_BANK2_CONTROL(gpio_num); + + return gpio_address; +} + +int gpio_get(gpio_t gpio_num) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + + return !!(reg & GPIO_PIN_STS); +} + +void gpio_set(gpio_t gpio_num, int value) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + reg &= ~GPIO_OUTPUT_MASK; + reg |= !!value << GPIO_OUTPUT_SHIFT; + write32((void *)gpio_address, reg); +} + +void gpio_input_pulldown(gpio_t gpio_num) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + reg &= ~GPIO_PULLUP_ENABLE; + reg |= GPIO_PULLDOWN_ENABLE; + write32((void *)gpio_address, reg); +} + +void gpio_input_pullup(gpio_t gpio_num) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + reg &= ~GPIO_PULLDOWN_ENABLE; + reg |= GPIO_PULLUP_ENABLE; + write32((void *)gpio_address, reg); +} + +void gpio_input(gpio_t gpio_num) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + reg &= ~GPIO_OUTPUT_ENABLE; + write32((void *)gpio_address, reg); +} + +void gpio_output(gpio_t gpio_num, int value) +{ + uint32_t reg; + uintptr_t gpio_address = gpio_get_address(gpio_num); + + reg = read32((void *)gpio_address); + reg |= GPIO_OUTPUT_ENABLE; + write32((void *)gpio_address, reg); + gpio_set(gpio_num, value); +} + +const char *gpio_acpi_path(gpio_t gpio) +{ + return "\\_SB.GPIO"; +} + +uint16_t gpio_acpi_pin(gpio_t gpio) +{ + return gpio; +} + +__weak void soc_gpio_hook(uint8_t gpio, uint8_t mux) {} + +void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) +{ + uint32_t *gpio_ptr, *inter_master; + uint32_t control, control_flags, edge_level, direction; + uint32_t mask, bit_edge, bit_level; + uint8_t mux, index, gpio; + int gevent_num; + const struct soc_amd_event *gev_tbl; + size_t gev_items; + + inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE + + GPIO_MASTER_SWITCH); + direction = 0; + edge_level = 0; + mask = 0; + + /* + * Disable blocking wake/interrupt status generation while updating + * debounce registers. Otherwise when a debounce register is updated + * the whole GPIO controller will zero out all interrupt enable status + * bits while the delay happens. This could cause us to drop the bits + * due to the read-modify-write that happens on each register. + * + * Additionally disable interrupt generation so we don't get any + * spurious interrupts while updating the registers. + */ + mem_read_write32(inter_master, 0, GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); + + soc_get_gpio_event_table(&gev_tbl, &gev_items); + + for (index = 0; index < size; index++) { + gpio = gpio_list_ptr[index].gpio; + mux = gpio_list_ptr[index].function; + control = gpio_list_ptr[index].control; + control_flags = gpio_list_ptr[index].flags; + + iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); + iomux_read8(gpio); /* Flush posted write */ + + soc_gpio_hook(gpio, mux); + + gpio_ptr = (uint32_t *)gpio_get_address(gpio); + + if (control_flags & GPIO_SPECIAL_FLAG) { + gevent_num = get_gpio_gevent(gpio, gev_tbl, gev_items); + if (gevent_num < 0) { + printk(BIOS_WARNING, "Warning: GPIO pin %d has" + " no associated gevent!\n", gpio); + continue; + } + switch (control_flags & GPIO_SPECIAL_MASK) { + case GPIO_DEBOUNCE_FLAG: + mem_read_write32(gpio_ptr, control, + GPIO_DEBOUNCE_MASK); + break; + case GPIO_WAKE_FLAG: + mem_read_write32(gpio_ptr, control, + INT_WAKE_MASK); + break; + case GPIO_INT_FLAG: + mem_read_write32(gpio_ptr, control, + AMD_GPIO_CONTROL_MASK); + break; + case GPIO_SMI_FLAG: + mem_read_write32(gpio_ptr, control, + INT_SCI_SMI_MASK); + program_smi(control_flags, gevent_num); + break; + case GPIO_SCI_FLAG: + mem_read_write32(gpio_ptr, control, + INT_SCI_SMI_MASK); + get_sci_config_bits(control_flags, &bit_edge, + &bit_level); + edge_level |= bit_edge << gevent_num; + direction |= bit_level << gevent_num; + mask |= (1 << gevent_num); + soc_route_sci(gevent_num); + break; + default: + printk(BIOS_WARNING, "Error, flags 0x%08x\n", + control_flags); + break; + } + } else { + mem_read_write32(gpio_ptr, control, + AMD_GPIO_CONTROL_MASK); + } + } + + /* + * Re-enable interrupt status generation. + * + * We leave MASK_STATUS disabled because the kernel may reconfigure the + * debounce registers while the drivers load. This will cause interrupts + * to be missed during boot. + */ + mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); + + /* Set all SCI trigger direction (high/low) */ + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), + direction, mask); + + /* Set all SCI trigger level (edge/level) */ + mem_read_write32((uint32_t *) + (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), + edge_level, mask); +} + +int gpio_interrupt_status(gpio_t gpio) +{ + uintptr_t gpio_address = gpio_get_address(gpio); + uint32_t reg = read32((void *)gpio_address); + + if (reg & GPIO_INT_STATUS) { + /* Clear interrupt status, preserve wake status */ + reg &= ~GPIO_WAKE_STATUS; + write32((void *)gpio_address, reg); + return 1; + } + + return 0; +} diff --git a/src/soc/amd/common/block/hda/Kconfig b/src/soc/amd/common/block/hda/Kconfig new file mode 100644 index 0000000000..775de2fd8c --- /dev/null +++ b/src/soc/amd/common/block/hda/Kconfig @@ -0,0 +1,6 @@ +config SOC_AMD_COMMON_BLOCK_HDA + bool + default n + help + Select this option to use AMD common High Definition Audio + driver support. diff --git a/src/soc/amd/common/block/hda/Makefile.inc b/src/soc/amd/common/block/hda/Makefile.inc new file mode 100644 index 0000000000..d6f1b3275a --- /dev/null +++ b/src/soc/amd/common/block/hda/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += hda.c diff --git a/src/soc/amd/stoneyridge/hda.c b/src/soc/amd/common/block/hda/hda.c similarity index 97% rename from src/soc/amd/stoneyridge/hda.c rename to src/soc/amd/common/block/hda/hda.c index 0ab2f91ee7..f4ea732fba 100644 --- a/src/soc/amd/stoneyridge/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -17,7 +17,6 @@ #include #include #include -#include static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h new file mode 100644 index 0000000000..cf266ed7d8 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ACPI_H__ +#define __AMDBLOCKS_ACPI_H__ + +#include + +/* ACPI MMIO registers 0xfed80800 */ +#define MMIO_ACPI_PM1_STS 0x00 +#define MMIO_ACPI_PM1_EN 0x02 +#define MMIO_ACPI_PM1_CNT_BLK 0x04 + /* sleep types defined in arch/x86/include/arch/acpi.h */ +#define ACPI_PM1_CNT_SCIEN BIT(0) +#define MMIO_ACPI_PM_TMR_BLK 0x08 +#define MMIO_ACPI_CPU_CONTROL 0x0c +#define MMIO_ACPI_GPE0_STS 0x14 +#define MMIO_ACPI_GPE0_EN 0x18 + +void acpi_clear_pm1_status(void); + +/* + * If a system reset is about to be requested, modify the PM1 register so it + * will never be misinterpreted as an S3 resume. + */ +void set_pm1cnt_s5(void); +void acpi_enable_sci(void); +void acpi_disable_sci(void); + +#endif /* __AMDBLOCKS_ACPI_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index e1cf7cbdc2..32da867137 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,83 +18,250 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +/* iomap.h must indicate if the device uses a block, optional if unused. */ +#include +#ifndef SUPPORTS_ACPIMMIO_SMI_BASE + #define SUPPORTS_ACPIMMIO_SMI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO_BASE + #define SUPPORTS_ACPIMMIO_PMIO_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_PMIO2_BASE + #define SUPPORTS_ACPIMMIO_PMIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_BIOSRAM_BASE + #define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOSRAM_BASE + #define SUPPORTS_ACPIMMIO_CMOSRAM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_CMOS_BASE + #define SUPPORTS_ACPIMMIO_CMOS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACPI_BASE + #define SUPPORTS_ACPIMMIO_ACPI_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ASF_BASE + #define SUPPORTS_ACPIMMIO_ASF_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_SMBUS_BASE + #define SUPPORTS_ACPIMMIO_SMBUS_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_WDT_BASE + #define SUPPORTS_ACPIMMIO_WDT_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_HPET_BASE + #define SUPPORTS_ACPIMMIO_HPET_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_IOMUX_BASE + #define SUPPORTS_ACPIMMIO_IOMUX_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_MISC_BASE + #define SUPPORTS_ACPIMMIO_MISC_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_DPVGA_BASE + #define SUPPORTS_ACPIMMIO_DPVGA_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO0_BASE + #define SUPPORTS_ACPIMMIO_GPIO0_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO1_BASE + #define SUPPORTS_ACPIMMIO_GPIO1_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_GPIO2_BASE + #define SUPPORTS_ACPIMMIO_GPIO2_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_XHCIPM_BASE + #define SUPPORTS_ACPIMMIO_XHCIPM_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_ACDCTMR_BASE + #define SUPPORTS_ACPIMMIO_ACDCTMR_BASE 0 +#endif +#ifndef SUPPORTS_ACPIMMIO_AOAC_BASE + #define SUPPORTS_ACPIMMIO_AOAC_BASE 0 +#endif + +/* + * The following AcpiMmio register block mapping represents definitions + * that have been documented in AMD publications. All blocks aren't + * implemented in all products, so the caller should be careful not to + * inadvertently access a non-existent block. The definitions within + * each block are also subject to change across products. Please refer + * to the appropriate RRG, the BKDG, or PPR for the product. + * + * The base address is configurable in older products, but defaults to + * 0xfed80000. The address is fixed at 0xfed80000 in newer products. + * + * +---------------------------------------------------------------------------+ + * |0x000 SMBus PCI space | + * | * Dual-mapped to PCI configuration header of D14F0 | + * +---------------------------------------------------------------------------+ + * |0x100 GPIO configuration registers | + * | * old style, never implemented with newer style | + * +---------------------------------------------------------------------------+ + * |0x200 SMI configuration registers | + * +---------------------------------------------------------------------------+ + * |0x300 Power Management registers | + * | * Dual-mapped via IO Index/Data 0xcd6/0xcd7 (byte access only) | + * +---------------------------------------------------------------------------+ + * |0x400 Power Management 2 registers | + * +---------------------------------------------------------------------------+ + * |0x500 BIOS RAM | + * | * General-purpose storage in S3 domain | + * | * Byte access only | + * +---------------------------------------------------------------------------+ + * |0x600 CMOS RAM | + * | * Dual-mapped to storage at Alt RTC Index/Data (0x72/0x73) | + * | * Byte access only | + * +---------------------------------------------------------------------------+ + * |0x700 CMOS | + * | * Dual-mapped to storage at RTC Index/Data (0x70/0x71) | + * | * Byte access only | + * +---------------------------------------------------------------------------+ + * |0x800 Standard ACPI registers | + * | * Dual-mapped to I/O ACPI registers | + * +---------------------------------------------------------------------------+ + * |0x900 ASF controller registers | + * | * Dual-mapped to I/O ASF controller registers | + * +---------------------------------------------------------------------------+ + * |0xa00 SMBus controller registers | + * | * Dual-mapped to I/O SMBus controller registers | + * +---------------------------------------------------------------------------+ + * |0xb00 WDT registers | + * | * Dual-mapped to WDT registers, typ. enabled at 0xfeb00000 | + * +---------------------------------------------------------------------------+ + * |0xc00 HPET registers | + * | * Dual-mapped to HPET registers, typ. enabled at 0xfed00000 | + * +---------------------------------------------------------------------------+ + * |0xd00 MUX configuration registers for GPIO signals | + * +---------------------------------------------------------------------------+ + * |0xe00 Miscellaneous registers | + * +---------------------------------------------------------------------------+ + * |0x1000 Serial debug bus | + * +---------------------------------------------------------------------------+ + * |0x1400 DP-VGA | + * +---------------------------------------------------------------------------+ + * |0x1500 GPIO configuration registers bank 0 | + * | * new style, never implemented with older style | + * +---------------------------------------------------------------------------+ + * |0x1600 GPIO configuration registers bank 1 | + * | * new style, never implemented with older style | + * +---------------------------------------------------------------------------+ + * |0x1700 GPIO configuration registers bank 2 | + * | * new style, never implemented with older style | + * +---------------------------------------------------------------------------+ + * |0x1c00 xHCI Power Management registers | + * +---------------------------------------------------------------------------+ + * |0x1d00 Wake device (AC DC timer) | + * +---------------------------------------------------------------------------+ + * |0x1e00 Always On Always Connect registers | + * +---------------------------------------------------------------------------+ + */ + +/* Enable the AcpiMmio range at 0xfed80000 */ void enable_acpimmio_decode(void); + +/* Access PM registers using IO cycles */ uint8_t pm_io_read8(uint8_t reg); uint16_t pm_io_read16(uint8_t reg); uint32_t pm_io_read32(uint8_t reg); void pm_io_write8(uint8_t reg, uint8_t value); void pm_io_write16(uint8_t reg, uint16_t value); void pm_io_write32(uint8_t reg, uint32_t value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); + +/* Access SMI registers at 0xfed80100 */ +uint8_t smi_read8(uint8_t reg); +uint16_t smi_read16(uint8_t reg); +uint32_t smi_read32(uint8_t reg); +void smi_write8(uint8_t reg, uint8_t value); +void smi_write16(uint8_t reg, uint16_t value); +void smi_write32(uint8_t reg, uint32_t value); + +/* Access Power Management registers at 0xfed80300 */ uint8_t pm_read8(uint8_t reg); uint16_t pm_read16(uint8_t reg); uint32_t pm_read32(uint8_t reg); void pm_write8(uint8_t reg, uint8_t value); void pm_write16(uint8_t reg, uint16_t value); void pm_write32(uint8_t reg, uint32_t value); + +/* Access Power Management 2 registers at 0xfed80400 */ uint8_t pm2_read8(uint8_t reg); uint16_t pm2_read16(uint8_t reg); uint32_t pm2_read32(uint8_t reg); void pm2_write8(uint8_t reg, uint8_t value); void pm2_write16(uint8_t reg, uint16_t value); void pm2_write32(uint8_t reg, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -uint16_t biosram_read16(uint8_t offset); -uint32_t biosram_read32(uint8_t offset); -void biosram_write16(uint8_t offset, uint16_t value); -void biosram_write32(uint8_t offset, uint32_t value); + +/* Access BIOS RAM storage at 0xfed80500 */ +uint8_t biosram_read8(uint8_t reg); +uint16_t biosram_read16(uint8_t reg); +uint32_t biosram_read32(uint8_t reg); +void biosram_write8(uint8_t reg, uint8_t value); +void biosram_write16(uint8_t reg, uint16_t value); +void biosram_write32(uint8_t reg, uint32_t value); + +/* Access ACPI registers at 0xfed80800 */ uint8_t acpi_read8(uint8_t reg); uint16_t acpi_read16(uint8_t reg); uint32_t acpi_read32(uint8_t reg); void acpi_write8(uint8_t reg, uint8_t value); void acpi_write16(uint8_t reg, uint16_t value); void acpi_write32(uint8_t reg, uint32_t value); + +/* Access ASF controller registers at 0xfed80900 */ uint8_t asf_read8(uint8_t reg); uint16_t asf_read16(uint8_t reg); -uint32_t asf_read32(uint8_t reg); void asf_write8(uint8_t reg, uint8_t value); void asf_write16(uint8_t reg, uint16_t value); -void asf_write32(uint8_t reg, uint32_t value); + +/* Access SMBus controller registers at 0xfed80a00 */ uint8_t smbus_read8(uint8_t reg); uint16_t smbus_read16(uint8_t reg); void smbus_write8(uint8_t reg, uint8_t value); void smbus_write16(uint8_t reg, uint16_t value); + +/* Access WDT registers at 0xfed80b00 */ uint8_t wdt_read8(uint8_t reg); uint16_t wdt_read16(uint8_t reg); uint32_t wdt_read32(uint8_t reg); void wdt_write8(uint8_t reg, uint8_t value); void wdt_write16(uint8_t reg, uint16_t value); void wdt_write32(uint8_t reg, uint32_t value); + +/* Access HPET registers at 0xfed80c00 */ uint8_t hpet_read8(uint8_t reg); uint16_t hpet_read16(uint8_t reg); uint32_t hpet_read32(uint8_t reg); void hpet_write8(uint8_t reg, uint8_t value); void hpet_write16(uint8_t reg, uint16_t value); void hpet_write32(uint8_t reg, uint32_t value); + +/* Access GPIO MUX registers at 0xfed80d00 */ uint8_t iomux_read8(uint8_t reg); uint16_t iomux_read16(uint8_t reg); uint32_t iomux_read32(uint8_t reg); void iomux_write8(uint8_t reg, uint8_t value); void iomux_write16(uint8_t reg, uint16_t value); void iomux_write32(uint8_t reg, uint32_t value); + +/* Access Miscellaneous registers at 0xfed80e00 */ uint8_t misc_read8(uint8_t reg); uint16_t misc_read16(uint8_t reg); uint32_t misc_read32(uint8_t reg); void misc_write8(uint8_t reg, uint8_t value); void misc_write16(uint8_t reg, uint16_t value); void misc_write32(uint8_t reg, uint32_t value); + +/* Access xHCI Power Management registers at 0xfed81c00 */ uint8_t xhci_pm_read8(uint8_t reg); uint16_t xhci_pm_read16(uint8_t reg); uint32_t xhci_pm_read32(uint8_t reg); void xhci_pm_write8(uint8_t reg, uint8_t value); void xhci_pm_write16(uint8_t reg, uint16_t value); void xhci_pm_write32(uint8_t reg, uint32_t value); + +/* Access Always On Always Connect registers at 0xfed81e00 */ uint8_t aoac_read8(uint8_t reg); void aoac_write8(uint8_t reg, uint8_t value); diff --git a/src/soc/amd/common/block/include/amdblocks/alink.h b/src/soc/amd/common/block/include/amdblocks/alink.h new file mode 100644 index 0000000000..a6f748b809 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/alink.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_ALINK_H__ +#define __AMDBLOCKS_ALINK_H__ + +#include + +#define AB_INDX 0xcd8 +#define AB_DATA (AB_INDX + 4) + +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /* c or p? */, u32 axindc, u32 mask, u32 val); + +#endif /* __AMDBLOCKS_ALINK_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h new file mode 100644 index 0000000000..da841347fb --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCK_GPIO_BANKS_H__ +#define __AMDBLOCK_GPIO_BANKS_H__ + +#include +#include + +struct soc_amd_gpio { + uint8_t gpio; + uint8_t function; + uint32_t control; + uint32_t flags; +}; + +struct soc_amd_event { + uint8_t gpio; + uint8_t event; +}; + +#define GPIO_BANK0_CONTROL(gpio) (ACPIMMIO_GPIO0_BASE + ((gpio) * 4)) +#define GPIO_BANK1_CONTROL(gpio) (ACPIMMIO_GPIO1_BASE + (((gpio) - 64) * 4)) +#define GPIO_BANK2_CONTROL(gpio) (ACPIMMIO_GPIO2_BASE + (((gpio) - 128) * 4)) + +#define GPIO_MASTER_SWITCH 0xFC +#define GPIO_MASK_STS_EN BIT(28) +#define GPIO_INTERRUPT_EN BIT(30) + +#define GPIO_PIN_IN (1 << 0) /* for byte access */ +#define GPIO_PIN_OUT (1 << 6) /* for byte access */ + +#define GPIO_EDGE_TRIG (0 << 8) +#define GPIO_LEVEL_TRIG (1 << 8) +#define GPIO_TRIGGER_MASK (1 << 8) + +#define GPIO_ACTIVE_HIGH (0 << 9) +#define GPIO_ACTIVE_LOW (1 << 9) +#define GPIO_ACTIVE_BOTH (2 << 9) +#define GPIO_ACTIVE_MASK (3 << 9) + +#define GPIO_INT_STATUS_EN (1 << 11) +#define GPIO_INT_DELIVERY_EN (1 << 12) +#define GPIO_INTERRUPT_MASK (3 << 11) +#define GPIO_S0I3_WAKE_EN (1 << 13) +#define GPIO_S3_WAKE_EN (1 << 14) +#define GPIO_S4_S5_WAKE_EN (1 << 15) + +#define GPIO_PIN_STS (1 << 16) +#define GPIO_PULLUP_ENABLE (1 << 20) +#define GPIO_PULLDOWN_ENABLE (1 << 21) +#define GPIO_OUTPUT_SHIFT 22 +#define GPIO_OUTPUT_MASK (1 << GPIO_OUTPUT_SHIFT) +#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) +#define GPIO_OUTPUT_ENABLE (1 << 23) + +#define GPIO_INT_STATUS (1 << 28) +#define GPIO_WAKE_STATUS (1 << 29) + +enum { + GEVENT_0, + GEVENT_1, + GEVENT_2, + GEVENT_3, + GEVENT_4, + GEVENT_5, + GEVENT_6, + GEVENT_7, + GEVENT_8, + GEVENT_9, + GEVENT_10, + GEVENT_11, + GEVENT_12, + GEVENT_13, + GEVENT_14, + GEVENT_15, + GEVENT_16, + GEVENT_17, + GEVENT_18, + GEVENT_19, + GEVENT_20, + GEVENT_21, + GEVENT_22, + GEVENT_23, + GEVENT_24, + GEVENT_25, + GEVENT_26, + GEVENT_27, + GEVENT_28, + GEVENT_29, + GEVENT_30, + GEVENT_31, +}; + +#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) +#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE + +#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE +#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE +#define GPIO_PULL_PULL_NONE 0 + +#define AMD_GPIO_CONTROL_MASK 0x00f4ff00 +#define AMD_GPIO_MUX_MASK 0x03 + +/* Definitions for PAD_INT. */ +#define GPIO_INT_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_EDGE_TRIG) +#define GPIO_INT_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_EDGE_TRIG) +#define GPIO_INT_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_EDGE_TRIG) +#define GPIO_INT_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_LEVEL_TRIG) +#define GPIO_INT_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_LEVEL_TRIG) + +enum { + GPIO_TRIGGER_LEVEL_LOW, + GPIO_TRIGGER_LEVEL_HIGH, + GPIO_TRIGGER_EDGE_LOW, + GPIO_TRIGGER_EDGE_HIGH, +}; + +#define GPIO_TRIGGER_INVALID -1 +#define SCI_TRIGGER_EDGE 0 +#define SCI_TRIGGER_LEVEL 1 + +#define GPIO_SPECIAL_FLAG (1 << 31) +#define GPIO_DEBOUNCE_FLAG (1 << 30) +#define GPIO_WAKE_FLAG (1 << 29) +#define GPIO_INT_FLAG (1 << 28) +#define GPIO_SMI_FLAG (1 << 27) +#define GPIO_SCI_FLAG (1 << 26) +#define GPIO_FLAG_DEBOUNCE (GPIO_SPECIAL_FLAG | GPIO_DEBOUNCE_FLAG) +#define GPIO_FLAG_WAKE (GPIO_SPECIAL_FLAG | GPIO_WAKE_FLAG) +#define GPIO_FLAG_INT (GPIO_SPECIAL_FLAG | GPIO_INT_FLAG) +#define GPIO_FLAG_SCI (GPIO_SPECIAL_FLAG | GPIO_SCI_FLAG) +#define GPIO_FLAG_SMI (GPIO_SPECIAL_FLAG | GPIO_SMI_FLAG) + +#define FLAGS_TRIGGER_MASK 0x00000003 +#define GPIO_SPECIAL_MASK 0x7c000000 +#define GPIO_DEBOUNCE_MASK 0x000000ff +#define INT_TRIGGER_MASK 0x00000700 +#define INT_WAKE_MASK 0x0000e700 +#define INT_SCI_SMI_MASK 0x00f40000 + +#define IN_GLITCH_SHIFT 5 +#define GLITCH_LOW 1 +#define GLITCH_HIGH 2 +#define GLITCH_NONE 3 +#define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) +#define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) +#define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) + +#define GPIO_TIMEBASE_61uS 0 +#define GPIO_TIMEBASE_183uS (1 << 4) +#define GPIO_TIMEBASE_15560uS (1 << 7) +#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ + GPIO_TIMEBASE_15560uS) +#define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) +#define GPIO_IN_60uS (1 | GPIO_TIMEBASE_61uS) +#define GPIO_IN_120uS (2 | GPIO_TIMEBASE_61uS) +#define GPIO_IN_200uS (3 | GPIO_TIMEBASE_61uS) +#define GPIO_IN_500uS (8 | GPIO_TIMEBASE_61uS) +#define GPIO_IN_1mS (5 | GPIO_TIMEBASE_183uS) +#define GPIO_IN_2mS (11 | GPIO_TIMEBASE_183uS) +#define GPIO_IN_15mS (1 | GPIO_TIMEBASE_15560uS) +#define GPIO_IN_50mS (3 | GPIO_TIMEBASE_15560uS) +#define GPIO_IN_100mS (6 | GPIO_TIMEBASE_15560uS) +#define GPIO_IN_200mS (13 | GPIO_TIMEBASE_15560uS) +#define GPIO_IN_500mS (8 | GPIO_TIMEBASE_62440uS) + +#define GPIO_EVENT_INT_STATUS GPIO_INT_STATUS_EN +#define GPIO_EVENT_INT_DELIVER GPIO_INT_DELIVERY_EN +#define GPIO_EVENT_INT_STATUS_DELIVER (GPIO_INT_STATUS_EN | \ + GPIO_INT_DELIVERY_EN) +#define GPIO_WAKE_S0i3 (1 << 13) +#define GPIO_WAKE_S3 (1 << 14) +#define GPIO_WAKE_S4_S5 (1 << 15) +#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) +#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) + +/* + * Several macros are available to declare programming of GPIO pins, and if + * needed, more than 1 macro can be used for any pin. However, some macros + * will have no effect if combined. For example debounce only affects input + * or one of the interrupts. Some macros should not be combined, such as SMI + * and regular interrupt. The defined macros and their parameters are: + * PAD_NF Define native alternate function for the pin. + * pin the pin to be programmed + * function the native function + * pull pull up, pull down or no pull + * PAD_GPI The pin is a GPIO input + * pin the pin to be programmed + * pull pull up, pull down or no pull + * PAD_GPO The pin is a GPIO output + * pin the pin to be programmed + * direction high or low + * PAD_INT The pin is regular interrupt that works while booting + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * action STATUS, DELIVER, STATUS_DELIVER + * PAD_SCI The pin is a SCI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH + * PAD_SMI The pin is a SMI source + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH + * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI + * pin the pin to be programmed + * pull pull up, pull down or no pull + * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES + * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) + * PAD_DEBOUNCE The input or interrupt will be debounced, invalid after + * PAD_NF + * pin the pin to be programmed + * debounce_type preserve low glitch, preserve high glitch, no glitch + * debounce_time the debounce time + */ + +/* Native function pad configuration */ +#define PAD_NF(pin, func, pull) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## func, \ + .control = GPIO_PULL ## _ ## pull, \ + .flags = 0 } +/* General purpose input pad configuration */ +#define PAD_GPI(pin, pull) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = GPIO_PULL ## _ ## pull, \ + .flags = 0 } +/* General purpose output pad configuration */ +#define PAD_GPO(pin, direction) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = GPIO_OUTPUT ## _OUT_ ## direction, \ + .flags = 0 } +/* Auxiliary macro for legacy interrupt and wake */ +#define PAD_AUX1(pull, trigger) (GPIO_PULL ## _ ## pull | \ + GPIO_INT ## _ ## trigger) +/* Legacy interrupt pad configuration */ +#define PAD_INT(pin, pull, trigger, action) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = (PAD_AUX1(pull, trigger) | \ + GPIO_EVENT_INT ## _ ## action), \ + .flags = GPIO_FLAG_INT } +/* Auxiliary macro for SCI and SMI */ +#define PAD_AUX2(trigger, flag) (GPIO_TRIGGER ## _ ## trigger | flag) +/* SCI pad configuration */ +#define PAD_SCI(pin, pull, trigger) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = GPIO_PULL ## _ ## pull, \ + .flags = PAD_AUX2(trigger, GPIO_FLAG_SCI) } +/* SMI pad configuration */ +#define PAD_SMI(pin, pull, trigger) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = GPIO_PULL ## _ ## pull, \ + .flags = PAD_AUX2(trigger, GPIO_FLAG_SMI) } +/* WAKE pad configuration */ +#define PAD_WAKE(pin, pull, trigger, type) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = (PAD_AUX1(pull, trigger) | \ + GPIO_WAKE ## _ ## type), \ + .flags = GPIO_FLAG_WAKE } +/* pin debounce configuration */ +#define PAD_DEBOUNCE(pin, type, time) \ + { .gpio = (pin), \ + .function = pin ## _IOMUX_ ## GPIOxx, \ + .control = (GPIO_IN ## _ ## type | GPIO_IN ## _ ## time), \ + .flags = GPIO_FLAG_DEBOUNCE } + +typedef uint32_t gpio_t; + +/* Get the address of the control register of a particular pin */ +uintptr_t gpio_get_address(gpio_t gpio_num); + +/** + * @brief program a particular set of GPIO + * + * @param gpio_list_ptr = pointer to array of gpio configurations + * @param size = number of entries in array + * + * @return none + */ +void program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); +/* Return the interrupt status and clear if set. */ +int gpio_interrupt_status(gpio_t gpio); +/* Implemented by soc, provides table of avaialable GPIO mapping to Gevents */ +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items); +/* May be implemented by soc to handle special cases */ +void soc_gpio_hook(uint8_t gpio, uint8_t mux); + +#endif /* __AMDBLOCK_GPIO_BANKS_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h new file mode 100644 index 0000000000..7b33d7ad11 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_LPC_H__ +#define __AMDBLOCKS_LPC_H__ + +#include + +/* PCI registers for D14F3 */ +#define LPC_PCI_CONTROL 0x40 +#define LEGACY_DMA_EN BIT(2) + +#define LPC_IO_PORT_DECODE_ENABLE 0x44 +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) + +#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 +#define LPC_WIDEIO2_ENABLE BIT(25) +#define LPC_WIDEIO1_ENABLE BIT(24) +#define DECODE_IO_PORT_ENABLE6 BIT(23) +#define DECODE_IO_PORT_ENABLE5 BIT(22) +#define DECODE_IO_PORT_ENABLE4 BIT(21) +#define DECODE_MEM_PORT_ENABLE1 BIT(20) +#define DECODE_IO_PORT_ENABLE3 BIT(19) +#define DECODE_IO_PORT_ENABLE2 BIT(18) +#define DECODE_IO_PORT_ENABLE1 BIT(17) +#define DECODE_IO_PORT_ENABLE0 BIT(16) +#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) +#define LPC_DECODE_RTC_IO_ENABLE BIT(6) +#define DECODE_MEM_PORT_ENABLE0 BIT(5) +#define LPC_WIDEIO0_ENABLE BIT(2) +#define DECODE_ALTERNATE_SIO_ENABLE BIT(1) +#define DECODE_SIO_ENABLE BIT(0) +#define WIDEIO_RANGE_ERROR -1 + +/* Assuming word access to higher word (register 0x4a) */ +#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a +#define LPC_WIDEIO2_ENABLE_H BIT(9) +#define LPC_WIDEIO1_ENABLE_H BIT(8) +#define DECODE_IO_PORT_ENABLE6_H BIT(7) +#define DECODE_IO_PORT_ENABLE5_H BIT(6) +#define DECODE_IO_PORT_ENABLE4_H BIT(5) +#define DECODE_IO_PORT_ENABLE3_H BIT(3) +#define DECODE_IO_PORT_ENABLE2_H BIT(2) +#define DECODE_IO_PORT_ENABLE1_H BIT(1) +#define DECODE_IO_PORT_ENABLE0_H BIT(0) + +#define LPC_MEM_PORT1 0x4c +#define LPC_MEM_PORT0 0x60 + +/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. + For ease of access, each sub-register is declared separetely. */ +#define LPC_WIDEIO_GENERIC_PORT 0x64 +#define LPC_WIDEIO1_GENERIC_PORT 0x66 +#define ROM_ADDRESS_RANGE1_START 0x68 +#define ROM_ADDRESS_RANGE1_END 0x6a +#define ROM_ADDRESS_RANGE2_START 0x6c +#define ROM_ADDRESS_RANGE2_END 0x6e + +#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 +#define LPC_ALT_WIDEIO2_ENABLE BIT(3) +#define LPC_ALT_WIDEIO1_ENABLE BIT(2) +#define LPC_ALT_WIDEIO0_ENABLE BIT(0) + +#define LPC_MISC_CONTROL_BITS 0x78 +#define LPC_NOHOG BIT(0) + +#define LPC_TRUSTED_PLATFORM_MODULE 0x7c +#define TPM_12_EN BIT(0) +#define TPM_LEGACY_EN BIT(2) + +#define LPC_WIDEIO2_GENERIC_PORT 0x90 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ABORT_ENABLE BIT(2) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_ROM_ALT_ENABLE BIT(0) +#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) + +/* LPC register 0xb8 is DWORD, here there are definitions for byte + access. For example, bits 31-24 are accessed through byte access + at register 0xbb. */ +#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 +#define SPI_FROM_HOST_PREFETCH_EN BIT(24) +#define SPI_FROM_USB_PREFETCH_EN BIT(23) + +#define LPC_HOST_CONTROL 0xbb +#define PREFETCH_EN_SPI_FROM_HOST BIT(0) +#define T_START_ENH BIT(3) + +/* LPC is typically enabled very early, but this function is last opportunity */ +void soc_late_lpc_bridge_enable(void); +void lpc_enable_port80(void); +void lpc_enable_pci_port80(void); +void lpc_enable_decode(uint32_t decodes); +uintptr_t lpc_spibase(void); +void lpc_tpm_decode(void); +void lpc_tpm_decode_spi(void); +void lpc_enable_rom(void); +void lpc_enable_spi_prefetch(void); + +/** + * @brief Find the size of a particular wide IO + * + * @param index = index of desired wide IO + * + * @return size of desired wide IO + */ +uint16_t lpc_wideio_size(int index); +/** + * @brief Identify if any LPC wide IO is covering the IO range + * + * @param start = start of IO range + * @param size = size of IO range + * + * @return Index of wide IO covering the range or error + */ +int lpc_find_wideio_range(uint16_t start, uint16_t size); +/** + * @brief Program a LPC wide IO to support an IO range + * + * @param start = start of range to be routed through wide IO + * @param size = size of range to be routed through wide IO + * + * @return Index of wide IO register used or error + */ +int lpc_set_wideio_range(uint16_t start, uint16_t size); + +uintptr_t lpc_get_spibase(void); +void lpc_set_spibase(uint32_t base, uint32_t enable); + +#endif /* __AMDBLOCKS_LPC_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/sata.h b/src/soc/amd/common/block/include/amdblocks/sata.h new file mode 100644 index 0000000000..2a21436525 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/sata.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_SATA_H__ +#define __AMDBLOCKS_SATA_H__ + +#include + +void soc_enable_sata_features(struct device *dev); + +#endif /* __AMDBLOCKS_SATA_H__ */ diff --git a/src/soc/amd/common/block/iommu/Kconfig b/src/soc/amd/common/block/iommu/Kconfig new file mode 100644 index 0000000000..4580400a7c --- /dev/null +++ b/src/soc/amd/common/block/iommu/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_IOMMU + bool + default n + help + Select this option to use AMD common IOMMU support. diff --git a/src/soc/amd/common/block/iommu/Makefile.inc b/src/soc/amd/common/block/iommu/Makefile.inc new file mode 100644 index 0000000000..d08dbfcc33 --- /dev/null +++ b/src/soc/amd/common/block/iommu/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_IOMMU) += iommu.c diff --git a/src/soc/amd/stoneyridge/iommu.c b/src/soc/amd/common/block/iommu/iommu.c similarity index 89% rename from src/soc/amd/stoneyridge/iommu.c rename to src/soc/amd/common/block/iommu/iommu.c index e33402ac43..1c982ca00d 100644 --- a/src/soc/amd/stoneyridge/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -43,13 +43,17 @@ static struct device_operations iommu_ops = { .read_resources = iommu_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, - .scan_bus = 0, .ops_pci = &lops_pci, }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU, + PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, + 0 +}; + static const struct pci_driver iommu_driver __pci_driver = { .ops = &iommu_ops, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU, + .devices = pci_device_ids, }; diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig new file mode 100644 index 0000000000..b0d59a55f4 --- /dev/null +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_LPC + bool + default n + help + Select this option to use the traditional LPC-ISA bridge at D14F3. diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc new file mode 100644 index 0000000000..72b1e42013 --- /dev/null +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -0,0 +1,8 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc.c + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c diff --git a/src/soc/amd/stoneyridge/lpc.c b/src/soc/amd/common/block/lpc/lpc.c similarity index 94% rename from src/soc/amd/stoneyridge/lpc.c rename to src/soc/amd/common/block/lpc/lpc.c index 3ace1fdce6..b896517214 100644 --- a/src/soc/amd/stoneyridge/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -28,15 +28,21 @@ #include #include #include +#include #include -#include #include #include +#include + +/* Most systems should have already enabled the bridge */ +void __weak soc_late_lpc_bridge_enable(void) { } static void lpc_init(struct device *dev) { u8 byte; + soc_late_lpc_bridge_enable(); + /* Initialize isa dma */ isa_dma_init(); @@ -64,8 +70,8 @@ static void lpc_init(struct device *dev) pci_write_config8(dev, LPC_MISC_CONTROL_BITS, byte); /* - * Enable hand-instance of the pulse generator and SPI - * controller prefetch of flash. + * Enable hand-instance of the pulse generator and SPI prefetch from + * host (earlier is recommended for boot speed). */ byte = pci_read_config8(dev, LPC_HOST_CONTROL); byte |= PREFETCH_EN_SPI_FROM_HOST | T_START_ENH; @@ -146,7 +152,7 @@ static void lpc_set_resources(struct device *dev) /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); - spi_enable_bits &= SPI_PRESERVE_BITS; + spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); @@ -247,9 +253,9 @@ static void set_child_resource(struct device *dev, struct device *child, break; default: rsize = 0; - wideio_index = sb_find_wideio_range(base, res->size); + wideio_index = lpc_find_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { - rsize = sb_wideio_size(wideio_index); + rsize = lpc_wideio_size(wideio_index); printk(BIOS_DEBUG, "Covered by wideIO"); printk(BIOS_DEBUG, " %d\n", wideio_index); } @@ -260,7 +266,7 @@ static void set_child_resource(struct device *dev, struct device *child, *reg_x |= set_x; /* check if we can fit resource in variable range */ } else { - wideio_index = sb_set_wideio_range(base, res->size); + wideio_index = lpc_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ *reg_x = pci_read_config32(dev, diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c new file mode 100644 index 0000000000..008d14c34e --- /dev/null +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -0,0 +1,308 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* The LPC-ISA bridge is always at D14F3 */ +#if !defined(__SIMPLE_DEVICE__) +#include +#define _LPCB_DEV pcidev_on_root(0x14, 0x3) +#else +#define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) +#endif + +/* + * Structure to simplify code obtaining the total of used wide IO + * registers and the size assigned to each. + */ +static const struct wide_io_ioport_and_bits { + uint32_t enable; + uint16_t port; + uint8_t alt; +} wio_io_en[] = { + { + .enable = LPC_WIDEIO0_ENABLE, + .port = LPC_WIDEIO_GENERIC_PORT, + .alt = LPC_ALT_WIDEIO0_ENABLE + }, + { + .enable = LPC_WIDEIO1_ENABLE, + .port = LPC_WIDEIO1_GENERIC_PORT, + .alt = LPC_ALT_WIDEIO1_ENABLE + }, + { + .enable = LPC_WIDEIO2_ENABLE, + .port = LPC_WIDEIO2_GENERIC_PORT, + .alt = LPC_ALT_WIDEIO2_ENABLE + } +}; + +/** + * @brief Find the size of a particular wide IO + * + * @param index = index of desired wide IO + * + * @return size of desired wide IO + */ +uint16_t lpc_wideio_size(int index) +{ + uint32_t enable_register; + uint16_t size = 0; + uint8_t alternate_register; + + if (index >= ARRAY_SIZE(wio_io_en)) + return size; + enable_register = pci_read_config32(_LPCB_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(_LPCB_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + if (enable_register & wio_io_en[index].enable) + size = (alternate_register & wio_io_en[index].alt) ? + 16 : 512; + return size; +} + +/** + * @brief Identify if any LPC wide IO is covering the IO range + * + * @param start = start of IO range + * @param size = size of IO range + * + * @return Index of wide IO covering the range or error + */ +int lpc_find_wideio_range(uint16_t start, uint16_t size) +{ + int i, index = WIDEIO_RANGE_ERROR; + uint16_t end, current_size, start_wideio, end_wideio; + + end = start + size; + for (i = 0; i < ARRAY_SIZE(wio_io_en); i++) { + current_size = lpc_wideio_size(i); + if (current_size == 0) + continue; + start_wideio = pci_read_config16(_LPCB_DEV, + wio_io_en[i].port); + end_wideio = start_wideio + current_size; + if ((start >= start_wideio) && (end <= end_wideio)) { + index = i; + break; + } + } + return index; +} + +/** + * @brief Program a LPC wide IO to support an IO range + * + * @param start = start of range to be routed through wide IO + * @param size = size of range to be routed through wide IO + * + * @return Index of wide IO register used or error + */ +int lpc_set_wideio_range(uint16_t start, uint16_t size) +{ + int i, index = WIDEIO_RANGE_ERROR; + uint32_t enable_register; + uint8_t alternate_register; + + enable_register = pci_read_config32(_LPCB_DEV, + LPC_IO_OR_MEM_DECODE_ENABLE); + alternate_register = pci_read_config8(_LPCB_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE); + for (i = 0; i < ARRAY_SIZE(wio_io_en); i++) { + if (enable_register & wio_io_en[i].enable) + continue; + index = i; + pci_write_config16(_LPCB_DEV, wio_io_en[i].port, start); + enable_register |= wio_io_en[i].enable; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, + enable_register); + if (size <= 16) + alternate_register |= wio_io_en[i].alt; + else + alternate_register &= ~wio_io_en[i].alt; + pci_write_config8(_LPCB_DEV, + LPC_ALT_WIDEIO_RANGE_ENABLE, + alternate_register); + break; + } + return index; +} + +void lpc_enable_port80(void) +{ + u8 byte; + + byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte |= DECODE_IO_PORT_ENABLE4_H; + pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); +} + +void lpc_enable_pci_port80(void) +{ + u8 byte; + + byte = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); + byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ + pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); +} + +void lpc_enable_decode(uint32_t decodes) +{ + pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); +} + +uintptr_t lpc_spibase(void) +{ + u32 base, enables; + + /* Make sure the base address is predictable */ + base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + enables = base & SPI_PRESERVE_BITS; + base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED); + + if (!base) { + base = SPI_BASE_ADDRESS; + pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, + base | enables | SPI_ROM_ENABLE); + /* PCI_COMMAND_MEMORY is read-only and enabled. */ + } + return base; +} + +/* + * Enable FCH to decode TPM associated Memory and IO regions + * + * Enable decoding of TPM cycles defined in TPM 1.2 spec + * Enable decoding of legacy TPM addresses: IO addresses 0x7f- + * 0x7e and 0xef-0xee. + * This function should be called if TPM is connected in any way to the FCH and + * conforms to the regions decoded. + * Absent any other routing configuration the TPM cycles will be claimed by the + * LPC bus + */ +void lpc_tpm_decode(void) +{ + u32 value; + + value = pci_read_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE); + value |= TPM_12_EN | TPM_LEGACY_EN; + pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); +} + +/* + * Enable FCH to decode TPM associated Memory and IO regions to SPI + * + * This should be used if TPM is connected to SPI bus. + * Assumes SPI address space is already configured via a call to lpc_spibase(). + */ +void lpc_tpm_decode_spi(void) +{ + /* Enable TPM decoding to FCH */ + lpc_tpm_decode(); + + /* Route TPM accesses to SPI */ + u32 spibase = pci_read_config32(_LPCB_DEV, + SPIROM_BASE_ADDRESS_REGISTER); + pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase + | ROUTE_TPM_2_SPI); +} + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The southbridge power-on default is to map 512K ROM space. + * + */ +void lpc_enable_rom(void) +{ + u8 reg8; + + /* + * Decode variable LPC ROM address ranges 1 and 2. + * Bits 3-4 are not defined in any publicly available datasheet + */ + reg8 = pci_read_config8(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); + + /* + * LPC ROM address range 1: + * Enable LPC ROM range mirroring start at 0x000e(0000). + */ + pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); + + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); + + /* + * LPC ROM address range 2: + * + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 + - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(_LPCB_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); +} + +void lpc_enable_spi_prefetch(void) +{ + uint32_t dword; + + dword = pci_read_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); + dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; + pci_write_config32(_LPCB_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); +} + +uintptr_t lpc_get_spibase(void) +{ + u32 base; + + base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); + return (uintptr_t)base; +} + +void lpc_set_spibase(u32 base, u32 enable) +{ + u32 reg32; + + /* only two types of CS# enables are allowed */ + enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE; + + reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + + reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */ + reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE); + reg32 |= enable; + reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); + + pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); +} diff --git a/src/soc/amd/common/block/s3/Kconfig b/src/soc/amd/common/block/s3/Kconfig index 0880163d54..ebc1695d9b 100644 --- a/src/soc/amd/common/block/s3/Kconfig +++ b/src/soc/amd/common/block/s3/Kconfig @@ -1,6 +1,7 @@ config SOC_AMD_COMMON_BLOCK_S3 bool default n + depends on SOC_AMD_COMMON_BLOCK_ACPI select CACHE_MRC_SETTINGS select MRC_WRITE_NV_LATE help diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c index 0ba2f13b46..74aa79c398 100644 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ b/src/soc/amd/common/block/s3/s3_resume.c @@ -21,6 +21,7 @@ #include #include #include +#include /* Training data versioning is not supported or tracked. */ #define DEFAULT_MRC_VERSION 0 diff --git a/src/soc/amd/common/block/sata/Kconfig b/src/soc/amd/common/block/sata/Kconfig new file mode 100644 index 0000000000..0c3d5bc0a1 --- /dev/null +++ b/src/soc/amd/common/block/sata/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SATA + bool + default n + help + Select this option to use AMD common SATA driver support. diff --git a/src/soc/amd/common/block/sata/Makefile.inc b/src/soc/amd/common/block/sata/Makefile.inc new file mode 100644 index 0000000000..59b99eb9b4 --- /dev/null +++ b/src/soc/amd/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_HDA) += sata.c diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c new file mode 100644 index 0000000000..cbbc7cfd92 --- /dev/null +++ b/src/soc/amd/common/block/sata/sata.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void __weak soc_enable_sata_features(struct device *dev) { } + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = soc_enable_sata_features, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_AMD_CZ_SATA, + PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, + 0 +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .devices = pci_device_ids, +}; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index d4e1feb251..ba82565bf4 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -46,8 +46,14 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_PI select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK + select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_ACPI + select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_PCI + select SOC_AMD_COMMON_BLOCK_HDA + select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 68dba097c1..babd878524 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -46,7 +46,6 @@ bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c bootblock-y += monotonic_timer.c bootblock-y += pmutil.c bootblock-y += reset.c -bootblock-y += sb_util.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-y += nb_util.c @@ -61,7 +60,6 @@ romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c romstage-y += reset.c -romstage-y += sb_util.c romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += ramtop.c @@ -75,7 +73,6 @@ romstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-y += sb_util.c verstage-y += pmutil.c verstage-y += reset.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -86,7 +83,6 @@ verstage-$(CONFIG_SPI_FLASH) += spi.c postcar-y += monotonic_timer.c postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c postcar-y += ramtop.c -postcar-y += sb_util.c postcar-y += nb_util.c postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c postcar-y += tsc_freq.c @@ -99,12 +95,8 @@ ramstage-y += mca.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += gpio.c -ramstage-y += hda.c -ramstage-y += iommu.c ramstage-y += monotonic_timer.c ramstage-y += southbridge.c -ramstage-y += sb_util.c -ramstage-y += lpc.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += reset.c @@ -124,7 +116,6 @@ ramstage-y += nb_util.c smm-y += monotonic_timer.c smm-y += smihandler.c smm-y += smi_util.c -smm-y += sb_util.c smm-y += tsc_freq.c smm-$(CONFIG_DEBUG_SMI) += uart.c smm-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 4f11ea227a..d1ea24ffd5 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* Not supported */ fadt->pstate_cnt = 0; /* Not supported */ fadt->cst_cnt = 0; /* Not supported */ - acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 0); /* clear SCI_EN */ + acpi_disable_sci(); } else { fadt->smi_cmd = 0; /* disable system management mode */ fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ @@ -107,7 +108,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ - acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 1); /* set SCI_EN */ + acpi_enable_sci(); } fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; @@ -317,9 +318,9 @@ static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) { - if (gpio_num >= GPIO_TOTAL_PINS) { + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, GPIO_TOTAL_PINS); + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); @@ -347,9 +348,9 @@ static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) { - if (gpio_num >= GPIO_TOTAL_PINS) { + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, GPIO_TOTAL_PINS); + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); return -1; } uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); diff --git a/src/soc/amd/stoneyridge/acpi/sb_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_fch.asl index 4c1196dad6..e7975f8d94 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_fch.asl @@ -22,7 +22,7 @@ Device (AAHB) Name (_UID, 0x0) Name (_CRS, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0xFEDC0000, 0x2000) + Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000) }) Method (_STA, 0x0, NotSerialized) diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 1334df11c4..3623814080 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -51,7 +51,7 @@ Device(SBUS) { /* 0:14.2 - I2S Audio */ /* 0:14.3 - LPC */ -#include "lpc.asl" +#include /* 0:14.7 - SD Controller */ Device(SDCN) { diff --git a/src/soc/amd/stoneyridge/acpi/soc.asl b/src/soc/amd/stoneyridge/acpi/soc.asl index 6fd838a56d..52c7ee6c00 100644 --- a/src/soc/amd/stoneyridge/acpi/soc.asl +++ b/src/soc/amd/stoneyridge/acpi/soc.asl @@ -28,4 +28,4 @@ Device(PCI0) { #include "sb_fch.asl" /* Add GPIO library */ -#include +#include diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c index 7c9680582c..f63a0d93a4 100644 --- a/src/soc/amd/stoneyridge/gpio.c +++ b/src/soc/amd/stoneyridge/gpio.c @@ -15,14 +15,11 @@ * GNU General Public License for more details. */ -#include -#include -#include -#include +#include +#include #include #include -#include -#include "chip.h" +#include static const struct soc_amd_event gpio_event_table[] = { { GPIO_1, GEVENT_19 }, @@ -51,290 +48,20 @@ static const struct soc_amd_event gpio_event_table[] = { { GPIO_69, GEVENT_17 }, }; -static int get_gpio_gevent(uint8_t gpio) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(gpio_event_table); i++) { - if (gpio_event_table[i].gpio == gpio) - return (int)gpio_event_table[i].event; - } - return -1; -} - -static void mem_read_write32(uint32_t *address, uint32_t value, uint32_t mask) -{ - uint32_t reg32; - - value &= mask; - reg32 = read32(address); - reg32 &= ~mask; - reg32 |= value; - write32(address, reg32); -} - -__weak void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) -{ - printk(BIOS_WARNING, "Warning: SMI disabled!\n"); -} - -static void program_smi(uint32_t flag, int gevent_num) -{ - uint32_t trigger; - - trigger = flag & FLAGS_TRIGGER_MASK; - /* - * Only level trigger is allowed for SMI. Trigger values are 0 - * through 3, with 0-1 being level trigger and 2-3 being edge - * trigger. GPIO_TRIGGER_EDGE_LOW is 2, so trigger has to be - * less than GPIO_TRIGGER_EDGE_LOW. - */ - assert(trigger < GPIO_TRIGGER_EDGE_LOW); - - if (trigger == GPIO_TRIGGER_LEVEL_HIGH) - configure_gevent_smi(gevent_num, SMI_MODE_SMI, - SMI_SCI_LVL_HIGH); - if (trigger == GPIO_TRIGGER_LEVEL_LOW) - configure_gevent_smi(gevent_num, SMI_MODE_SMI, - SMI_SCI_LVL_LOW); -} - -static void route_sci(uint8_t event) +void soc_route_sci(uint8_t event) { smi_write8(SMI_SCI_MAP(event), event); } -static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level) +void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items) { - uint32_t trigger; - - trigger = flag & FLAGS_TRIGGER_MASK; - switch (trigger) { - case GPIO_TRIGGER_LEVEL_LOW: - *edge = SCI_TRIGGER_LEVEL; - *level = 0; - break; - case GPIO_TRIGGER_LEVEL_HIGH: - *edge = SCI_TRIGGER_LEVEL; - *level = 1; - break; - case GPIO_TRIGGER_EDGE_LOW: - *edge = SCI_TRIGGER_EDGE; - *level = 0; - break; - case GPIO_TRIGGER_EDGE_HIGH: - *edge = SCI_TRIGGER_EDGE; - *level = 1; - break; - default: - break; - } + *table = gpio_event_table; + *items = ARRAY_SIZE(gpio_event_table); } -uintptr_t gpio_get_address(gpio_t gpio_num) +void soc_gpio_hook(uint8_t gpio, uint8_t mux) { - uintptr_t gpio_address; - - if (gpio_num < 64) - gpio_address = GPIO_BANK0_CONTROL(gpio_num); - else if (gpio_num < 128) - gpio_address = GPIO_BANK1_CONTROL(gpio_num); - else - gpio_address = GPIO_BANK2_CONTROL(gpio_num); - - return gpio_address; -} - -int gpio_get(gpio_t gpio_num) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - - return !!(reg & GPIO_PIN_STS); -} - -void gpio_set(gpio_t gpio_num, int value) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - reg &= ~GPIO_OUTPUT_MASK; - reg |= !!value << GPIO_OUTPUT_SHIFT; - write32((void *)gpio_address, reg); -} - -void gpio_input_pulldown(gpio_t gpio_num) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - reg &= ~GPIO_PULLUP_ENABLE; - reg |= GPIO_PULLDOWN_ENABLE; - write32((void *)gpio_address, reg); -} - -void gpio_input_pullup(gpio_t gpio_num) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - reg &= ~GPIO_PULLDOWN_ENABLE; - reg |= GPIO_PULLUP_ENABLE; - write32((void *)gpio_address, reg); -} - -void gpio_input(gpio_t gpio_num) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - reg &= ~GPIO_OUTPUT_ENABLE; - write32((void *)gpio_address, reg); -} - -void gpio_output(gpio_t gpio_num, int value) -{ - uint32_t reg; - uintptr_t gpio_address = gpio_get_address(gpio_num); - - reg = read32((void *)gpio_address); - reg |= GPIO_OUTPUT_ENABLE; - write32((void *)gpio_address, reg); - gpio_set(gpio_num, value); -} - -const char *gpio_acpi_path(gpio_t gpio) -{ - return "\\_SB.GPIO"; -} - -uint16_t gpio_acpi_pin(gpio_t gpio) -{ - return gpio; -} - -void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size) -{ - uint32_t *gpio_ptr, *inter_master; - uint32_t control, control_flags, edge_level, direction; - uint32_t mask, bit_edge, bit_level; - uint8_t mux, index, gpio; - int gevent_num; - - inter_master = (uint32_t *)(uintptr_t)(ACPIMMIO_GPIO0_BASE - + GPIO_MASTER_SWITCH); - direction = 0; - edge_level = 0; - mask = 0; - - /* - * Disable blocking wake/interrupt status generation while updating - * debounce registers. Otherwise when a debounce register is updated - * the whole GPIO controller will zero out all interrupt enable status - * bits while the delay happens. This could cause us to drop the bits - * due to the read-modify-write that happens on each register. - * - * Additionally disable interrupt generation so we don't get any - * spurious interrupts while updating the registers. - */ - mem_read_write32(inter_master, 0, GPIO_MASK_STS_EN | GPIO_INTERRUPT_EN); - - for (index = 0; index < size; index++) { - gpio = gpio_list_ptr[index].gpio; - mux = gpio_list_ptr[index].function; - control = gpio_list_ptr[index].control; - control_flags = gpio_list_ptr[index].flags; - - iomux_write8(gpio, mux & AMD_GPIO_MUX_MASK); - iomux_read8(gpio); /* Flush posted write */ - /* special case if pin 2 is assigned to wake */ - if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) - route_sci(GPIO_2_EVENT); - gpio_ptr = (uint32_t *)gpio_get_address(gpio); - - if (control_flags & GPIO_SPECIAL_FLAG) { - gevent_num = get_gpio_gevent(gpio); - if (gevent_num < 0) { - printk(BIOS_WARNING, "Warning: GPIO pin %d has" - " no associated gevent!\n", gpio); - continue; - } - switch (control_flags & GPIO_SPECIAL_MASK) { - case GPIO_DEBOUNCE_FLAG: - mem_read_write32(gpio_ptr, control, - GPIO_DEBOUNCE_MASK); - break; - case GPIO_WAKE_FLAG: - mem_read_write32(gpio_ptr, control, - INT_WAKE_MASK); - break; - case GPIO_INT_FLAG: - mem_read_write32(gpio_ptr, control, - AMD_GPIO_CONTROL_MASK); - break; - case GPIO_SMI_FLAG: - mem_read_write32(gpio_ptr, control, - INT_SCI_SMI_MASK); - program_smi(control_flags, gevent_num); - break; - case GPIO_SCI_FLAG: - mem_read_write32(gpio_ptr, control, - INT_SCI_SMI_MASK); - get_sci_config_bits(control_flags, &bit_edge, - &bit_level); - edge_level |= bit_edge << gevent_num; - direction |= bit_level << gevent_num; - mask |= (1 << gevent_num); - route_sci(gevent_num); - break; - default: - printk(BIOS_WARNING, "Error, flags 0x%08x\n", - control_flags); - break; - } - } else { - mem_read_write32(gpio_ptr, control, - AMD_GPIO_CONTROL_MASK); - } - } - - /* - * Re-enable interrupt status generation. - * - * We leave MASK_STATUS disabled because the kernel may reconfigure the - * debounce registers while the drivers load. This will cause interrupts - * to be missed during boot. - */ - mem_read_write32(inter_master, GPIO_INTERRUPT_EN, GPIO_INTERRUPT_EN); - - /* Set all SCI trigger direction (high/low) */ - mem_read_write32((uint32_t *) - (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_TRIG), - direction, mask); - - /* Set all SCI trigger level (edge/level) */ - mem_read_write32((uint32_t *) - (uintptr_t)(ACPIMMIO_SMI_BASE + SMI_SCI_LEVEL), - edge_level, mask); -} - -int gpio_interrupt_status(gpio_t gpio) -{ - uintptr_t gpio_address = gpio_get_address(gpio); - uint32_t reg = read32((void *)gpio_address); - - if (reg & GPIO_INT_STATUS) { - /* Clear interrupt status, preserve wake status */ - reg &= ~GPIO_WAKE_STATUS; - write32((void *)gpio_address, reg); - return 1; - } - - return 0; + /* Always program Gevent when WAKE_L_AGPIO2 is configured as WAKE_L */ + if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK)) + soc_route_sci(GPIO_2_EVENT); } diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index c3e5539e19..7f65a4f3f3 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -203,7 +203,7 @@ void sb_reset_i2c_slaves(void) /* Save and reprogram I2C SCL pins */ for (i = 0; i < saved_pins_count; i++) save_i2c_pin_registers(i2c_2_gpi[i].gpio, &save_table[i]); - sb_program_gpios(i2c_2_gpi, saved_pins_count); + program_gpios(i2c_2_gpi, saved_pins_count); /* * Toggle SCL back and forth 9 times under 100KHz. A single read is diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h index 26d0336d0a..d8774f051a 100644 --- a/src/soc/amd/stoneyridge/include/soc/gpio.h +++ b/src/soc/amd/stoneyridge/include/soc/gpio.h @@ -21,59 +21,13 @@ #ifndef __ACPI__ #include -#include -#include +#include -struct soc_amd_gpio { - uint8_t gpio; - uint8_t function; - uint32_t control; - uint32_t flags; -}; +/* The following sections describe only the GPIOs defined for this SOC */ -struct soc_amd_event { - uint8_t gpio; - uint8_t event; -}; +#define SOC_GPIO_TOTAL_PINS 149 -#define GPIO_MASTER_SWITCH 0xFC -#define GPIO_MASK_STS_EN BIT(28) -#define GPIO_INTERRUPT_EN BIT(30) - -#define GPIO_TOTAL_PINS 149 -#define GPIO_PIN_IN (1 << 0) /* for byte access */ -#define GPIO_PIN_OUT (1 << 6) /* for byte access */ - -#define GPIO_EDGE_TRIG (0 << 8) -#define GPIO_LEVEL_TRIG (1 << 8) -#define GPIO_TRIGGER_MASK (1 << 8) - -#define GPIO_ACTIVE_HIGH (0 << 9) -#define GPIO_ACTIVE_LOW (1 << 9) -#define GPIO_ACTIVE_BOTH (2 << 9) -#define GPIO_ACTIVE_MASK (3 << 9) - -#define GPIO_INT_STATUS_EN (1 << 11) -#define GPIO_INT_DELIVERY_EN (1 << 12) -#define GPIO_INTERRUPT_MASK (3 << 11) -#define GPIO_S0I3_WAKE_EN (1 << 13) -#define GPIO_S3_WAKE_EN (1 << 14) -#define GPIO_S4_S5_WAKE_EN (1 << 15) - -#define GPIO_PIN_STS (1 << 16) -#define GPIO_PULLUP_ENABLE (1 << 20) -#define GPIO_PULLDOWN_ENABLE (1 << 21) -#define GPIO_OUTPUT_SHIFT 22 -#define GPIO_OUTPUT_MASK (1 << GPIO_OUTPUT_SHIFT) -#define GPIO_OUTPUT_VALUE (1 << GPIO_OUTPUT_SHIFT) -#define GPIO_OUTPUT_ENABLE (1 << 23) - -#define GPIO_INT_STATUS (1 << 28) -#define GPIO_WAKE_STATUS (1 << 29) - -/* GPIO_0 - GPIO_62 */ -#define GPIO_BANK0_CONTROL(gpio) \ - (AMD_SB_ACPI_MMIO_ADDR + 0x1500 + ((gpio) * 4)) +/* Bank 0: GPIO_0 - GPIO_62 */ #define GPIO_0 0 #define GPIO_1 1 #define GPIO_2 2 @@ -105,9 +59,7 @@ struct soc_amd_event { #define GPIO_40 40 #define GPIO_42 42 -/* GPIO_64 - GPIO_127 */ -#define GPIO_BANK1_CONTROL(gpio) \ - (AMD_SB_ACPI_MMIO_ADDR + 0x1600 + (((gpio) - 64) * 4)) +/* Bank 1: GPIO_64 - GPIO_127 */ #define GPIO_64 64 #define GPIO_65 65 #define GPIO_66 66 @@ -150,10 +102,7 @@ struct soc_amd_event { #define GPIO_122 122 #define GPIO_126 126 -/* GPIO_128 - GPIO_183 */ -#define GPIO_BANK2_CONTROL(gpio) \ - (AMD_SB_ACPI_MMIO_ADDR + 0x1700 + (((gpio) - 128) * 4)) -/* GPIO_128 Reserved */ +/* Bank 2: GPIO_128 - GPIO_183 */ #define GPIO_129 129 #define GPIO_130 130 #define GPIO_131 131 @@ -353,230 +302,7 @@ struct soc_amd_event { #define GPIO_148_IOMUX_I2C1_SDA 0 #define GPIO_148_IOMUX_GPIOxx 1 -enum { - GEVENT_0, - GEVENT_1, - GEVENT_2, - GEVENT_3, - GEVENT_4, - GEVENT_5, - GEVENT_6, - GEVENT_7, - GEVENT_8, - GEVENT_9, - GEVENT_10, - GEVENT_11, - GEVENT_12, - GEVENT_13, - GEVENT_14, - GEVENT_15, - GEVENT_16, - GEVENT_17, - GEVENT_18, - GEVENT_19, - GEVENT_20, - GEVENT_21, - GEVENT_22, - GEVENT_23, -}; #define GPIO_2_EVENT GEVENT_8 -#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE) -#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE - -#define GPIO_PULL_PULL_UP GPIO_PULLUP_ENABLE -#define GPIO_PULL_PULL_DOWN GPIO_PULLDOWN_ENABLE -#define GPIO_PULL_PULL_NONE 0 - -#define AMD_GPIO_CONTROL_MASK 0x00f4ff00 -#define AMD_GPIO_MUX_MASK 0x03 - -/* Definitions for PAD_INT. */ -#define GPIO_INT_EDGE_HIGH (GPIO_ACTIVE_HIGH | GPIO_EDGE_TRIG) -#define GPIO_INT_EDGE_LOW (GPIO_ACTIVE_LOW | GPIO_EDGE_TRIG) -#define GPIO_INT_BOTH_EDGES (GPIO_ACTIVE_BOTH | GPIO_EDGE_TRIG) -#define GPIO_INT_LEVEL_HIGH (GPIO_ACTIVE_HIGH | GPIO_LEVEL_TRIG) -#define GPIO_INT_LEVEL_LOW (GPIO_ACTIVE_LOW | GPIO_LEVEL_TRIG) - -enum { - GPIO_TRIGGER_LEVEL_LOW, - GPIO_TRIGGER_LEVEL_HIGH, - GPIO_TRIGGER_EDGE_LOW, - GPIO_TRIGGER_EDGE_HIGH, -}; - -#define GPIO_TRIGGER_INVALID -1 -#define SCI_TRIGGER_EDGE 0 -#define SCI_TRIGGER_LEVEL 1 - -#define GPIO_SPECIAL_FLAG (1 << 31) -#define GPIO_DEBOUNCE_FLAG (1 << 30) -#define GPIO_WAKE_FLAG (1 << 29) -#define GPIO_INT_FLAG (1 << 28) -#define GPIO_SMI_FLAG (1 << 27) -#define GPIO_SCI_FLAG (1 << 26) -#define GPIO_FLAG_DEBOUNCE (GPIO_SPECIAL_FLAG | GPIO_DEBOUNCE_FLAG) -#define GPIO_FLAG_WAKE (GPIO_SPECIAL_FLAG | GPIO_WAKE_FLAG) -#define GPIO_FLAG_INT (GPIO_SPECIAL_FLAG | GPIO_INT_FLAG) -#define GPIO_FLAG_SCI (GPIO_SPECIAL_FLAG | GPIO_SCI_FLAG) -#define GPIO_FLAG_SMI (GPIO_SPECIAL_FLAG | GPIO_SMI_FLAG) - -#define FLAGS_TRIGGER_MASK 0x00000003 -#define GPIO_SPECIAL_MASK 0x7c000000 -#define GPIO_DEBOUNCE_MASK 0x000000ff -#define INT_TRIGGER_MASK 0x00000700 -#define INT_WAKE_MASK 0x0000e700 -#define INT_SCI_SMI_MASK 0x00f40000 - -#define IN_GLITCH_SHIFT 5 -#define GLITCH_LOW 1 -#define GLITCH_HIGH 2 -#define GLITCH_NONE 3 -#define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT) -#define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT) -#define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT) - -#define GPIO_TIMEBASE_61uS 0 -#define GPIO_TIMEBASE_183uS (1 << 4) -#define GPIO_TIMEBASE_15560uS (1 << 7) -#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \ - GPIO_TIMEBASE_15560uS) -#define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS) -#define GPIO_IN_60uS (1 | GPIO_TIMEBASE_61uS) -#define GPIO_IN_120uS (2 | GPIO_TIMEBASE_61uS) -#define GPIO_IN_200uS (3 | GPIO_TIMEBASE_61uS) -#define GPIO_IN_500uS (8 | GPIO_TIMEBASE_61uS) -#define GPIO_IN_1mS (5 | GPIO_TIMEBASE_183uS) -#define GPIO_IN_2mS (11 | GPIO_TIMEBASE_183uS) -#define GPIO_IN_15mS (1 | GPIO_TIMEBASE_15560uS) -#define GPIO_IN_50mS (3 | GPIO_TIMEBASE_15560uS) -#define GPIO_IN_100mS (6 | GPIO_TIMEBASE_15560uS) -#define GPIO_IN_200mS (13 | GPIO_TIMEBASE_15560uS) -#define GPIO_IN_500mS (8 | GPIO_TIMEBASE_62440uS) - -#define GPIO_EVENT_INT_STATUS GPIO_INT_STATUS_EN -#define GPIO_EVENT_INT_DELIVER GPIO_INT_DELIVERY_EN -#define GPIO_EVENT_INT_STATUS_DELIVER (GPIO_INT_STATUS_EN | \ - GPIO_INT_DELIVERY_EN) -#define GPIO_WAKE_S0i3 (1 << 13) -#define GPIO_WAKE_S3 (1 << 14) -#define GPIO_WAKE_S4_S5 (1 << 15) -#define GPIO_WAKE_S0i3_S4_S5 (GPIO_WAKE_S0i3 | GPIO_WAKE_S4_S5) -#define GPIO_WAKE_S3_S4_S5 (GPIO_WAKE_S3 | GPIO_WAKE_S4_S5) - -/* - * Several macros are available to declare programming of GPIO pins, and if - * needed, more than 1 macro can be used for any pin. However, some macros - * will have no effect if combined. For example debounce only affects input - * or one of the interrupts. Some macros should not be combined, such as SMI - * and regular interrupt. The defined macros and their parameters are: - * PAD_NF Define native alternate function for the pin. - * pin the pin to be programmed - * function the native function - * pull pull up, pull down or no pull - * PAD_GPI The pin is a GPIO input - * pin the pin to be programmed - * pull pull up, pull down or no pull - * PAD_GPO The pin is a GPIO output - * pin the pin to be programmed - * direction high or low - * PAD_INT The pin is regular interrupt that works while booting - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * action STATUS, DELIVER, STATUS_DELIVER - * PAD_SCI The pin is a SCI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH - * PAD_SMI The pin is a SMI source - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH - * PAD_WAKE The pin can wake, use after PAD_INT or PAD_SCI - * pin the pin to be programmed - * pull pull up, pull down or no pull - * trigger LEVEL_LOW, LEVEL_HIGH, EDGE_LOW, EDGE_HIGH, BOTH_EDGES - * type S0i3, S3, S4_S5 or S4_S5 combinations (S0i3_S3 invalid) - * PAD_DEBOUNCE The input or interrupt will be debounced, invalid after - * PAD_NF - * pin the pin to be programmed - * debounce_type preserve low glitch, preserve high glitch, no glitch - * debounce_time the debounce time - */ - -/* Native function pad configuration */ -#define PAD_NF(pin, func, pull) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## func, \ - .control = GPIO_PULL ## _ ## pull, \ - .flags = 0 } -/* General purpose input pad configuration */ -#define PAD_GPI(pin, pull) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = GPIO_PULL ## _ ## pull, \ - .flags = 0 } -/* General purpose output pad configuration */ -#define PAD_GPO(pin, direction) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = GPIO_OUTPUT ## _OUT_ ## direction, \ - .flags = 0 } -/* Auxiliary macro for legacy interrupt and wake */ -#define PAD_AUX1(pull, trigger) (GPIO_PULL ## _ ## pull | \ - GPIO_INT ## _ ## trigger) -/* Legacy interrupt pad configuration */ -#define PAD_INT(pin, pull, trigger, action) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = (PAD_AUX1(pull, trigger) | \ - GPIO_EVENT_INT ## _ ## action), \ - .flags = GPIO_FLAG_INT } -/* Auxiliary macro for SCI and SMI */ -#define PAD_AUX2(trigger, flag) (GPIO_TRIGGER ## _ ## trigger | flag) -/* SCI pad configuration */ -#define PAD_SCI(pin, pull, trigger) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = GPIO_PULL ## _ ## pull, \ - .flags = PAD_AUX2(trigger, GPIO_FLAG_SCI) } -/* SMI pad configuration */ -#define PAD_SMI(pin, pull, trigger) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = GPIO_PULL ## _ ## pull, \ - .flags = PAD_AUX2(trigger, GPIO_FLAG_SMI) } -/* WAKE pad configuration */ -#define PAD_WAKE(pin, pull, trigger, type) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = (PAD_AUX1(pull, trigger) | \ - GPIO_WAKE ## _ ## type), \ - .flags = GPIO_FLAG_WAKE } -/* pin debounce configuration */ -#define PAD_DEBOUNCE(pin, type, time) \ - { .gpio = (pin), \ - .function = pin ## _IOMUX_ ## GPIOxx, \ - .control = (GPIO_IN ## _ ## type | GPIO_IN ## _ ## time), \ - .flags = GPIO_FLAG_DEBOUNCE } - -typedef uint32_t gpio_t; -/* Get the address of the control register of a particular pin */ -uintptr_t gpio_get_address(gpio_t gpio_num); - -/** - * @brief program a particular set of GPIO - * - * @param gpio_list_ptr = pointer to array of gpio configurations - * @param size = number of entries in array - * - * @return none - */ -void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size); - -/* Return the interrupt status and clear if set. */ -int gpio_interrupt_status(gpio_t gpio); - #endif /* __ACPI__ */ #endif /* __STONEYRIDGE_GPIO_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 1caef3362f..612b6e871b 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,8 +22,27 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +/* + * AcpiMmio blocks are at fixed offsets from FED8_0000h and enabled in PMx04[1]. + * All ranges not specified as supported below may, or may not, be listed in + * any documentation but should be considered reserved through FED8_1FFFh. + */ #include +#define SUPPORTS_ACPIMMIO_SMI_BASE 1 /* 0xfed80100 */ +#define SUPPORTS_ACPIMMIO_PMIO_BASE 1 /* 0xfed80300 */ +#define SUPPORTS_ACPIMMIO_BIOSRAM_BASE 1 /* 0xfed80500 */ +#define SUPPORTS_ACPIMMIO_ACPI_BASE 1 /* 0xfed80800 */ +#define SUPPORTS_ACPIMMIO_ASF_BASE 1 /* 0xfed80900 */ +#define SUPPORTS_ACPIMMIO_SMBUS_BASE 1 /* 0xfed80a00 */ +#define SUPPORTS_ACPIMMIO_IOMUX_BASE 1 /* 0xfed80d00 */ +#define SUPPORTS_ACPIMMIO_MISC_BASE 1 /* 0xfed80e00 */ +#define SUPPORTS_ACPIMMIO_GPIO0_BASE 1 /* 0xfed81500 */ +#define SUPPORTS_ACPIMMIO_GPIO1_BASE 1 /* 0xfed81800 */ +#define SUPPORTS_ACPIMMIO_GPIO2_BASE 1 /* 0xfed81700 */ +#define SUPPORTS_ACPIMMIO_XHCIPM_BASE 1 /* 0xfed81c00 */ +#define SUPPORTS_ACPIMMIO_AOAC_BASE 1 /* 0xfed81e00 */ + +#define ALINK_AHB_ADDRESS 0xfedc0000 /* I2C fixed address */ #define I2C_BASE_ADDRESS 0xfedc2000 diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index 71f7fafa5e..391084d807 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -21,38 +21,15 @@ #define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) -#define AX_INDXC 0 -#define AX_INDXP 2 -#define AXCFG 4 -#define ABCFG 6 -#define RC_INDXC 1 -#define RC_INDXP 3 - /* * Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -#define abcfg_reg(reg, mask, val) \ - alink_ab_indx((ABCFG), (reg), (mask), (val)) -#define axcfg_reg(reg, mask, val) \ - alink_ab_indx((AXCFG), (reg), (mask), (val)) -#define axindxc_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXC), (reg), (mask), (val)) -#define axindxp_reg(reg, mask, val) \ - alink_ax_indx((AX_INDXP), (reg), (mask), (val)) -#define rcindxc_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) -#define rcindxp_reg(reg, port, mask, val) \ - alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) - int do_smbus_read_byte(u32 mmio, u8 device, u8 address); int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); int do_smbus_recv_byte(u32 mmio, u8 device); int do_smbus_send_byte(u32 mmio, u8 device, u8 val); -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val); #endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index d22b8dbdd5..000eed8554 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -233,6 +233,7 @@ void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); void disable_gevent_smi(uint8_t gevent); void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes); +void soc_route_sci(uint8_t event); #ifndef __SMM__ void enable_smi_generation(void); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 6734efb04d..ad4040759c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -103,15 +103,6 @@ #define PM_USB_ENABLE 0xef #define PM_USB_ALL_CONTROLLERS 0x7f -/* ACPI MMIO registers 0xfed80800 */ -#define MMIO_ACPI_PM1_STS 0x00 -#define MMIO_ACPI_PM1_EN 0x02 -#define MMIO_ACPI_PM1_CNT_BLK 0x04 -#define MMIO_ACPI_CPU_CONTROL 0x0c -#define MMIO_ACPI_GPE0_STS 0x14 -#define MMIO_ACPI_GPE0_EN 0x18 -#define MMIO_ACPI_PM_TMR_BLK 0x08 - /* SMBUS MMIO offsets 0xfed80a00 */ #define SMBHSTSTAT 0x0 #define SMBHST_STAT_FAILED 0x10 @@ -256,126 +247,16 @@ #define GPE0_LIMIT 28 #define TOTAL_BITS(a) (8 * sizeof(a)) -/* - * PCI Config Space Definitions - */ - -/* ISA Bridge D14F3 */ -#define LPC_PCI_CONTROL 0x40 -#define LEGACY_DMA_EN BIT(2) - -#define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) -#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) -#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) -#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) -#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) -#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) -#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) -#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) -#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) -#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) -#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) -#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) -#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) -#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) -#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) -#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) -#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) -#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) -#define DECODE_ENABLE_MIDI_PORT0 BIT(18) -#define DECODE_ENABLE_MIDI_PORT1 BIT(19) -#define DECODE_ENABLE_MIDI_PORT2 BIT(20) -#define DECODE_ENABLE_MIDI_PORT3 BIT(21) -#define DECODE_ENABLE_MSS_PORT0 BIT(22) -#define DECODE_ENABLE_MSS_PORT1 BIT(23) -#define DECODE_ENABLE_MSS_PORT2 BIT(24) -#define DECODE_ENABLE_MSS_PORT3 BIT(25) -#define DECODE_ENABLE_FDC_PORT0 BIT(26) -#define DECODE_ENABLE_FDC_PORT1 BIT(27) -#define DECODE_ENABLE_GAME_PORT BIT(28) -#define DECODE_ENABLE_KBC_PORT BIT(29) -#define DECODE_ENABLE_ACPIUC_PORT BIT(30) -#define DECODE_ENABLE_ADLIB_PORT BIT(31) - -#define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 -#define LPC_WIDEIO2_ENABLE BIT(25) -#define LPC_WIDEIO1_ENABLE BIT(24) -#define DECODE_IO_PORT_ENABLE6 BIT(23) -#define DECODE_IO_PORT_ENABLE5 BIT(22) -#define DECODE_IO_PORT_ENABLE4 BIT(21) -#define DECODE_MEM_PORT_ENABLE1 BIT(20) -#define DECODE_IO_PORT_ENABLE3 BIT(19) -#define DECODE_IO_PORT_ENABLE2 BIT(18) -#define DECODE_IO_PORT_ENABLE1 BIT(17) -#define DECODE_IO_PORT_ENABLE0 BIT(16) -#define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) -#define LPC_DECODE_RTC_IO_ENABLE BIT(6) -#define DECODE_MEM_PORT_ENABLE0 BIT(5) -#define LPC_WIDEIO0_ENABLE BIT(2) -#define DECODE_ALTERNATE_SIO_ENABLE BIT(1) -#define DECODE_SIO_ENABLE BIT(0) -#define WIDEIO_RANGE_ERROR -1 -#define TOTAL_WIDEIO_PORTS 3 - -/* Assuming word access to higher word (register 0x4a) */ -#define LPC_IO_OR_MEM_DEC_EN_HIGH 0x4a -#define LPC_WIDEIO2_ENABLE_H BIT(9) -#define LPC_WIDEIO1_ENABLE_H BIT(8) -#define DECODE_IO_PORT_ENABLE6_H BIT(7) -#define DECODE_IO_PORT_ENABLE5_H BIT(6) -#define DECODE_IO_PORT_ENABLE4_H BIT(5) -#define DECODE_IO_PORT_ENABLE3_H BIT(3) -#define DECODE_IO_PORT_ENABLE2_H BIT(2) -#define DECODE_IO_PORT_ENABLE1_H BIT(1) -#define DECODE_IO_PORT_ENABLE0_H BIT(0) - -#define LPC_MEM_PORT1 0x4c -#define LPC_MEM_PORT0 0x60 - -/* Register 0x64 is 32-bit, composed by two 16-bit sub-registers. - For ease of access, each sub-register is declared separetely. */ -#define LPC_WIDEIO_GENERIC_PORT 0x64 -#define LPC_WIDEIO1_GENERIC_PORT 0x66 -#define ROM_ADDRESS_RANGE1_START 0x68 -#define ROM_ADDRESS_RANGE1_END 0x6a -#define ROM_ADDRESS_RANGE2_START 0x6c -#define ROM_ADDRESS_RANGE2_END 0x6e - -#define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 -#define LPC_ALT_WIDEIO2_ENABLE BIT(3) -#define LPC_ALT_WIDEIO1_ENABLE BIT(2) -#define LPC_ALT_WIDEIO0_ENABLE BIT(0) - -#define LPC_MISC_CONTROL_BITS 0x78 -#define LPC_NOHOG BIT(0) - -#define LPC_TRUSTED_PLATFORM_MODULE 0x7c -#define TPM_12_EN BIT(0) -#define TPM_LEGACY_EN BIT(2) - -#define LPC_WIDEIO2_GENERIC_PORT 0x90 - -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 -#define SPI_BASE_RESERVED (BIT(4) | BIT(5)) -#define ROUTE_TPM_2_SPI BIT(3) -#define SPI_ABORT_ENABLE BIT(2) -#define SPI_ROM_ENABLE BIT(1) -#define SPI_ROM_ALT_ENABLE BIT(0) -#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) - -/* LPC register 0xb8 is DWORD, here there are definitions for byte - access. For example, bits 31-24 are accessed through byte access - at register 0xbb. */ -#define LPC_ROM_DMA_EC_HOST_CONTROL 0xb8 -#define SPI_FROM_HOST_PREFETCH_EN BIT(24) -#define SPI_FROM_USB_PREFETCH_EN BIT(23) - -#define LPC_HOST_CONTROL 0xbb -#define PREFETCH_EN_SPI_FROM_HOST BIT(0) -#define T_START_ENH BIT(3) +/* SATA Controller D11F0 */ +#define SATA_MISC_CONTROL_REG 0x40 +#define SATA_MISC_SUBCLASS_WREN BIT(0) +/* Register in AHCIBaseAddress (BAR5 at D11F0x24) */ +#define SATA_CAPABILITIES_REG 0xfc +#define SATA_CAPABILITY_SPM BIT(12) /* SPI Controller (base address in D14F3xA0) */ +#define SPI_BASE_ALIGNMENT BIT(6) + #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) @@ -475,23 +356,13 @@ struct soc_power_reg { #define XHCI_FW_BOOTRAM_SIZE 0x8000 void enable_aoac_devices(void); -void sb_enable_rom(void); void sb_clk_output_48Mhz(u32 osc); void sb_disable_4dw_burst(void); void sb_enable(struct device *dev); void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); -void sb_lpc_port80(void); -void sb_lpc_decode(void); -void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void sb_tpm_decode(void); -void sb_tpm_decode_spi(void); -void lpc_wideio_512_window(uint16_t base); -void lpc_wideio_16_window(uint16_t base); -uint16_t pm_acpi_pm_cnt_blk(void); -uint16_t pm_acpi_pm_evt_blk(void); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** @@ -526,33 +397,6 @@ uint32_t get_uma_size(void); * @return 64bit base address */ uint64_t get_uma_base(void); -/** - * @brief Find the size of a particular wide IO - * - * @param index = index of desired wide IO - * - * @return size of desired wide IO - */ -uint16_t sb_wideio_size(int index); -/** - * @brief Identify if any LPC wide IO is covering the IO range - * - * @param start = start of IO range - * @param size = size of IO range - * - * @return Index of wide IO covering the range or error - */ -int sb_find_wideio_range(uint16_t start, uint16_t size); -/** - * @brief Program a LPC wide IO to support an IO range - * - * @param start = start of range to be routed through wide IO - * @param size = size of range to be routed through wide IO - * - * @return Index of wide IO register used or error - */ -int sb_set_wideio_range(uint16_t start, uint16_t size); - /* * Call the mainboard to get the USB Over Current Map. The mainboard * returns the map and 0 on Success or -1 on error or no map. There is @@ -568,10 +412,4 @@ void i2c_soc_early_init(void); /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); -/* - * If a system reset is about to be requested, modify the PM1 register so it - * will never be misinterpreted as an S3 resume. - */ -void set_pm1cnt_s5(void); - #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index 7367251193..59de34890f 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -25,29 +25,3 @@ int vbnv_cmos_failed(void) /* If CMOS power has failed, the century will be set to 0xff */ return cmos_read(RTC_CLK_ALTCENTURY) == 0xff; } - -int vboot_platform_is_resuming(void) -{ - if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS)) - return 0; - - uint16_t pm_cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); - return acpi_sleep_from_pm1(pm_cnt) == ACPI_S3; -} - -/* If a system reset is about to be requested, modify the PM1 register so it - * will never be misinterpreted as an S3 resume. */ -void set_pm1cnt_s5(void) -{ - uint16_t pm1; - - pm1 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); - pm1 &= ~SLP_TYP; - pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; - acpi_write16(MMIO_ACPI_PM1_CNT_BLK, pm1); -} - -void vboot_platform_prepare_reboot(void) -{ - set_pm1cnt_s5(); -} diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index 52932e27f0..6740698dd2 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -17,60 +17,32 @@ #include #include #include +#include +#include #include - -static void sata_init(struct device *dev) +void soc_enable_sata_features(struct device *dev) { - /************************************** - * Configure the SATA port multiplier * - **************************************/ - #define BYTE_TO_DWORD_OFFSET(x) (x/4) - #define AHCI_BASE_ADDRESS_REG 0x24 - #define MISC_CONTROL_REG 0x40 - #define UNLOCK_BIT (1<<0) - #define SATA_CAPABILITIES_REG 0xfc - #define CFG_CAP_SPM (1<<12) + u8 *ahci_ptr; + u32 misc_ctl, cap_cfg; - u32 *ahci_ptr = (void *)(uintptr_t)ALIGN_DOWN( - pci_read_config32(dev, AHCI_BASE_ADDRESS_REG), 256); u32 temp; /* unlock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp |= UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); + misc_ctl = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + misc_ctl |= SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, misc_ctl); /* set the SATA AHCI mode to allow port expanders */ - *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) - |= CFG_CAP_SPM; + ahci_ptr = (u8 *)(uintptr_t)ALIGN_DOWN( + pci_read_config32(dev, PCI_BASE_ADDRESS_5), 256); + + cap_cfg = read32(ahci_ptr + SATA_CAPABILITIES_REG); + cap_cfg |= SATA_CAPABILITY_SPM; + write32(ahci_ptr + SATA_CAPABILITIES_REG, cap_cfg); /* lock the write-protect */ - temp = pci_read_config32(dev, MISC_CONTROL_REG); - temp &= ~UNLOCK_BIT; - pci_write_config32(dev, MISC_CONTROL_REG, temp); -}; - -static struct pci_operations lops_pci = { - /* .set_subsystem = pci_dev_set_subsystem, */ -}; - -static struct device_operations sata_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = sata_init, - .ops_pci = &lops_pci, -}; - -static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_CZ_SATA, - PCI_DEVICE_ID_AMD_CZ_SATA_AHCI, - 0 -}; - -static const struct pci_driver sata0_driver __pci_driver = { - .ops = &sata_ops, - .vendor = PCI_VENDOR_ID_AMD, - .devices = pci_device_ids, + temp = pci_read_config32(dev, SATA_MISC_CONTROL_REG); + temp &= ~SATA_MISC_SUBCLASS_WREN; + pci_write_config32(dev, SATA_MISC_CONTROL_REG, temp); }; diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c deleted file mode 100644 index 11bf73a723..0000000000 --- a/src/soc/amd/stoneyridge/sb_util.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2017 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -uint16_t pm_acpi_pm_cnt_blk(void) -{ - return pm_read16(PM1_CNT_BLK); -} - -uint16_t pm_acpi_pm_evt_blk(void) -{ - return pm_read16(PM_EVT_BLK); -} - -int acpi_get_sleep_type(void) -{ - return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())); -} - -void save_uma_size(uint32_t size) -{ - biosram_write32(BIOSRAM_UMA_SIZE, size); -} - -void save_uma_base(uint64_t base) -{ - biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); - biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); -} - -uint32_t get_uma_size(void) -{ - return biosram_read32(BIOSRAM_UMA_SIZE); -} - -uint64_t get_uma_base(void) -{ - uint64_t base; - base = biosram_read32(BIOSRAM_UMA_BASE); - base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); - return base; -} diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index df7a86edc7..31457f98b8 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -189,79 +189,3 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) return 0; } - -void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - // printk(BIOS_DEBUG, "about write %x, index=%x", tmp, - // (reg_space&0x3)<<29 | reg_addr); - - /* probably we dont have to do it again. */ - outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val) -{ - u32 tmp; - - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - tmp = inl(AB_DATA); - /* rpr 4.2 - * For certain revisions of the chip, the ABCFG registers, - * with an address of 0x100NN (where 'N' is any hexadecimal - * number), require an extra programming step.*/ - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, - // (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); - - /* probably we dont have to do it again. */ - outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} - -/* - * space = 0: AX_INDXC, AX_DATAC - * space = 1: AX_INDXP, AX_DATAP - */ -void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val) -{ - u32 tmp; - - /* read axindc to tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - tmp = inl(AB_DATA); - outl(0, AB_INDX); - - tmp &= ~mask; - tmp |= val; - - /* write tmp */ - outl(space << 29 | space << 3 | 0x30, AB_INDX); - outl(axindc, AB_DATA); - outl(0, AB_INDX); - outl(space << 29 | space << 3 | 0x34, AB_INDX); - outl(tmp, AB_DATA); - outl(0, AB_INDX); -} diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c3aed578ff..d8438bb366 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -25,6 +25,7 @@ #include #include #include +#include #include /* bits in smm_io_trap */ @@ -88,19 +89,14 @@ static void southbridge_smi_gsmi(void) static void sb_apmc_smi_handler(void) { - u32 reg32; const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); switch (cmd) { case APM_CNT_ACPI_ENABLE: - reg32 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); - reg32 |= (1 << 0); /* SCI_EN */ - acpi_write32(MMIO_ACPI_PM1_CNT_BLK, reg32); + acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: - reg32 = acpi_read32(MMIO_ACPI_PM1_CNT_BLK); - reg32 &= ~(1 << 0); /* clear SCI_EN */ - acpi_write32(MMIO_ACPI_PM1_CNT_BLK, reg32); + acpi_disable_sci(); break; case APM_CNT_ELOG_GSMI: if (CONFIG(ELOG_GSMI)) @@ -203,7 +199,7 @@ static void sb_slp_typ_handler(void) * An IO cycle is required to trigger the STPCLK/STPGNT * handshake when the Pm1 write is reissued. */ - outw(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); + outw(pm1cnt | SLP_EN, pm_read16(PM1_CNT_BLK)); hlt(); } } diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 84db3dd76c..45408ead02 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -22,11 +22,12 @@ #include #include #include -#include #include #include #include #include +#include +#include #include #include #include @@ -152,130 +153,12 @@ const static struct irq_idx_name irq_association[] = { { PIRQ_UART1, "UART1" }, }; -/* - * Structure to simplify code obtaining the total of used wide IO - * registers and the size assigned to each. - */ -static struct wide_io_ioport_and_bits { - uint32_t enable; - uint16_t port; - uint8_t alt; -} wio_io_en[TOTAL_WIDEIO_PORTS] = { - { - LPC_WIDEIO0_ENABLE, - LPC_WIDEIO_GENERIC_PORT, - LPC_ALT_WIDEIO0_ENABLE - }, - { - LPC_WIDEIO1_ENABLE, - LPC_WIDEIO1_GENERIC_PORT, - LPC_ALT_WIDEIO1_ENABLE - }, - { - LPC_WIDEIO2_ENABLE, - LPC_WIDEIO2_GENERIC_PORT, - LPC_ALT_WIDEIO2_ENABLE - } -}; - const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) { *size = ARRAY_SIZE(irq_association); return irq_association; } -/** - * @brief Find the size of a particular wide IO - * - * @param index = index of desired wide IO - * - * @return size of desired wide IO - */ -uint16_t sb_wideio_size(int index) -{ - uint32_t enable_register; - uint16_t size = 0; - uint8_t alternate_register; - - if (index >= TOTAL_WIDEIO_PORTS) - return size; - enable_register = pci_read_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE); - alternate_register = pci_read_config8(SOC_LPC_DEV, - LPC_ALT_WIDEIO_RANGE_ENABLE); - if (enable_register & wio_io_en[index].enable) - size = (alternate_register & wio_io_en[index].alt) ? - 16 : 512; - return size; -} - -/** - * @brief Identify if any LPC wide IO is covering the IO range - * - * @param start = start of IO range - * @param size = size of IO range - * - * @return Index of wide IO covering the range or error - */ -int sb_find_wideio_range(uint16_t start, uint16_t size) -{ - int i, index = WIDEIO_RANGE_ERROR; - uint16_t end, current_size, start_wideio, end_wideio; - - end = start + size; - for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { - current_size = sb_wideio_size(i); - if (current_size == 0) - continue; - start_wideio = pci_read_config16(SOC_LPC_DEV, - wio_io_en[i].port); - end_wideio = start_wideio + current_size; - if ((start >= start_wideio) && (end <= end_wideio)) { - index = i; - break; - } - } - return index; -} - -/** - * @brief Program a LPC wide IO to support an IO range - * - * @param start = start of range to be routed through wide IO - * @param size = size of range to be routed through wide IO - * - * @return Index of wide IO register used or error - */ -int sb_set_wideio_range(uint16_t start, uint16_t size) -{ - int i, index = WIDEIO_RANGE_ERROR; - uint32_t enable_register; - uint8_t alternate_register; - - enable_register = pci_read_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE); - alternate_register = pci_read_config8(SOC_LPC_DEV, - LPC_ALT_WIDEIO_RANGE_ENABLE); - for (i = 0; i < TOTAL_WIDEIO_PORTS; i++) { - if (enable_register & wio_io_en[i].enable) - continue; - index = i; - pci_write_config16(SOC_LPC_DEV, wio_io_en[i].port, start); - enable_register |= wio_io_en[i].enable; - pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, - enable_register); - if (size <= 16) - alternate_register |= wio_io_en[i].alt; - else - alternate_register &= ~wio_io_en[i].alt; - pci_write_config8(SOC_LPC_DEV, - LPC_ALT_WIDEIO_RANGE_ENABLE, - alternate_register); - break; - } - return index; -} - static void power_on_aoac_device(int aoac_device_control_register) { uint8_t byte; @@ -315,16 +198,7 @@ void enable_aoac_devices(void) } while (!status); } -void sb_pci_port80(void) -{ - u8 byte; - - byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte &= ~DECODE_IO_PORT_ENABLE4_H; /* disable lpc port 80 */ - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); -} - -void sb_lpc_port80(void) +static void sb_enable_lpc(void) { u8 byte; @@ -332,14 +206,9 @@ void sb_lpc_port80(void) byte = pm_io_read8(PM_LPC_GATING); byte |= PM_LPC_ENABLE; pm_io_write8(PM_LPC_GATING, byte); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH); - byte |= DECODE_IO_PORT_ENABLE4_H; /* enable port 80 */ - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH, byte); } -void sb_lpc_decode(void) +static void sb_lpc_decode(void) { u32 tmp = 0; @@ -357,7 +226,11 @@ void sb_lpc_decode(void) | DECODE_ENABLE_KBC_PORT | DECODE_ENABLE_ACPIUC_PORT | DECODE_ENABLE_ADLIB_PORT; - pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, tmp); + /* Decode SIOs at 2E/2F and 4E/4F */ + if (CONFIG(STONEYRIDGE_LEGACY_FREE)) + tmp |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; + + lpc_enable_decode(tmp); } static void sb_enable_cf9_io(void) @@ -397,27 +270,23 @@ void sb_clk_output_48Mhz(u32 osc) misc_write32(MISC_CLK_CNTL1, ctrl); } -static uintptr_t sb_spibase(void) +static uintptr_t sb_init_spi_base(void) { - u32 base, enables; + uintptr_t base; /* Make sure the base address is predictable */ - base = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); - enables = base & SPI_PRESERVE_BITS; - base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED); + base = lpc_get_spibase(); - if (!base) { - base = SPI_BASE_ADDRESS; - pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, - base | enables | SPI_ROM_ENABLE); - /* PCI_COMMAND_MEMORY is read-only and enabled. */ - } - return (uintptr_t)base; + if (base) + return base; + + lpc_set_spibase(SPI_BASE_ADDRESS, SPI_ROM_ENABLE); + return SPI_BASE_ADDRESS; } void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = sb_spibase(); + uintptr_t base = sb_init_spi_base(); write16((void *)(base + SPI100_SPEED_CONFIG), (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | @@ -428,7 +297,7 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) void sb_disable_4dw_burst(void) { - uintptr_t base = sb_spibase(); + uintptr_t base = sb_init_spi_base(); write16((void *)(base + SPI100_HOST_PREF_CONFIG), read16((void *)(base + SPI100_HOST_PREF_CONFIG)) & ~SPI_RD4DW_EN_HOST); @@ -436,115 +305,12 @@ void sb_disable_4dw_burst(void) void sb_read_mode(u32 mode) { - uintptr_t base = sb_spibase(); + uintptr_t base = sb_init_spi_base(); write32((void *)(base + SPI_CNTRL0), (read32((void *)(base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK) | mode); } -/* - * Enable FCH to decode TPM associated Memory and IO regions - * - * Enable decoding of TPM cycles defined in TPM 1.2 spec - * Enable decoding of legacy TPM addresses: IO addresses 0x7f- - * 0x7e and 0xef-0xee. - * This function should be called if TPM is connected in any way to the FCH and - * conforms to the regions decoded. - * Absent any other routing configuration the TPM cycles will be claimed by the - * LPC bus - */ -void sb_tpm_decode(void) -{ - u32 value; - - value = pci_read_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE); - value |= TPM_12_EN | TPM_LEGACY_EN; - pci_write_config32(SOC_LPC_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); -} - -/* - * Enable FCH to decode TPM associated Memory and IO regions to SPI - * - * This should be used if TPM is connected to SPI bus. - * Assumes SPI address space is already configured via a call to sb_spibase(). - */ -void sb_tpm_decode_spi(void) -{ - /* Enable TPM decoding to FCH */ - sb_tpm_decode(); - - /* Route TPM accesses to SPI */ - u32 spibase = pci_read_config32(SOC_LPC_DEV, - SPIROM_BASE_ADDRESS_REGISTER); - pci_write_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase - | ROUTE_TPM_2_SPI); -} - -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The southbridge power-on default is to map 512K ROM space. - * - */ -void sb_enable_rom(void) -{ - u8 reg8; - - /* - * Decode variable LPC ROM address ranges 1 and 2. - * Bits 3-4 are not defined in any publicly available datasheet - */ - reg8 = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); - reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg8); - - /* - * LPC ROM address range 1: - * Enable LPC ROM range mirroring start at 0x000e(0000). - */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_START, 0x000e); - - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE1_END, 0x000f); - - /* - * LPC ROM address range 2: - * - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_START, 0x10000 - - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(SOC_LPC_DEV, ROM_ADDRESS_RANGE2_END, 0xffff); -} - -static void sb_lpc_early_setup(void) -{ - uint32_t dword; - - /* Enable SPI prefetch */ - dword = pci_read_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL); - dword |= SPI_FROM_HOST_PREFETCH_EN | SPI_FROM_USB_PREFETCH_EN; - pci_write_config32(SOC_LPC_DEV, LPC_ROM_DMA_EC_HOST_CONTROL, dword); - - if (CONFIG(STONEYRIDGE_LEGACY_FREE)) { - /* Decode SIOs at 2E/2F and 4E/4F */ - dword = pci_read_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE); - dword |= DECODE_ALTERNATE_SIO_ENABLE | DECODE_SIO_ENABLE; - pci_write_config32(SOC_LPC_DEV, - LPC_IO_OR_MEM_DECODE_ENABLE, dword); - } -} - static void setup_spread_spectrum(int *reboot) { uint16_t rstcfg = pm_read16(PWR_RESET_CFG); @@ -627,11 +393,12 @@ void bootblock_fch_early_init(void) { int reboot = 0; - sb_enable_rom(); - sb_lpc_port80(); + lpc_enable_rom(); + sb_enable_lpc(); + lpc_enable_port80(); sb_lpc_decode(); - sb_lpc_early_setup(); - sb_spibase(); + lpc_enable_spi_prefetch(); + sb_init_spi_base(); sb_disable_4dw_burst(); /* Must be disabled on CZ(ST) */ enable_acpimmio_decode(); fch_smbus_init(); @@ -755,83 +522,6 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -static uint16_t reset_pm1_status(void) -{ - uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); - acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); - return pm1_sts; -} - -static uint16_t print_pm1_status(uint16_t pm1_sts) -{ - static const char *const pm1_sts_bits[16] = { - [0] = "TMROF", - [4] = "BMSTATUS", - [5] = "GBL", - [8] = "PWRBTN", - [10] = "RTC", - [14] = "PCIEXPWAK", - [15] = "WAK", - }; - - if (!pm1_sts) - return 0; - - printk(BIOS_DEBUG, "PM1_STS: "); - print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_DEBUG, "\n"); - - return pm1_sts; -} - -static void sb_log_pm1_status(uint16_t pm1_sts) -{ - if (!CONFIG(ELOG)) - return; - - if (pm1_sts & WAK_STS) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? ACPI_S3 : ACPI_S5); - - if (pm1_sts & PWRBTN_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - - if (pm1_sts & RTC_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - - if (pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); -} - -static void sb_save_sws(uint16_t pm1_status) -{ - struct soc_power_reg *sws; - uint32_t reg32; - uint16_t reg16; - - sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); - if (sws == NULL) - return; - sws->pm1_sts = pm1_status; - sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); - reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); - acpi_write32(MMIO_ACPI_GPE0_STS, reg32); - sws->gpe0_sts = reg32; - sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); - reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); - reg16 &= SLP_TYP; - sws->wake_from = reg16 >> SLP_TYP_SHIFT; -} - -static void sb_clear_pm1_status(void) -{ - uint16_t pm1_sts = reset_pm1_status(); - - sb_save_sws(pm1_sts); - sb_log_pm1_status(pm1_sts); - print_pm1_status(pm1_sts); -} - static int get_index_bit(uint32_t value, uint16_t limit) { uint16_t i; @@ -884,7 +574,7 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); void southbridge_init(void *chip_info) { sb_init_acpi_ports(); - sb_clear_pm1_status(); + acpi_clear_pm1_status(); } static void set_sb_final_nvs(void) @@ -959,3 +649,27 @@ static void set_pci_irqs(void *unused) * on entry into BS_DEV_ENABLE. */ BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); + +void save_uma_size(uint32_t size) +{ + biosram_write32(BIOSRAM_UMA_SIZE, size); +} + +void save_uma_base(uint64_t base) +{ + biosram_write32(BIOSRAM_UMA_BASE, (uint32_t) base); + biosram_write32(BIOSRAM_UMA_BASE + 4, (uint32_t) (base >> 32)); +} + +uint32_t get_uma_size(void) +{ + return biosram_read32(BIOSRAM_UMA_SIZE); +} + +uint64_t get_uma_base(void) +{ + uint64_t base; + base = biosram_read32(BIOSRAM_UMA_BASE); + base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); + return base; +} diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index c682d980bb..8abfa160f4 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) @@ -103,11 +104,7 @@ static int execute_command(void) void spi_init(void) { - uintptr_t bar; - - bar = pci_read_config32(SOC_LPC_DEV, SPIROM_BASE_ADDRESS_REGISTER); - bar = ALIGN_DOWN(bar, 64); - set_spibar(bar); + set_spibar(lpc_get_spibase()); } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index b272a99efe..16d14d945f 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -91,7 +91,9 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) dram_part_num, strlen(dram_part_num), NULL, /* SPD not available */ - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + 0, + 0); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 29dcd56767..59e133076a 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -97,7 +97,9 @@ void save_lpddr4_dimm_info_part_num(const char *dram_part_num) dram_part_num, strlen(dram_part_num), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + 0, + 0); index++; } } diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ed5c9728a3..920179f834 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -51,15 +51,23 @@ config CPU_SPECIFIC_OPTIONS select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select C_ENVIRONMENT_BOOTBLOCK + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/braswell/bootblock/bootblock.c" - config MMCONF_BASE_ADDRESS hex default 0xe0000000 diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index e479a3c5e5..1017d80c65 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -9,9 +9,14 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += gpio_support.c +bootblock-y += bootblock/bootblock.c +bootblock-y += lpc_init.c +bootblock-y += pmutil.c +bootblock-y += tsc_freq.c + romstage-y += gpio_support.c romstage-y += iosf.c -romstage-y += lpc_init.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += smbus.c diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 457b8b895d..2d1a3e8687 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google, Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,37 +15,93 @@ * GNU General Public License for more details. */ +#include +#include +#include #include -#include -#include -#include +#include +#include +#include +#include #include -#include +#include +#include +#include -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); + /* Call lib/bootblock.c main */ + bootblock_main_with_timestamp(base_timestamp, NULL, 0); } -static void enable_rom_caching(void) +static void program_base_addresses(void) { - msr_t msr; + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +static void spi_init(void) +{ + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +static void soc_rtc_init(void) +{ + int rtc_failed = rtc_failure(); + + if (rtc_failed) { + printk(BIOS_ERR, + "RTC Failure detected. Resetting date to %x/%x/%x%x\n", + COREBOOT_BUILD_MONTH_BCD, + COREBOOT_BUILD_DAY_BCD, + 0x20, + COREBOOT_BUILD_YEAR_BCD); + } + + cmos_init(rtc_failed); } static void setup_mmconfig(void) @@ -67,12 +124,22 @@ static void setup_mmconfig(void) pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) + +void bootblock_soc_early_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); +} +void bootblock_soc_init(void) +{ + /* Continue chipset initialization */ + soc_rtc_init(); + set_max_freq(); + spi_init(); + + lpc_init(); } diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/include/soc/bootblock.h similarity index 68% rename from src/soc/intel/braswell/romstage/pmc.c rename to src/soc/intel/braswell/include/soc/bootblock.h index 127458e59c..e6e25ccbb1 100644 --- a/src/soc/intel/braswell/romstage/pmc.c +++ b/src/soc/intel/braswell/include/soc/bootblock.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,15 +14,9 @@ * GNU General Public License for more details. */ -#include -#include -#include +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ -void tco_disable(void) -{ - uint32_t reg; +void set_max_freq(void); - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} +#endif /* _SOC_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index 4ecbd2c1f9..9fad9bc5a0 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -23,12 +23,10 @@ #include void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); -/* romstage_common.c functions */ -void program_base_addresses(void); +/* romstage.c functions */ int chipset_prev_sleep_state(struct chipset_power_state *ps); /* Values for FSP's PcdMemoryTypeEnable */ diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 3d3e407a29..d405133110 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,3 +1,2 @@ romstage-y += ../../../../cpu/intel/car/romstage.c -romstage-y += pmc.c romstage-y += romstage.c diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 8dfc291d1e..e0e22f220e 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -19,90 +19,13 @@ #include #include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include #include #include -#include -#include #include -#include -#include -#include -#include #include "../chip.h" -void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - void *scs = (void *)(SPI_BASE_ADDRESS + SCS); - void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - -static void soc_rtc_init(void) -{ - int rtc_failed = rtc_failure(); - - if (rtc_failed) { - printk(BIOS_ERR, - "RTC Failure detected. Resetting date to %x/%x/%x%x\n", - COREBOOT_BUILD_MONTH_BCD, - COREBOOT_BUILD_DAY_BCD, - 0x20, - COREBOOT_BUILD_YEAR_BCD); - } - - cmos_init(rtc_failed); -} static struct chipset_power_state power_state; @@ -171,24 +94,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps) return prev_sleep_state; } -/* SOC initialization before the console is enabled */ -void car_soc_pre_console_init(void) -{ - /* Early chipset initialization */ - program_base_addresses(); - tco_disable(); -} - -/* SOC initialization after console is enabled */ -void car_soc_post_console_init(void) -{ - /* Continue chipset initialization */ - soc_rtc_init(); - set_max_freq(); - spi_init(); - - lpc_init(); -} /* SOC initialization after RAM is enabled */ void soc_after_ram_init(struct romstage_params *params) diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 76906b2548..dac3522d0a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -107,6 +107,7 @@ config CPU_SPECIFIC_OPTIONS select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO select FSP_T_XIP if FSP_CAR + select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl index cdfff911b8..0012a4dfd8 100644 --- a/src/soc/intel/cannonlake/acpi/scs.asl +++ b/src/soc/intel/cannonlake/acpi/scs.asl @@ -84,6 +84,7 @@ Scope (\_SB.PCI0) { Name (_ADR, 0x00140005) Name (_DDN, "SD Controller") Name (TEMP, 0) + Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61")) OperationRegion (SDPC, PCI_Config, 0x00, 0x100) Field (SDPC, WordAcc, NoLock, Preserve) @@ -95,6 +96,67 @@ Scope (\_SB.PCI0) { PGEN, 1, /* PG_ENABLE */ } + /* _DSM x86 Device Specific Method + * Arg0: UUID Unique function identifier + * Arg1: Integer Revision Level + * Arg2: Integer Function Index (0 = Return Supported Functions) + * Arg3: Package Parameters + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^DSUU)) { + /* Check the revision */ + If (LGreaterEqual (Arg1, Zero)) { + /* Switch statement based on the function index. */ + Switch (ToInteger (Arg2)) { + /* + * Function Index 0 the return value is a buffer containing + * one bit for each function index, starting with zero. + * Bit 0 - Indicates whether there is support for any functions other than function 0. + * Bit 1 - Indicates support to clear power control register + * Bit 2 - Indicates support to set power control register + * Bit 3 - Indicates support to set 1.8V signalling + * Bit 4 - Indicates support to set 3.3V signalling + * Bit 5 - Indicates support for HS200 mode + * Bit 6 - Indicates support for HS400 mode + * Bit 9 - Indicates eMMC I/O Driver Strength + */ + /* + * For SD we have to support functions to + * set 1.8V signalling and 3.3V signalling [BIT4, BIT3] + */ + Case (0) { + Return (Buffer () { 0x19 }) + } + + /* + * Function Index 3: Set 1.8v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + Case (3) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + /* + * Function Index 4: Set 3.3v signalling. + * We put a sleep of 100ms in this method to + * work around a known issue with detecting + * UHS SD card on PCH. This is to compensate + * for the SD VR slowness. + */ + Case (4) { + Sleep (100) + Return(Buffer () { 0x00 }) + } + } + } + } + Return(Buffer() { 0x0 }) + } + Method(_INI) { /* Clear register 0x1C20/0x4820 */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb73a..77bad8f627 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -50,7 +50,11 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif /* * PcdDebugInterfaceFlags * This config will allow coreboot to pass information to the FSP diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 98d4c006a8..fa530a29a6 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -101,6 +101,8 @@ static void save_dimm_info(void) mainboard_get_dram_part_num(&dram_part_num, &dram_part_num_len); + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -112,7 +114,9 @@ static void save_dimm_info(void) dram_part_num, dram_part_num_len, src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c index 9af291700b..e8f0d17833 100644 --- a/src/soc/intel/cannonlake/smihandler.c +++ b/src/soc/intel/cannonlake/smihandler.c @@ -88,7 +88,7 @@ void smihandler_soc_at_finalize(void) config = dev->chip_info; - if (config->HeciEnabled == 0) + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); } diff --git a/src/soc/intel/common/block/graphics/Kconfig b/src/soc/intel/common/block/graphics/Kconfig index 4ab92001c3..36cac22ec9 100644 --- a/src/soc/intel/common/block/graphics/Kconfig +++ b/src/soc/intel/common/block/graphics/Kconfig @@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_GRAPHICS bool help Intel Processor common Graphics support + +config SKIP_GRAPHICS_ENABLING + bool + depends on SOC_INTEL_COMMON_BLOCK_GRAPHICS + default n + help + Skip GT specific programming in coreboot to support + early parts without GT enable. diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 86547a443f..54c7706f6e 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -124,8 +124,8 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM, + PCI_DEVICE_ID_INTEL_SPT_H_CM236, PCI_DEVICE_ID_INTEL_SPT_H_C236, - PCI_DEVICE_ID_INTEL_KBP_H_C236, PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM, PCI_DEVICE_ID_INTEL_SPT_H_H110, PCI_DEVICE_ID_INTEL_SPT_H_H170, @@ -156,13 +156,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, - PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, - PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, - PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, - PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, + PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, + PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, + PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, + PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index a58c63102d..ab5ee03a6d 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -23,3 +23,11 @@ config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI. + +config HECI_DISABLE_USING_SMM + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + HECI disable using SMM. Select this option to make HECI disable + using SMM mode, independent of dedicated UPD to perform HECI disable. diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 281a7f7655..a93db65af6 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -341,6 +341,9 @@ static const unsigned short systemagent_ids[] = { PCI_DEVICE_ID_INTEL_SKL_ID_Y, PCI_DEVICE_ID_INTEL_SKL_ID_ULX, PCI_DEVICE_ID_INTEL_SKL_ID_H, + PCI_DEVICE_ID_INTEL_SKL_ID_H_2, + PCI_DEVICE_ID_INTEL_SKL_ID_S_2, + PCI_DEVICE_ID_INTEL_SKL_ID_S_4, PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, PCI_DEVICE_ID_INTEL_KBL_ID_S, diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index d89e9d5827..e3ed3a2e69 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -22,7 +22,8 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width) + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support) { dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; @@ -30,6 +31,12 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; + if (vdd_voltage > 0xFFFF) { + dimm->vdd_voltage = 0xFFFF; + } else { + dimm->vdd_voltage = vdd_voltage; + } + strncpy((char *)dimm->module_part_number, module_part_num, min(sizeof(dimm->module_part_number), @@ -57,4 +64,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, printk(BIOS_NOTICE, "Incorrect DIMM Data width: %u\n", (unsigned int)data_width); } + + if (ecc_support) + dimm->bus_width |= 0x8; } diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 5824f5d665..12b8da0d85 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -26,6 +26,7 @@ void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, - const u8 *module_serial_num, u16 data_width); + const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, + bool ecc_support); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 052e37dadb..f0b291877d 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_2017_BINDING select DISPLAY_FSP_VERSION_INFO + select HECI_DISABLE_USING_SMM config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index cd6a6ba842..0d4e32d131 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -13,19 +13,19 @@ bootblock-y += bootblock/cpu.c bootblock-y += bootblock/pch.c bootblock-y += pmutil.c bootblock-y += bootblock/report_platform.c +bootblock-y += espi.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c -bootblock-y += lpc.c bootblock-y += p2sb.c bootblock-y += uart.c +romstage-y += espi.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += i2c.c -romstage-y += lpc.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -36,6 +36,7 @@ ramstage-y += acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c +ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c ramstage-y += gpio.c @@ -44,7 +45,6 @@ ramstage-y += gspi.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += lockdown.c -ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c index f16469eb63..3a46c930ab 100644 --- a/src/soc/intel/icelake/acpi.c +++ b/src/soc/intel/icelake/acpi.c @@ -169,7 +169,7 @@ void soc_power_states_generation(int core_id, int cores_per_package) void soc_fill_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = pcidev_on_root(0, 0); const struct soc_intel_icelake_config *config = dev->chip_info; if (!config->PmTimerDisabled) { @@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void) void acpi_create_gnvs(struct global_nvs_t *gnvs) { - const struct device *dev = PCH_DEV_LPC; + const struct device *dev = pcidev_on_root(0, 0); const struct soc_intel_icelake_config *config = dev->chip_info; /* Set unknown wake source */ diff --git a/src/soc/intel/icelake/acpi/lpc.asl b/src/soc/intel/icelake/acpi/espi.asl similarity index 96% rename from src/soc/intel/icelake/acpi/lpc.asl rename to src/soc/intel/icelake/acpi/espi.asl index f936392ea3..4456812ba6 100644 --- a/src/soc/intel/icelake/acpi/lpc.asl +++ b/src/soc/intel/icelake/acpi/espi.asl @@ -13,10 +13,12 @@ * GNU General Public License for more details. */ + +/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */ Device (LPCB) { Name (_ADR, 0x001f0000) - Name (_DDN, "LPC Bus Device") + Name (_DDN, "ESPI Bus Device") Device (FWH) { diff --git a/src/soc/intel/icelake/acpi/southbridge.asl b/src/soc/intel/icelake/acpi/southbridge.asl index 1b9abe6b63..ffd2fcca71 100644 --- a/src/soc/intel/icelake/acpi/southbridge.asl +++ b/src/soc/intel/icelake/acpi/southbridge.asl @@ -32,8 +32,8 @@ /* GPIO controller */ #include "gpio.asl" -/* LPC 0:1f.0 */ -#include "lpc.asl" +/* ESPI 0:1f.0 */ +#include "espi.asl" /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 094079140d..aefcaa5a47 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include #include #include +#include #include -#include #include #include #include @@ -145,8 +145,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); } diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e4d2..a9eef40756 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -46,16 +46,16 @@ static struct { }; static struct { - u16 lpcid; + u16 espiid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, }; static struct { @@ -170,18 +170,18 @@ static void report_mch_info(void) static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; - uint16_t lpcid = get_dev_id(dev); + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); const char *pch_type = "Unknown"; for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { + if (pch_table[i].espiid == espiid) { pch_type = pch_table[i].name; break; } } printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, get_dev_revision(dev), pch_type); + espiid, get_dev_revision(dev), pch_type); } static void report_igd_info(void) diff --git a/src/soc/intel/icelake/chip.c b/src/soc/intel/icelake/chip.c index 2616db1768..eff1c7a17c 100644 --- a/src/soc/intel/icelake/chip.c +++ b/src/soc/intel/icelake/chip.c @@ -89,7 +89,8 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_GSPI2: return "SPI2"; case PCH_DEVFN_EMMC: return "EMMC"; case PCH_DEVFN_SDCARD: return "SDXC"; - case PCH_DEVFN_LPC: return "LPCB"; + /* Keeping ACPI device name coherent with ec.asl */ + case PCH_DEVFN_ESPI: return "LPCB"; case PCH_DEVFN_P2SB: return "P2SB"; case PCH_DEVFN_PMC: return "PMC_"; case PCH_DEVFN_HDA: return "HDAS"; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 77611262a3..028f6b2c31 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -254,10 +254,6 @@ struct soc_intel_icelake_config { /* Enable Pch iSCLK */ uint8_t pch_isclk; - /* Intel VT configuration */ - uint8_t VtdDisable; - uint8_t VmxEnable; - /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ enum { PLATFORM_POR, diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/espi.c similarity index 90% rename from src/soc/intel/icelake/lpc.c rename to src/soc/intel/icelake/espi.c index 3d05824279..9ca0c7c295 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/espi.c @@ -24,9 +24,9 @@ #include #include #include +#include #include #include -#include #include #include @@ -71,10 +71,10 @@ uint8_t get_pch_series(void) uint16_t lpc_did_hi_byte; /* - * Fetch upper 8 bits on LPC device ID to determine PCH type + * Fetch upper 8 bits on ESPI device ID to determine PCH type * Adding 1 to the offset to fetch upper 8 bits */ - lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1); + lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1); if (lpc_did_hi_byte == 0x9D) return PCH_LP; @@ -87,11 +87,12 @@ uint8_t get_pch_series(void) #if ENV_RAMSTAGE static void soc_mirror_dmi_pcr_io_dec(void) { + struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0); uint32_t io_dec_arr[] = { - pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC), - pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC), + pci_read_config32(dev, ESPI_GEN1_DEC), + pci_read_config32(dev, ESPI_GEN2_DEC), + pci_read_config32(dev, ESPI_GEN3_DEC), + pci_read_config32(dev, ESPI_GEN4_DEC), }; /* Mirror these same settings in DMI PCR */ soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]); @@ -215,10 +216,10 @@ void lpc_soc_init(struct device *dev) isa_dma_init(); pch_misc_init(); - /* Enable CLKRUN_EN for power gating LPC */ + /* Enable CLKRUN_EN for power gating ESPI */ lpc_enable_pci_clk_cntl(); - /* Set LPC Serial IRQ mode */ + /* Set ESPI Serial IRQ mode */ if (CONFIG(SERIRQ_CONTINUOUS_MODE)) lpc_set_serirq_mode(SERIRQ_CONTINUOUS); else @@ -233,13 +234,13 @@ void lpc_soc_init(struct device *dev) soc_mirror_dmi_pcr_io_dec(); } -/* Fill up LPC IO resource structure inside SoC directory */ +/* Fill up ESPI IO resource structure inside SoC directory */ void pch_lpc_soc_fill_io_resources(struct device *dev) { /* * PMC pci device gets hidden from PCI bus due to Silicon * policy hence bind ACPI BASE aka ABASE (offset 0x20) with - * LPC IO resources to ensure that ABASE falls under PCI reserved + * ESPI IO resources to ensure that ABASE falls under PCI reserved * IO memory range. * * Note: Don't add any more resource with same offset 0x20 diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 513ef0014c..ac7edd2dbb 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -13,14 +13,203 @@ * GNU General Public License for more details. */ +#include #include +#include +#include #include +#include +#include +#include +#include #include +#include +#include +#include + +static void parse_devicetree(FSP_S_CONFIG *params) +{ + struct device *dev = pcidev_on_root(0, 0); + if (!dev) { + printk(BIOS_ERR, "Could not find root device\n"); + return; + } + + const struct soc_intel_icelake_config *config = dev->chip_info; + + for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) + params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; + + for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { + params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; + params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; + params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; + } + + for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) + params->SerialIoUartMode[i] = config->SerialIoUartMode[i]; +} /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - /* ToDo: update with UPD override as FSP matures */ + int i; + FSP_S_CONFIG *params = &supd->FspsConfig; + struct device *dev = SA_DEV_ROOT; + config_t *config = dev->chip_info; + + /* Parse device tree and enable/disable devices */ + parse_devicetree(params); + + /* Load VBT before devicetree-specific config. */ + params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + + /* Set USB OC pin to 0 first */ + for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) + params->Usb2OverCurrentPin[i] = 0; + + for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) + params->Usb3OverCurrentPin[i] = 0; + + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) { + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + params->SkipMpInit = 0; + } else { + params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + } + + mainboard_silicon_init_params(params); + + params->PeiGraphicsPeimInit = 1; + params->GtFreqMax = 2; + params->CdClock = 3; + /* Unlock upper 8 bytes of RTC RAM */ + params->PchLockDownRtcMemoryLock = 0; + + params->CnviBtAudioOffload = config->CnviBtAudioOffload; + /* SATA */ + dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0); + if (!dev) + params->SataEnable = 0; + else { + params->SataEnable = dev->enabled; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + } + + /* Lan */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + + /* Audio */ + params->PchHdaDspEnable = config->PchHdaDspEnable; + params->PchHdaAudioLinkHda = config->PchHdaAudioLinkHda; + params->PchHdaAudioLinkDmic0 = config->PchHdaAudioLinkDmic0; + params->PchHdaAudioLinkDmic1 = config->PchHdaAudioLinkDmic1; + params->PchHdaAudioLinkSsp0 = config->PchHdaAudioLinkSsp0; + params->PchHdaAudioLinkSsp1 = config->PchHdaAudioLinkSsp1; + params->PchHdaAudioLinkSsp2 = config->PchHdaAudioLinkSsp2; + params->PchHdaAudioLinkSndw1 = config->PchHdaAudioLinkSndw1; + params->PchHdaAudioLinkSndw2 = config->PchHdaAudioLinkSndw2; + params->PchHdaAudioLinkSndw3 = config->PchHdaAudioLinkSndw3; + params->PchHdaAudioLinkSndw4 = config->PchHdaAudioLinkSndw4; + + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + /* S0ix */ + params->PchPmSlpS0Enable = config->s0ix_enable; + + /* USB */ + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2OverCurrentPin[i] = + config->usb2_ports[i].ocpin; + params->Usb2PhyPetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2PhyTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2PhyPredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2PhyPehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + /* Enable xDCI controller if enabled in devicetree and allowed */ + dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1); + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + + /* PCI Express */ + for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { + if (config->PcieClkSrcUsage[i] == 0) + config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; + } + memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, + sizeof(config->PcieClkSrcUsage)); + memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, + sizeof(config->PcieClkSrcClkReq)); + + /* eMMC */ + dev = pcidev_on_root(PCH_DEV_SLOT_STORAGE, 0); + if (!dev) + params->ScsEmmcEnabled = 0; + else { + params->ScsEmmcEnabled = dev->enabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->EmmcUseCustomDlls = config->EmmcUseCustomDlls; + if (config->EmmcUseCustomDlls == 1) { + params->EmmcTxCmdDelayRegValue = + config->EmmcTxCmdDelayRegValue; + params->EmmcTxDataDelay1RegValue = + config->EmmcTxDataDelay1RegValue; + params->EmmcTxDataDelay2RegValue = + config->EmmcTxDataDelay2RegValue; + params->EmmcRxCmdDataDelay1RegValue = + config->EmmcRxCmdDataDelay1RegValue; + params->EmmcRxCmdDataDelay2RegValue = + config->EmmcRxCmdDataDelay2RegValue; + params->EmmcRxStrobeDelayRegValue = + config->EmmcRxStrobeDelayRegValue; + } + } + + /* SD */ + dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 5); + if (!dev) + params->ScsSdCardEnabled = 0; + else { + params->ScsSdCardEnabled = dev->enabled; + params->SdCardPowerEnableActiveHigh = + config->SdCardPowerEnableActiveHigh; + } + + params->Heci3Enabled = config->Heci3Enabled; + params->Device4Enable = config->Device4Enable; } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/icelake/graphics.c b/src/soc/intel/icelake/graphics.c index 0fbddf06e9..07090331cb 100644 --- a/src/soc/intel/icelake/graphics.c +++ b/src/soc/intel/icelake/graphics.c @@ -34,6 +34,10 @@ void graphics_soc_init(struct device *dev) { uint32_t ddi_buf_ctl; + /* Skip IGD GT programming */ + if (CONFIG(SKIP_GRAPHICS_ENABLING)) + return; + /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/espi.h similarity index 67% rename from src/soc/intel/icelake/include/soc/lpc.h rename to src/soc/intel/icelake/include/soc/espi.h index ebfcaa867f..36ee9470ae 100644 --- a/src/soc/intel/icelake/include/soc/lpc.h +++ b/src/soc/intel/icelake/include/soc/espi.h @@ -13,12 +13,12 @@ * GNU General Public License for more details. */ -#ifndef _SOC_ICELAKE_LPC_H_ -#define _SOC_ICELAKE_LPC_H_ +#ifndef _SOC_ICELAKE_ESPI_H_ +#define _SOC_ICELAKE_ESPI_H_ #include -/* PCI Configuration Space (D31:F0): LPC */ +/* PCI Configuration Space (D31:F0): ESPI */ #define SCI_IRQ_SEL (7 << 0) #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 @@ -28,19 +28,14 @@ #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 #define SERIRQ_CNTL 0x64 -#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */ #define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/ #define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/ -#define LPC_EN 0x82 /* LPC IF Enables Register */ -#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ -#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ -#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ -#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -#define LGMR 0x98 /* LPC Generic Memory Range */ -#define BIOS_CNTL 0xdc -#define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 1) /* LE */ -#define LPC_BC_EISS (1 << 5) /* EISS */ +#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */ +#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */ +#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */ +#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */ +#define LGMR 0x98 /* ESPI Generic Memory Range */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 3cb0617249..889b5c5dde 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -171,22 +171,24 @@ #define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2) #define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3) -#define PCH_DEV_SLOT_LPC 0x1f -#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) -#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1) -#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2) -#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3) -#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4) -#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5) -#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6) -#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_P2SB _PCH_DEV(LPC, 1) -#define PCH_DEV_PMC _PCH_DEV(LPC, 2) -#define PCH_DEV_HDA _PCH_DEV(LPC, 3) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4) -#define PCH_DEV_SPI _PCH_DEV(LPC, 5) -#define PCH_DEV_GBE _PCH_DEV(LPC, 6) -#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7) +#define PCH_DEV_SLOT_ESPI 0x1f +#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI +#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) +#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) +#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) +#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4) +#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5) +#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6) +#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7) +#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0) +#define PCH_DEV_LPC PCH_DEV_ESPI +#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1) +#define PCH_DEV_PMC _PCH_DEV(ESPI, 2) +#define PCH_DEV_HDA _PCH_DEV(ESPI, 3) +#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4) +#define PCH_DEV_SPI _PCH_DEV(ESPI, 5) +#define PCH_DEV_GBE _PCH_DEV(ESPI, 6) +#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7) #endif diff --git a/src/soc/intel/icelake/include/soc/pcr_ids.h b/src/soc/intel/icelake/include/soc/pcr_ids.h index a6ad30b617..40d1360ffe 100644 --- a/src/soc/intel/icelake/include/soc/pcr_ids.h +++ b/src/soc/intel/icelake/include/soc/pcr_ids.h @@ -38,7 +38,7 @@ #define PID_SCS 0xc0 #define PID_RTC 0xc3 #define PID_ITSS 0xc4 -#define PID_LPC 0xc7 +#define PID_ESPI 0xc7 #define PID_SERIALIO 0xcb #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783555..cdb39ad591 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -30,10 +30,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 69b5b7a7ad..3c49feeccc 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -13,13 +13,72 @@ * GNU General Public License for more details. */ +#include +#include #include #include +#include +#include #include +static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, + const struct soc_intel_icelake_config *config) +{ + unsigned int i; + const struct device *dev = pcidev_on_root(0, 0); + uint32_t mask = 0; + + /* Set IGD stolen size to 60MB. */ + m_cfg->IgdDvmt50PreAlloc = 0xFE; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; + m_cfg->RMT = config->RMT; + m_cfg->SkipMbpHob = 1; + /* If Audio Codec is enabled, enable FSP UPD */ + if (!dev) + m_cfg->PchHdaEnable = 0; + else + m_cfg->PchHdaEnable = dev->enabled; + + for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { + if (config->PcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->PcieRpEnableMask = mask; + m_cfg->PrmrrSize = config->PrmrrSize; + m_cfg->EnableC6Dram = config->enable_c6dram; + /* Disable BIOS Guard */ + m_cfg->BiosGuard = 0; + /* Disable Cpu Ratio Override temporary. */ + m_cfg->CpuRatio = 0; + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; + m_cfg->PcdDebugInterfaceFlags = + CONFIG(DRIVERS_UART_8250IO) ? 0x02 : 0x10; + + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - /* ToDo: update with UPD override as FSP matures */ + const struct device *dev = pcidev_on_root(0, 0); + assert(dev != NULL); + const struct soc_intel_icelake_config *config = dev->chip_info; + FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + + soc_memory_init_params(m_cfg, config); + + /* Enable SMBus controller based on config */ + m_cfg->SmbusEnable = config->SmbusEnable; + /* Set debug probe type */ + m_cfg->PlatformDebugConsent = config->DebugConsent; + + /* Vt-D config */ + m_cfg->VtdDisable = 0; + + mainboard_memory_init_params(mupd); } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 179d99cff6..a09641cf44 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -86,6 +86,8 @@ static void save_dimm_info(void) if (src_dimm->Status != DIMM_PRESENT) continue; + u8 memProfNum = memory_info_hob->MemoryProfile; + /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -97,7 +99,9 @@ static void save_dimm_info(void) (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c index 5c00b63720..5fb2480604 100644 --- a/src/soc/intel/icelake/smihandler.c +++ b/src/soc/intel/icelake/smihandler.c @@ -86,7 +86,7 @@ void smihandler_soc_at_finalize(void) config = dev->chip_info; - if (config->HeciEnabled == 0) + if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) pch_disable_heci(); } diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index a23d78abd9..b5aa41292a 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -129,97 +129,93 @@ Device (XHCI) Method (_PS0, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + /* Disable d3hot and SS link trunk clock gating */ + Store(Zero, ^D3HE) + Store(Zero, ^STGE) - /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + } + + /* Disable USB2 PHY SUS Well Power Gating */ + Store (Zero, ^UPSW) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC disable power gating */ + Store (1, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } } - Decrement (Local0) - Sleep (10) } } } Method (_PS3, 0, Serialized) { - If (LEqual (^DVID, 0xFFFF)) { - Return - } - If (LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - Return - } + If (!LEqual (^DVID, 0xFFFF)) { + If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { - /* Clear PME Status */ - Store (1, ^PMES) + /* Clear PME Status */ + Store (1, ^PMES) - /* Enable PME */ - Store (1, ^PMEE) + /* Enable PME */ + Store (1, ^PMEE) - /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - } - - /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) - - /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) - - /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) - - /* - * Apply USB2 PHPY Power Gating workaround if needed. - * This code assumes XDCI is disabled, if it is enabled - * then this must also check if it is in D3 state too. - */ - If (^^PMC.UWAB) { - /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) - - /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) - While (^^PMC.PMFS) { - If (LNot (Local0)) { - Break + /* If device is in D3, set back to D0 */ + If (LEqual (^D0D3, 3)) { + Store (Zero, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + } + + /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ + Store (3, ^UPSW) + + /* Enable d3hot and SS link trunk clock gating */ + Store(One, ^D3HE) + Store(One, ^STGE) + + /* Now put device in D3 */ + Store (3, Local0) + Store (Local0, ^D0D3) + Store (^D0D3, Local0) + + /* + * Apply USB2 PHPY Power Gating workaround if needed. + * This code assumes XDCI is disabled, if it is enabled + * then this must also check if it is in D3 state too. + */ + If (^^PMC.UWAB) { + /* Write to MTPMC to have PMC enable power gating */ + Store (3, ^^PMC.MPMC) + + /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ + Store (10, Local0) + While (^^PMC.PMFS) { + If (LNot (Local0)) { + Break + } + Decrement (Local0) + Sleep (10) + } } - Decrement (Local0) - Sleep (10) } } } diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index 1e81809b4f..6733f912dc 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -53,6 +53,9 @@ static struct { { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, + { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, { PCI_DEVICE_ID_INTEL_KBL_ID_U, "Kabylake-U" }, { PCI_DEVICE_ID_INTEL_KBL_U_R, "Kabylake-R ULT"}, { PCI_DEVICE_ID_INTEL_KBL_ID_Y, "Kabylake-Y" }, @@ -77,6 +80,7 @@ static struct { { PCI_DEVICE_ID_INTEL_SPT_H_Q170, "Skylake PCH-H Q170" }, { PCI_DEVICE_ID_INTEL_SPT_H_Q150, "Skylake PCH-H Q150" }, { PCI_DEVICE_ID_INTEL_SPT_H_B150, "Skylake PCH-H B150" }, + { PCI_DEVICE_ID_INTEL_SPT_H_CM236, "Skylake PCH-H CM236" }, { PCI_DEVICE_ID_INTEL_SPT_H_C236, "Skylake PCH-H C236" }, { PCI_DEVICE_ID_INTEL_SPT_H_QM170, "Skylake PCH-H QM170" }, { PCI_DEVICE_ID_INTEL_SPT_H_HM175, "Skylake PCH-H HM175" }, diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a537165dd9..9c8e2bfaa9 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -48,6 +48,18 @@ struct soc_intel_skylake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* IGD panel configuration */ + unsigned int gpu_pp_up_delay_ms; + unsigned int gpu_pp_down_delay_ms; + unsigned int gpu_pp_cycle_delay_ms; + unsigned int gpu_pp_backlight_on_delay_ms; + unsigned int gpu_pp_backlight_off_delay_ms; + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity; + /* * Interrupt Routing configuration * If bit7 is 1, the interrupt is disabled. diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index f563c11302..7efc65a591 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -16,9 +16,11 @@ #include #include +#include #include #include #include +#include #include #include #include @@ -32,10 +34,72 @@ uintptr_t fsp_soc_get_igd_bar(void) return graphics_get_memory_base(); } +static void graphics_setup_panel(struct device *dev) +{ + struct soc_intel_skylake_config *conf = dev->chip_info; + struct resource *mmio_res; + uint8_t *base; + u32 reg32; + + if (!conf) + return; + + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!mmio_res || !mmio_res->base) + return; + base = (void *)(uintptr_t)mmio_res->base; + + reg32 = conf->gpu_pp_up_delay_ms * 10 << 16; + reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10; + write32(base + PCH_PP_ON_DELAYS, reg32); + + reg32 = conf->gpu_pp_down_delay_ms * 10 << 16; + reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10; + write32(base + PCH_PP_OFF_DELAYS, reg32); + + reg32 = read32(base + PCH_PP_DIVISOR); + reg32 &= ~0x1f; + reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f; + write32(base + PCH_PP_DIVISOR, reg32); + + /* So far all devices seem to use the PCH PWM function. + The CPU PWM registers are all zero after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* Reference clock is 24MHz. We can choose either a 16 + or a 128 step increment. Use 16 if we would have less + than 100 steps otherwise. */ + const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken1; + + south_chicken1 = read32(base + SOUTH_CHICKEN1); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken1 &= ~1; + } else { + pwm_increment = 128; + south_chicken1 |= 1; + } + write32(base + SOUTH_CHICKEN1, south_chicken1); + + pwm_period = 24 * 1000 * 1000 / pwm_increment + / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + write32(base + BLC_PWM_PCH_CTL2, + pwm_period << 16 | pwm_period / 2); + + write32(base + BLC_PWM_PCH_CTL1, + !!conf->gpu_pch_backlight_polarity << 29 | + BLM_PCH_PWM_ENABLE); + } +} + void graphics_soc_init(struct device *dev) { u32 ddi_buf_ctl; + graphics_setup_panel(dev); + /* * Enable DDI-A (eDP) 4-lane operation if the link is not up yet. * This will allow the kernel to use 4-lane eDP links properly diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 04c369beb8..2819c6f260 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -114,6 +114,7 @@ static void save_dimm_info(void) ddr_type = MEMORY_TYPE_UNKNOWN; break; } + u8 memProfNum = memory_info_hob->MemoryProfile; /* Populate the DIMM information */ dimm_info_fill(dest_dimm, @@ -126,7 +127,9 @@ static void save_dimm_info(void) (const char *)src_dimm->ModulePartNum, sizeof(src_dimm->ModulePartNum), src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, - memory_info_hob->DataWidth); + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport); index++; } } diff --git a/src/soc/qualcomm/qcs405/Kconfig b/src/soc/qualcomm/qcs405/Kconfig index aa867c2f25..e24993a2f0 100644 --- a/src/soc/qualcomm/qcs405/Kconfig +++ b/src/soc/qualcomm/qcs405/Kconfig @@ -19,6 +19,7 @@ config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_RETURN_FROM_VERSTAGE select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_MIGRATE_WORKING_DATA config QCS405_BLSP_SPI bool diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index c64e5bcf58..0ebfcaef78 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -8,6 +8,9 @@ bootblock-y += spi.c bootblock-y += mmu.c bootblock-y += gpio.c bootblock-y += clock.c +bootblock-y += i2c.c +bootblock-y += qup.c +bootblock-y += blsp.c bootblock-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ @@ -15,6 +18,9 @@ verstage-y += timer.c verstage-y += spi.c verstage-y += gpio.c verstage-y += clock.c +verstage-y += i2c.c +verstage-y += qup.c +verstage-y += blsp.c verstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ @@ -25,6 +31,9 @@ romstage-y += gpio.c romstage-y += clock.c romstage-y += usb.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += i2c.c +romstage-y += qup.c +romstage-y += blsp.c ################################################################################ ramstage-y += soc.c @@ -33,6 +42,9 @@ ramstage-y += spi.c ramstage-y += cbmem.c ramstage-y += gpio.c ramstage-y += clock.c +ramstage-y += i2c.c +ramstage-y += qup.c +ramstage-y += blsp.c ramstage-y += usb.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c new file mode 100644 index 0000000000..f185ea388a --- /dev/null +++ b/src/soc/qualcomm/qcs405/blsp.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2016, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +blsp_return_t blsp_i2c_init(blsp_qup_id_t id) +{ + void *base; + + switch (id) { + case BLSP_QUP_ID_1: + gpio_configure + (GPIO(24), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT); + gpio_configure + (GPIO(25), 2, GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT); + break; + default: + return BLSP_ID_ERROR; + } + + clock_configure_i2c(19200000); + clock_enable_i2c(); + + base = blsp_qup_base(id); + + if (!base) + return BLSP_ID_ERROR; + + /* Configure Mini core to I2C core */ + clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C); + + return BLSP_SUCCESS; +} diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 302652ba71..56824a430a 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -246,6 +246,14 @@ void clock_configure_spi(int blsp, int qup, uint32_t hz) clock_configure(spi_clk, spi_cfg, hz, ARRAY_SIZE(spi_cfg)); } +void clock_configure_i2c(uint32_t hz) +{ + struct qcs405_clock *i2c_clk = + (struct qcs405_clock *)&gcc->blsp1_qup1_i2c_clk; + + clock_configure(i2c_clk, i2c_cfg, hz, ARRAY_SIZE(i2c_cfg)); +} + void clock_enable_uart(void) { clock_enable(&gcc->blsp1_uart2_apps_cbcr); @@ -309,6 +317,16 @@ void clock_disable_spi(int blsp, int qup) } +void clock_enable_i2c(void) +{ + clock_enable(&gcc->blsp1_qup1_i2c_apps_cbcr); +} + +void clock_disable_i2c(void) +{ + clock_disable(&gcc->blsp1_qup1_i2c_apps_cbcr); +} + void clock_init(void) { clock_configure_gpll0(); diff --git a/src/soc/qualcomm/qcs405/i2c.c b/src/soc/qualcomm/qcs405/i2c.c new file mode 100644 index 0000000000..94f8e0d4bb --- /dev/null +++ b/src/soc/qualcomm/qcs405/i2c.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static qup_config_t blsp1_qup0_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup1_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup2_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static qup_config_t blsp1_qup3_config = { + QUP_MINICORE_I2C_MASTER, + 400000, + 19200000, + QUP_MODE_BLOCK, + 0 +}; + +static int i2c_read(uint32_t gsbi_id, uint8_t slave, + uint8_t *data, int data_len) +{ + qup_data_t obj; + qup_return_t qup_ret = 0; + + memset(&obj, 0, sizeof(obj)); + obj.protocol = QUP_MINICORE_I2C_MASTER; + obj.p.iic.addr = slave; + obj.p.iic.data_len = data_len; + obj.p.iic.data = data; + qup_ret = qup_recv_data(gsbi_id, &obj); + + if (qup_ret != QUP_SUCCESS) + return 1; + else + return 0; +} + +static int i2c_write(uint32_t gsbi_id, uint8_t slave, + uint8_t *data, int data_len, uint8_t stop_seq) +{ + qup_data_t obj; + qup_return_t qup_ret = 0; + + memset(&obj, 0, sizeof(obj)); + obj.protocol = QUP_MINICORE_I2C_MASTER; + obj.p.iic.addr = slave; + obj.p.iic.data_len = data_len; + obj.p.iic.data = data; + qup_ret = qup_send_data(gsbi_id, &obj, stop_seq); + + if (qup_ret != QUP_SUCCESS) + return 1; + else + return 0; +} + +static int i2c_init(blsp_qup_id_t id) +{ + qup_config_t *qup_config; + + switch (id) { + case BLSP_QUP_ID_0: + qup_config = &blsp1_qup0_config; + break; + case BLSP_QUP_ID_1: + qup_config = &blsp1_qup1_config; + break; + case BLSP_QUP_ID_2: + qup_config = &blsp1_qup2_config; + break; + case BLSP_QUP_ID_3: + qup_config = &blsp1_qup3_config; + break; + default: + printk(BIOS_ERR, "QUP configuration not defined for BLSP%d.\n", + id); + return 1; + } + + if (qup_config->initialized) + return 0; + + if (blsp_i2c_init(id)) { + printk(BIOS_ERR, "failed to initialize blsp\n"); + return 1; + } + + if (qup_init(id, qup_config)) { + printk(BIOS_ERR, "failed to initialize qup\n"); + return 1; + } + + if (qup_reset_i2c_master_status(id)) { + printk(BIOS_ERR, "failed to reset i2c master status\n"); + return 1; + } + + qup_config->initialized = 1; + return 0; +} + +int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, + int seg_count) +{ + struct i2c_msg *seg = segments; + int ret = 0; + + if (i2c_init(bus)) + return 1; + + while (!ret && seg_count--) { + if (seg->flags & I2C_M_RD) + ret = i2c_read(bus, seg->slave, seg->buf, seg->len); + else + ret = i2c_write(bus, seg->slave, seg->buf, seg->len, + (seg_count ? 0 : 1)); + seg++; + } + + if (ret) { + qup_set_state(bus, QUP_STATE_RESET); + return 1; + } + + return 0; +} diff --git a/src/soc/qualcomm/qcs405/include/soc/clock.h b/src/soc/qualcomm/qcs405/include/soc/clock.h index 8638128b15..55c1aaf7a8 100644 --- a/src/soc/qualcomm/qcs405/include/soc/clock.h +++ b/src/soc/qualcomm/qcs405/include/soc/clock.h @@ -69,7 +69,9 @@ struct qcs405_gcc { u8 _res1[0x2000 - 0x1014]; u32 blsp1_qup1_bcr; u32 blsp1_qup1_spi_apps_cbcr; - u8 _res2[0x2024 - 0x2008]; + u32 blsp1_qup1_i2c_apps_cbcr; + struct qcs405_clock blsp1_qup1_i2c_clk; + u8 _res2[0x2024 - 0x2020]; struct qcs405_clock blsp1_qup1_spi_clk; u8 _res3[0x3008-0x2038]; u32 blsp1_qup2_bcr; @@ -179,10 +181,13 @@ void clock_reset_aop(void); int clock_configure_qspi(uint32_t hz); int clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_uart(uint32_t hz); +void clock_configure_i2c(uint32_t hz); void clock_configure_spi(int blsp, int qup, uint32_t hz); void clock_enable_uart(void); void clock_disable_uart(void); void clock_enable_spi(int blsp, int qup); void clock_disable_spi(int blsp, int qup); +void clock_enable_i2c(void); +void clock_disable_i2c(void); #endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ diff --git a/src/soc/qualcomm/qcs405/qup.c b/src/soc/qualcomm/qcs405/qup.c new file mode 100644 index 0000000000..cff5241480 --- /dev/null +++ b/src/soc/qualcomm/qcs405/qup.c @@ -0,0 +1,609 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials provided + * with the distribution. + * * Neither the name of The Linux Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TIMEOUT_CNT 100 + +#define QUP_ADDR(id, reg) (blsp_qup_base(id) + (reg)) + +#define QUP_DEBUG 0 + +#define QUPDBG BIOS_ERR, "\t-> " + +#if QUP_DEBUG +#define qup_write32(a, v) do { \ + write32(a, v); \ + printk(QUPDBG "%s(%d): write32(0x%p, 0x%x)\n", \ + __func__, __LINE__, a, v); \ +} while (0) +#else +#define qup_write32 write32 +#endif + +struct i2c_clk_div_fld { + u32 clk_freq_out; + u8 fs_div; + u8 ht_div; +}; + +static struct i2c_clk_div_fld i2c_clk_div_map[] = { + {100000, 124, 62}, + {400000, 28, 14}, + {1000000, 8, 5}, +}; + +static void i2c_set_mstr_clk_ctl(unsigned int id, unsigned int hz) +{ + int i; + struct i2c_clk_div_fld *itr = i2c_clk_div_map; + u8 fs_div = 0; + u8 ht_div = 0; + u32 mstr_clk_ctl; + + for (i = 0; i < ARRAY_SIZE(i2c_clk_div_map); ++i, ++itr) { + if (hz == itr->clk_freq_out) { + if (!fs_div) + fs_div = itr->fs_div; + if (!ht_div) + ht_div = itr->ht_div; + break; + } + } + + /* format values in clk-ctl cache */ + mstr_clk_ctl = ((ht_div & 0xff) << 16) | (fs_div & 0xff); + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), mstr_clk_ctl); +} + + +static qup_return_t qup_i2c_master_status(blsp_qup_id_t id) +{ + uint32_t reg_val = read32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS)); + + if (read32(QUP_ADDR(id, QUP_ERROR_FLAGS))) + return QUP_ERR_XFER_FAIL; + +#if QUP_DEBUG + printk(QUPDBG "%s: 0x%x\n", __func__, reg_val); +#endif + + if (reg_val & QUP_I2C_INVALID_READ_ADDR) + return QUP_ERR_I2C_INVALID_SLAVE_ADDR; + if (reg_val & QUP_I2C_FAILED_MASK) + return QUP_ERR_I2C_FAILED; + if (reg_val & QUP_I2C_ARB_LOST) + return QUP_ERR_I2C_ARB_LOST; + if (reg_val & QUP_I2C_BUS_ERROR) + return QUP_ERR_I2C_BUS_ERROR; + if (reg_val & QUP_I2C_INVALID_WRITE) + return QUP_ERR_I2C_INVALID_WRITE; + if (reg_val & QUP_I2C_PACKET_NACK) + return QUP_ERR_I2C_NACK; + if (reg_val & QUP_I2C_INVALID_TAG) + return QUP_ERR_I2C_INVALID_TAG; + + return QUP_SUCCESS; +} + +static int check_bit_state(uint32_t *reg, int wait_for) +{ + unsigned int count = TIMEOUT_CNT; + + while ((read32(reg) & (QUP_STATE_VALID_MASK | QUP_STATE_MASK)) != + (QUP_STATE_VALID | wait_for)) { + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +/* + * Check whether GSBIn_QUP State is valid + */ +static qup_return_t qup_wait_for_state(blsp_qup_id_t id, unsigned int wait_for) +{ + return check_bit_state(QUP_ADDR(id, QUP_STATE), wait_for); +} + +qup_return_t qup_reset_i2c_master_status(blsp_qup_id_t id) +{ + /* + * The I2C_STATUS is a status register. + * Writing any value clears the status bits. + */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_STATUS), 0); + return QUP_SUCCESS; +} + +static qup_return_t qup_reset_master_status(blsp_qup_id_t id) +{ + qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS), 0x3C); + qup_write32(QUP_ADDR(id, QUP_ERROR_FLAGS_EN), 0x3C); + qup_reset_i2c_master_status(id); + return QUP_SUCCESS; +} + +static qup_return_t qup_fifo_wait_for(blsp_qup_id_t id, uint32_t status) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned int count = TIMEOUT_CNT; + + while (!(read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status)) { + ret = qup_i2c_master_status(id); + if (ret) + return ret; + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +static qup_return_t qup_fifo_wait_while(blsp_qup_id_t id, uint32_t status) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned int count = TIMEOUT_CNT; + + while (read32(QUP_ADDR(id, QUP_OPERATIONAL)) & status) { + ret = qup_i2c_master_status(id); + if (ret) + return ret; + if (count == 0) + return QUP_ERR_TIMEOUT; + count--; + } + + return QUP_SUCCESS; +} + +static inline uint32_t qup_i2c_create_output_tag(int stop, u8 data) +{ + uint32_t tag; + + if (stop) + tag = QUP_I2C_STOP_SEQ | QUP_I2C_DATA(data); + else + tag = QUP_I2C_DATA_SEQ | QUP_I2C_DATA(data); + + return tag; +} + +static inline qup_return_t qup_i2c_write_fifo_flush(blsp_qup_id_t id) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), OUTPUT_SERVICE_FLAG); + + mdelay(4); /* TPM seems to need this */ + + ret = qup_fifo_wait_while(id, OUTPUT_FIFO_NOT_EMPTY); + if (ret) + return ret; + + ret = qup_i2c_master_status(id); + + if (ret) + printk(BIOS_DEBUG, "%s: error\n", __func__); + + return ret; +} + +static qup_return_t qup_i2c_write_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t addr = p_tx_obj->p.iic.addr; + uint8_t *data_ptr = p_tx_obj->p.iic.data; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; + uint32_t tag, *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); + + qup_reset_master_status(id); + + qup_write32(QUP_ADDR(id, QUP_MX_OUTPUT_COUNT), data_len + 1); + + qup_set_state(id, QUP_STATE_RUN); + + /* + * Since UNPACK enable is set in io mode register, populate 2 tags + * for each fifo register. + * + * Create the first tag as follows, with the start tag and first byte + * of the data to be written + * +--------+--------+--------+--------+ + * | STOP / | data | START | ADDR | + * |DATA tag| byte | tag | << 1 | + * +--------+--------+--------+--------+ + * rest will be created in the following while loop. + */ + tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, + data_ptr[idx]); + tag = ((tag << 16) & 0xffff0000) | + (QUP_I2C_START_SEQ | QUP_I2C_ADDR(addr)); + data_len--; + idx++; + + qup_write32(fifo, tag); + + while (data_len) { + + tag = qup_i2c_create_output_tag(data_len == 1 && stop_seq, + data_ptr[idx]); + data_len--; + idx++; + + if (data_len) { + tag |= qup_i2c_create_output_tag( + data_len == 1 && stop_seq, + data_ptr[idx]) << 16; + data_len--; + idx++; + } + + qup_write32(fifo, tag); + + ret = qup_i2c_write_fifo_flush(id); + + if (ret) { + printk(QUPDBG "%s: error\n", __func__); + return ret; + } + } + + ret = qup_i2c_write_fifo_flush(id); + + qup_set_state(id, QUP_STATE_RESET); + + return ret; +} + +static qup_return_t qup_i2c_write(blsp_qup_id_t id, uint8_t mode, + qup_data_t *p_tx_obj, uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + switch (mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + ret = qup_i2c_write_fifo(id, p_tx_obj, stop_seq); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + + if (ret) { + qup_set_state(id, QUP_STATE_RESET); + printk(QUPDBG "%s() failed (%d)\n", __func__, ret); + } + + return ret; +} + +static int qup_i2c_parse_tag(uint32_t data, uint8_t *data_ptr, uint32_t len) +{ + int i, idx = 0; + int max = (len > 2) ? 2 : len; + + for (i = 0; i < max; i++) { + switch (QUP_I2C_MI_TAG(data)) { + case QUP_I2C_MIDATA_SEQ: + data_ptr[idx] = QUP_I2C_DATA(data); + idx++; + break; + case QUP_I2C_MISTOP_SEQ: + data_ptr[idx] = QUP_I2C_DATA(data); + idx++; + return idx; + default: + printk(QUPDBG "%s: Unexpected tag (0x%x)\n", __func__, + QUP_I2C_MI_TAG(data)); + return -1; + } + + data = (data >> 16); + } + + return idx; +} + +static qup_return_t qup_i2c_read_fifo(blsp_qup_id_t id, qup_data_t *p_tx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t addr = p_tx_obj->p.iic.addr; + uint8_t *data_ptr = p_tx_obj->p.iic.data; + unsigned int data_len = p_tx_obj->p.iic.data_len; + unsigned int idx = 0; + uint32_t *fifo = QUP_ADDR(id, QUP_OUTPUT_FIFO); + + qup_reset_master_status(id); + + qup_write32(QUP_ADDR(id, QUP_IO_MODES), + QUP_UNPACK_EN | QUP_PACK_EN | + ((QUP_MODE_BLOCK & QUP_MODE_MASK) << + QUP_OUTPUT_MODE_SHFT) | + ((QUP_MODE_BLOCK & QUP_MODE_MASK) << + QUP_INPUT_MODE_SHFT)); + + qup_write32(QUP_ADDR(id, QUP_MX_INPUT_COUNT), data_len); + + qup_set_state(id, QUP_STATE_RUN); + + qup_write32(fifo, (QUP_I2C_START_SEQ | + (QUP_I2C_ADDR(addr) | QUP_I2C_SLAVE_READ)) | + ((QUP_I2C_RECV_SEQ | data_len) << 16)); + + ret = qup_i2c_write_fifo_flush(id); + if (ret) { + printk(QUPDBG "%s: OUTPUT_FIFO_NOT_EMPTY\n", __func__); + return ret; + } + + ret = qup_fifo_wait_for(id, INPUT_SERVICE_FLAG); + if (ret) { + printk(QUPDBG "%s: INPUT_SERVICE_FLAG\n", __func__); + return ret; + } + + fifo = QUP_ADDR(id, QUP_INPUT_FIFO); + + while (data_len) { + uint32_t data; + int count; + + data = read32(fifo); + mdelay(1); + + count = qup_i2c_parse_tag(data, data_ptr + idx, data_len); + + if (count < 0) { + printk(QUPDBG "%s: Cannot parse tag 0x%x\n", + __func__, data); + qup_set_state(id, QUP_STATE_PAUSE); + + return QUP_ERR_I2C_INVALID_TAG; + } + + idx += count; + data_len -= count; + + qup_write32(QUP_ADDR(id, QUP_OPERATIONAL), INPUT_SERVICE_FLAG); + } + + p_tx_obj->p.iic.data_len = idx; + + qup_write32(QUP_ADDR(id, QUP_MX_READ_COUNT), 0); + + qup_set_state(id, QUP_STATE_RESET); + + return QUP_SUCCESS; +} + +static qup_return_t qup_i2c_read(blsp_qup_id_t id, uint8_t mode, + qup_data_t *p_tx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + qup_set_state(id, QUP_STATE_RESET); + + switch (mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + ret = qup_i2c_read_fifo(id, p_tx_obj); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + + if (ret) { + qup_set_state(id, QUP_STATE_RESET); + printk(QUPDBG "%s() failed (%d)\n", __func__, ret); + } + + return ret; +} + +qup_return_t qup_init(blsp_qup_id_t id, const qup_config_t *config_ptr) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint32_t reg_val; + + /* Reset the QUP core.*/ + qup_write32(QUP_ADDR(id, QUP_SW_RESET), 0x1); + + /* Wait till the reset takes effect */ + ret = qup_wait_for_state(id, QUP_STATE_RESET); + if (ret) + goto bailout; + + /* Reset the config */ + qup_write32(QUP_ADDR(id, QUP_CONFIG), 0); + + /* Program the config register */ + /* Set N value */ + reg_val = 0x0F; + /* Set protocol */ + switch (config_ptr->protocol) { + case QUP_MINICORE_I2C_MASTER: + reg_val |= ((config_ptr->protocol & + QUP_MINI_CORE_PROTO_MASK) << + QUP_MINI_CORE_PROTO_SHFT); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + goto bailout; + } + reg_val |= QUP_APP_CLK_ON_EN | QUP_CORE_CLK_ON_EN; + qup_write32(QUP_ADDR(id, QUP_CONFIG), reg_val); + + /* Choose version 1 tag */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CONFIG), 0); + + /* Reset i2c clk cntl register */ + qup_write32(QUP_ADDR(id, QUP_I2C_MASTER_CLK_CTL), 0); + + /* Set QUP IO Mode */ + switch (config_ptr->mode) { + case QUP_MODE_FIFO: + case QUP_MODE_BLOCK: + reg_val = QUP_UNPACK_EN | QUP_PACK_EN | + ((config_ptr->mode & QUP_MODE_MASK) << + QUP_OUTPUT_MODE_SHFT) | + ((config_ptr->mode & QUP_MODE_MASK) << + QUP_INPUT_MODE_SHFT); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + goto bailout; + } + qup_write32(QUP_ADDR(id, QUP_IO_MODES), reg_val); + + /*Set i2c clk cntl*/ + i2c_set_mstr_clk_ctl(id, 400000); + + qup_set_state(id, QUP_STATE_RESET); +bailout: + if (ret) + printk(QUPDBG "failed to init qup (%d)\n", ret); + + return ret; +} + +qup_return_t qup_set_state(blsp_qup_id_t id, uint32_t state) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + unsigned int curr_state = read32(QUP_ADDR(id, QUP_STATE)); + + if ((state <= QUP_STATE_PAUSE) + && (curr_state & QUP_STATE_VALID_MASK)) { + /* + * For PAUSE_STATE to RESET_STATE transition, + * two writes of 10[binary]) are required for the + * transition to complete. + */ + if (curr_state == QUP_STATE_PAUSE && state == QUP_STATE_RESET) { + qup_write32(QUP_ADDR(id, QUP_STATE), 0x2); + qup_write32(QUP_ADDR(id, QUP_STATE), 0x2); + } else { + qup_write32(QUP_ADDR(id, QUP_STATE), state); + } + ret = qup_wait_for_state(id, state); + } + + return ret; +} + +static qup_return_t qup_i2c_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >> + QUP_OUTPUT_MODE_SHFT) & QUP_MODE_MASK; + + ret = qup_i2c_write(id, mode, p_tx_obj, stop_seq); + if (QUP_DEBUG) { + int i; + + printk(BIOS_DEBUG, "i2c tx bus %d device %2.2x:", + id, p_tx_obj->p.iic.addr); + for (i = 0; i < p_tx_obj->p.iic.data_len; i++) + printk(BIOS_DEBUG, " %2.2x", p_tx_obj->p.iic.data[i]); + printk(BIOS_DEBUG, "\n"); + } + + return ret; +} + +qup_return_t qup_send_data(blsp_qup_id_t id, qup_data_t *p_tx_obj, + uint8_t stop_seq) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + if (p_tx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >> + QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { + switch (p_tx_obj->protocol) { + case QUP_MINICORE_I2C_MASTER: + ret = qup_i2c_send_data(id, p_tx_obj, stop_seq); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + } + + return ret; +} + +static qup_return_t qup_i2c_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + uint8_t mode = (read32(QUP_ADDR(id, QUP_IO_MODES)) >> + QUP_INPUT_MODE_SHFT) & QUP_MODE_MASK; + + ret = qup_i2c_read(id, mode, p_rx_obj); + if (QUP_DEBUG) { + int i; + + printk(BIOS_DEBUG, "i2c rxed on bus %d device %2.2x:", + id, p_rx_obj->p.iic.addr); + for (i = 0; i < p_rx_obj->p.iic.data_len; i++) + printk(BIOS_DEBUG, " %2.2x", p_rx_obj->p.iic.data[i]); + printk(BIOS_DEBUG, "\n"); + } + + return ret; +} + +qup_return_t qup_recv_data(blsp_qup_id_t id, qup_data_t *p_rx_obj) +{ + qup_return_t ret = QUP_ERR_UNDEFINED; + + if (p_rx_obj->protocol == ((read32(QUP_ADDR(id, QUP_CONFIG)) >> + QUP_MINI_CORE_PROTO_SHFT) & QUP_MINI_CORE_PROTO_MASK)) { + switch (p_rx_obj->protocol) { + case QUP_MINICORE_I2C_MASTER: + ret = qup_i2c_recv_data(id, p_rx_obj); + break; + default: + ret = QUP_ERR_UNSUPPORTED; + } + } + + return ret; +} diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h index ac9fd50f1b..3f83421e72 100644 --- a/src/soc/qualcomm/sdm845/include/soc/qspi.h +++ b/src/soc/qualcomm/sdm845/include/soc/qspi.h @@ -116,4 +116,6 @@ int sdm845_setup_bus(const struct spi_slave *slave); void sdm845_release_bus(const struct spi_slave *slave); int sdm845_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, void *din, size_t in_bytes); +int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); #endif /* __SOC_QUALCOMM_SDM845_QSPI_H__ */ diff --git a/src/soc/qualcomm/sdm845/qspi.c b/src/soc/qualcomm/sdm845/qspi.c index b9a5194a10..cced567a87 100644 --- a/src/soc/qualcomm/sdm845/qspi.c +++ b/src/soc/qualcomm/sdm845/qspi.c @@ -277,11 +277,9 @@ void sdm845_release_bus(const struct spi_slave *slave) cs_change(CS_DEASSERT); } -int sdm845_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) { - enum qspi_mode mode = SDR_1BIT; - if ((out_bytes && !dout) || (in_bytes && !din) || (in_bytes && out_bytes)) { return -1; @@ -294,3 +292,15 @@ int sdm845_xfer(const struct spi_slave *slave, const void *dout, return 0; } + +int sdm845_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c index e276e1d214..27aafa7b72 100644 --- a/src/soc/qualcomm/sdm845/spi.c +++ b/src/soc/qualcomm/sdm845/spi.c @@ -21,6 +21,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = sdm845_claim_bus, .release_bus = sdm845_release_bus, .xfer = sdm845_xfer, + .xfer_dual = sdm845_xfer_dual, .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6b7ce68a1a..66316828ba 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -306,7 +306,7 @@ static void sm_init(struct device *dev) } byte = pci_read_config8(dev, 0xAE); if (CONFIG(ENABLE_APIC_EXT_ID)) - byte |= 1 << 4; + byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ pci_write_config8(dev, 0xAE, byte); diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index db27ef7097..8909f50bc1 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -18,6 +18,12 @@ #include +enum sata_mode { + SATA_MODE_AHCI = 0, + SATA_MODE_IDE_LEGACY_COMBINED, + SATA_MODE_IDE_PLAIN, +}; + struct southbridge_intel_i82801gx_config { /** * Interrupt Routing configuration @@ -65,7 +71,7 @@ struct southbridge_intel_i82801gx_config { uint32_t ide_legacy_combined; uint32_t ide_enable_primary; uint32_t ide_enable_secondary; - uint32_t sata_ahci; + enum sata_mode sata_mode; uint32_t sata_ports_implemented; /* Enable linear PCIe Root Port function numbers starting at zero */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index e44fcf5123..76420b4e17 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -82,6 +82,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define FDVCT 0xe4 #define PCIE_4_PORTS_MAX (1 << 7) +#define AHCI_UNSUPPORTED (1 << 3) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index b657513dcf..24dbf7cf27 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -51,18 +51,42 @@ static u8 get_ich7_sata_ports(void) void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = dev->chip_info; + struct southbridge_intel_i82801gx_config *config = dev->chip_info; + + if (config->sata_mode == SATA_MODE_AHCI) { + /* Check if the southbridge supports AHCI */ + struct device *lpc_dev = pcidev_on_root(31, 0); + if (!lpc_dev) { + /* According to the PCI spec function 0 on a bus:device + needs to be active for other functions to be enabled. + Since SATA is on the same bus:device as the LPC + bridge, it makes little sense to continue. */ + die("Couldn't find the LPC device!\n"); + } + + const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT) + & AHCI_UNSUPPORTED); + + if (!ahci_supported) { + /* Fallback to IDE PLAIN for sata for the rest of the + initialization */ + config->sata_mode = SATA_MODE_IDE_PLAIN; + printk(BIOS_DEBUG, + "AHCI not supported, falling back to plain mode.\n"); + } - if (config->sata_ahci) { - /* Set map to ahci */ - pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); - } else { - /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, - pci_read_config8(dev, SATA_MAP) & ~0xc3); } + if (config->sata_mode == SATA_MODE_AHCI) { + /* Set map to ahci */ + pci_write_config8(dev, SATA_MAP, + (pci_read_config8(dev, SATA_MAP) + & ~0xc3) | 0x40); + } else { + /* Set map to ide */ + pci_write_config8(dev, SATA_MAP, + pci_read_config8(dev, SATA_MAP) & ~0xc3); + } /* At this point, the new pci id will appear on the bus */ } @@ -89,7 +113,8 @@ static void sata_init(struct device *dev) /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { + switch (config->sata_mode) { + case SATA_MODE_IDE_LEGACY_COMBINED: printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); /* No AHCI: clear AHCI base */ pci_write_config32(dev, 0x24, 0x00000000); @@ -120,7 +145,8 @@ static void sata_init(struct device *dev) /* Restrict ports - 0 and 2 only available */ ports &= 0x5; - } else if (config->sata_ahci) { + break; + case SATA_MODE_AHCI: printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); /* Allow both Legacy and Native mode */ pci_write_config8(dev, 0x09, 0x8f); @@ -131,7 +157,9 @@ static void sata_init(struct device *dev) ahci_bar = (u32 *)(pci_read_config32(dev, 0x27) & ~0x3ff); ahci_bar[3] = config->sata_ports_implemented; - } else { + break; + default: + case SATA_MODE_IDE_PLAIN: printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); /* Set Sata Controller Mode. No Mapping(?) */ pci_write_config8(dev, SATA_MAP, 0x00); @@ -168,6 +196,7 @@ static void sata_init(struct device *dev) /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); + break; } /* Set port control */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 85c89799e0..00eb413d1e 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -53,7 +53,7 @@ config DRAM_RESET_GATE_GPIO config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/intel/bd82x6x/bootblock.c" + default "southbridge/intel/ibexpeak/bootblock.c" config SERIRQ_CONTINUOUS_MODE bool diff --git a/src/southbridge/intel/ibexpeak/bootblock.c b/src/southbridge/intel/ibexpeak/bootblock.c new file mode 100644 index 0000000000..0086fe3281 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/bootblock.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "pch.h" + +/* + * Enable Prefetching and Caching. + */ +static void enable_spi_prefetch(void) +{ + u8 reg8; + pci_devfn_t dev = PCH_LPC_DEV; + + reg8 = pci_read_config8(dev, BIOS_CNTL); + reg8 &= ~(3 << 2); + reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ + pci_write_config8(dev, BIOS_CNTL, reg8); +} + +static void enable_port80_on_lpc(void) +{ + pci_devfn_t dev = PCH_LPC_DEV; + + /* Enable port 80 POST on LPC */ + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); +#if 0 + RCBA32(GCS) &= (~0x04); +#else + volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); + u32 reg32 = *gcs; + reg32 = reg32 & ~0x04; + *gcs = reg32; +#endif +} + +static void set_spi_speed(void) +{ + u32 fdod; + u8 ssfc; + + /* Observe SPI Descriptor Component Section 0 */ + RCBA32(0x38b0) = 0x1000; + + /* Extract the Write/Erase SPI Frequency from descriptor */ + fdod = RCBA32(0x38b4); + fdod >>= 24; + fdod &= 7; + + /* Set Software Sequence frequency to match */ + ssfc = RCBA8(0x3893); + ssfc &= ~7; + ssfc |= fdod; + RCBA8(0x3893) = ssfc; +} + +static void bootblock_southbridge_init(void) +{ + enable_spi_prefetch(); + enable_port80_on_lpc(); + set_spi_speed(); + + /* Enable upper 128bytes of CMOS */ + RCBA32(RC) = (1 << 2); +} diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index 85dbe70639..cb31f7e131 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -37,19 +37,19 @@ are permitted provided that the following conditions are met: #pragma pack(1) - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - + +#include + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + /** Fsp M Configuration **/ @@ -1421,799 +1421,830 @@ typedef struct { **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x044C - PcdSerialIoUartNumber - Select SerialIo Uart Controller for debug. +/** Offset 0x044C - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ - UINT8 PcdSerialIoUartNumber; + UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x044D - ReservedPchPreMem +/** Offset 0x044D - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x044E +**/ + UINT8 UnusedUpdSpace7[2]; + +/** Offset 0x0450 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0454 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0455 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0456 - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0457 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS **/ UINT8 ReservedPchPreMem[16]; -/** Offset 0x045D - ISA Serial Base selection +/** Offset 0x0467 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x045E - GT PLL voltage offset +/** Offset 0x0468 - GT PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 GtPllVoltageOffset; -/** Offset 0x045F - Ring PLL voltage offset +/** Offset 0x0469 - Ring PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 RingPllVoltageOffset; -/** Offset 0x0460 - System Agent PLL voltage offset +/** Offset 0x046A - System Agent PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 SaPllVoltageOffset; -/** Offset 0x0461 - Memory Controller PLL voltage offset +/** Offset 0x046B - Memory Controller PLL voltage offset Core PLL voltage offset. 0: No offset. Range 0-63 **/ UINT8 McPllVoltageOffset; -/** Offset 0x0462 - MRC Safe Config +/** Offset 0x046C - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x0463 - PcdSerialDebugBaudRate +/** Offset 0x046D - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. 3:9600, 4:19200, 6:56700, 7:115200 **/ UINT8 PcdSerialDebugBaudRate; -/** Offset 0x0464 - HobBufferSize +/** Offset 0x046E - HobBufferSize Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB total HOB size). 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value **/ UINT8 HobBufferSize; -/** Offset 0x0465 - Early Command Training +/** Offset 0x046F - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x0466 - SenseAmp Offset Training +/** Offset 0x0470 - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS **/ UINT8 SOT; -/** Offset 0x0467 - Early ReadMPR Timing Centering 2D +/** Offset 0x0471 - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $EN_DIS **/ UINT8 ERDMPRTC2D; -/** Offset 0x0468 - Read MPR Training +/** Offset 0x0472 - Read MPR Training Enables/Disable Read MPR Training $EN_DIS **/ UINT8 RDMPRT; -/** Offset 0x0469 - Receive Enable Training +/** Offset 0x0473 - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS **/ UINT8 RCVET; -/** Offset 0x046A - Jedec Write Leveling +/** Offset 0x0474 - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS **/ UINT8 JWRL; -/** Offset 0x046B - Early Write Time Centering 2D +/** Offset 0x0475 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS **/ UINT8 EWRTC2D; -/** Offset 0x046C - Early Read Time Centering 2D +/** Offset 0x0476 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS **/ UINT8 ERDTC2D; -/** Offset 0x046D - Write Timing Centering 1D +/** Offset 0x0477 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS **/ UINT8 WRTC1D; -/** Offset 0x046E - Write Voltage Centering 1D +/** Offset 0x0478 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS **/ UINT8 WRVC1D; -/** Offset 0x046F - Read Timing Centering 1D +/** Offset 0x0479 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS **/ UINT8 RDTC1D; -/** Offset 0x0470 - Dimm ODT Training +/** Offset 0x047A - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS **/ UINT8 DIMMODTT; -/** Offset 0x0471 - DIMM RON Training +/** Offset 0x047B - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS **/ UINT8 DIMMRONT; -/** Offset 0x0472 - Write Drive Strength/Equalization 2D +/** Offset 0x047C - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_DIS **/ UINT8 WRDSEQT; -/** Offset 0x0473 - Write Slew Rate Training +/** Offset 0x047D - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS **/ UINT8 WRSRT; -/** Offset 0x0474 - Read ODT Training +/** Offset 0x047E - Read ODT Training Enables/Disable Read ODT Training $EN_DIS **/ UINT8 RDODTT; -/** Offset 0x0475 - Read Equalization Training +/** Offset 0x047F - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS **/ UINT8 RDEQT; -/** Offset 0x0476 - Read Amplifier Training +/** Offset 0x0480 - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS **/ UINT8 RDAPT; -/** Offset 0x0477 - Write Timing Centering 2D +/** Offset 0x0481 - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS **/ UINT8 WRTC2D; -/** Offset 0x0478 - Read Timing Centering 2D +/** Offset 0x0482 - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS **/ UINT8 RDTC2D; -/** Offset 0x0479 - Write Voltage Centering 2D +/** Offset 0x0483 - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS **/ UINT8 WRVC2D; -/** Offset 0x047A - Read Voltage Centering 2D +/** Offset 0x0484 - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS **/ UINT8 RDVC2D; -/** Offset 0x047B - Command Voltage Centering +/** Offset 0x0485 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS **/ UINT8 CMDVC; -/** Offset 0x047C - Late Command Training +/** Offset 0x0486 - Late Command Training Enables/Disable Late Command Training $EN_DIS **/ UINT8 LCT; -/** Offset 0x047D - Round Trip Latency Training +/** Offset 0x0487 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS **/ UINT8 RTL; -/** Offset 0x047E - Turn Around Timing Training +/** Offset 0x0488 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS **/ UINT8 TAT; -/** Offset 0x047F - Memory Test +/** Offset 0x0489 - Memory Test Enables/Disable Memory Test $EN_DIS **/ UINT8 MEMTST; -/** Offset 0x0480 - DIMM SPD Alias Test +/** Offset 0x048A - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS **/ UINT8 ALIASCHK; -/** Offset 0x0481 - Receive Enable Centering 1D +/** Offset 0x048B - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS **/ UINT8 RCVENC1D; -/** Offset 0x0482 - Retrain Margin Check +/** Offset 0x048C - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS **/ UINT8 RMC; -/** Offset 0x0483 - Write Drive Strength Up/Dn independently +/** Offset 0x048D - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn independently $EN_DIS **/ UINT8 WRDSUDT; -/** Offset 0x0484 - ECC Support +/** Offset 0x048E - ECC Support Enables/Disable ECC Support $EN_DIS **/ UINT8 EccSupport; -/** Offset 0x0485 - Memory Remap +/** Offset 0x048F - Memory Remap Enables/Disable Memory Remap $EN_DIS **/ UINT8 RemapEnable; -/** Offset 0x0486 - Rank Interleave support +/** Offset 0x0490 - Rank Interleave support Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at the same time. $EN_DIS **/ UINT8 RankInterleave; -/** Offset 0x0487 - Enhanced Interleave support +/** Offset 0x0491 - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS **/ UINT8 EnhancedInterleave; -/** Offset 0x0488 - Memory Trace +/** Offset 0x0492 - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of equal size. This option may change TOLUD and REMAP values as needed. $EN_DIS **/ UINT8 MemoryTrace; -/** Offset 0x0489 - Ch Hash Support +/** Offset 0x0493 - Ch Hash Support Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode $EN_DIS **/ UINT8 ChHashEnable; -/** Offset 0x048A - Extern Therm Status +/** Offset 0x0494 - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS **/ UINT8 EnableExtts; -/** Offset 0x048B - Closed Loop Therm Manage +/** Offset 0x0495 - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS **/ UINT8 EnableCltm; -/** Offset 0x048C - Open Loop Therm Manage +/** Offset 0x0496 - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS **/ UINT8 EnableOltm; -/** Offset 0x048D - DDR PowerDown and idle counter +/** Offset 0x0497 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS **/ UINT8 EnablePwrDn; -/** Offset 0x048E - DDR PowerDown and idle counter - LPDDR +/** Offset 0x0498 - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) $EN_DIS **/ UINT8 EnablePwrDnLpddr; -/** Offset 0x048F - Use user provided power weights, scale factor, and channel power floor values +/** Offset 0x0499 - Use user provided power weights, scale factor, and channel power floor values Enables/Disable Use user provided power weights, scale factor, and channel power floor values $EN_DIS **/ UINT8 UserPowerWeightsEn; -/** Offset 0x0490 - RAPL PL Lock +/** Offset 0x049A - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS **/ UINT8 RaplLim2Lock; -/** Offset 0x0491 - RAPL PL 2 enable +/** Offset 0x049B - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS **/ UINT8 RaplLim2Ena; -/** Offset 0x0492 - RAPL PL 1 enable +/** Offset 0x049C - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS **/ UINT8 RaplLim1Ena; -/** Offset 0x0493 - SelfRefresh Enable +/** Offset 0x049D - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS **/ UINT8 SrefCfgEna; -/** Offset 0x0494 - Throttler CKEMin Defeature - LPDDR +/** Offset 0x049E - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) $EN_DIS **/ UINT8 ThrtCkeMinDefeatLpddr; -/** Offset 0x0495 - Throttler CKEMin Defeature +/** Offset 0x049F - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS **/ UINT8 ThrtCkeMinDefeat; -/** Offset 0x0496 - Enable RH Prevention +/** Offset 0x04A0 - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS **/ UINT8 RhPrevention; -/** Offset 0x0497 - Exit On Failure (MRC) +/** Offset 0x04A1 - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS **/ UINT8 ExitOnFailure; -/** Offset 0x0498 - LPDDR Thermal Sensor +/** Offset 0x04A2 - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS **/ UINT8 DdrThermalSensor; -/** Offset 0x0499 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x04A3 - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedClock; -/** Offset 0x049A - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP +/** Offset 0x04A4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP $EN_DIS **/ UINT8 Ddr4DdpSharedZq; -/** Offset 0x049B +/** Offset 0x04A5 **/ - UINT8 UnusedUpdSpace7; + UINT8 UnusedUpdSpace8; -/** Offset 0x049C - Ch Hash Mask +/** Offset 0x04A6 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6 **/ UINT16 ChHashMask; -/** Offset 0x049E -**/ - UINT8 UnusedUpdSpace8[2]; - -/** Offset 0x04A0 - Base reference clock value +/** Offset 0x04A8 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz **/ UINT32 BClkFrequency; -/** Offset 0x04A4 - Ch Hash Interleaved Bit +/** Offset 0x04AC - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 **/ UINT8 ChHashInterleaveBit; -/** Offset 0x04A5 - Energy Scale Factor +/** Offset 0x04AD - Energy Scale Factor Energy Scale Factor, Default is 4 **/ UINT8 EnergyScaleFact; -/** Offset 0x04A6 - EPG DIMM Idd3N +/** Offset 0x04AE - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 26 **/ UINT16 Idd3n; -/** Offset 0x04A8 - EPG DIMM Idd3P +/** Offset 0x04B0 - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated on a per DIMM basis. Default is 11 **/ UINT16 Idd3p; -/** Offset 0x04AA - CMD Slew Rate Training +/** Offset 0x04B2 - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS **/ UINT8 CMDSR; -/** Offset 0x04AB - CMD Drive Strength and Tx Equalization +/** Offset 0x04B3 - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization $EN_DIS **/ UINT8 CMDDSEQ; -/** Offset 0x04AC - CMD Normalization +/** Offset 0x04B4 - CMD Normalization Enable/Disable CMD Normalization $EN_DIS **/ UINT8 CMDNORM; -/** Offset 0x04AD - Early DQ Write Drive Strength and Equalization Training +/** Offset 0x04B5 - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive Strength and Equalization Training $EN_DIS **/ UINT8 EWRDSEQ; -/** Offset 0x04AE - RH Activation Probability +/** Offset 0x04B6 - RH Activation Probability RH Activation Probability, Probability value is 1/2^(inputvalue) **/ UINT8 RhActProbability; -/** Offset 0x04AF - RAPL PL 2 WindowX +/** Offset 0x04B7 - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindX; -/** Offset 0x04B0 - RAPL PL 2 WindowY +/** Offset 0x04B8 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def) **/ UINT8 RaplLim2WindY; -/** Offset 0x04B1 - RAPL PL 1 WindowX +/** Offset 0x04B9 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindX; -/** Offset 0x04B2 - RAPL PL 1 WindowY +/** Offset 0x04BA - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) **/ UINT8 RaplLim1WindY; -/** Offset 0x04B3 +/** Offset 0x04BB **/ UINT8 UnusedUpdSpace9; -/** Offset 0x04B4 - RAPL PL 2 Power +/** Offset 0x04BC - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (222= Def) **/ UINT16 RaplLim2Pwr; -/** Offset 0x04B6 - RAPL PL 1 Power +/** Offset 0x04BE - RAPL PL 1 Power range[0;2^14-1]= [2047.875;0]in W, (0= Def) **/ UINT16 RaplLim1Pwr; -/** Offset 0x04B8 - Warm Threshold Ch0 Dimm0 +/** Offset 0x04C0 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm0; -/** Offset 0x04B9 - Warm Threshold Ch0 Dimm1 +/** Offset 0x04C1 - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh0Dimm1; -/** Offset 0x04BA - Warm Threshold Ch1 Dimm0 +/** Offset 0x04C2 - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm0; -/** Offset 0x04BB - Warm Threshold Ch1 Dimm1 +/** Offset 0x04C3 - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 WarmThresholdCh1Dimm1; -/** Offset 0x04BC - Hot Threshold Ch0 Dimm0 +/** Offset 0x04C4 - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm0; -/** Offset 0x04BD - Hot Threshold Ch0 Dimm1 +/** Offset 0x04C5 - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh0Dimm1; -/** Offset 0x04BE - Hot Threshold Ch1 Dimm0 +/** Offset 0x04C6 - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm0; -/** Offset 0x04BF - Hot Threshold Ch1 Dimm1 +/** Offset 0x04C7 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255 **/ UINT8 HotThresholdCh1Dimm1; -/** Offset 0x04C0 - Warm Budget Ch0 Dimm0 +/** Offset 0x04C8 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm0; -/** Offset 0x04C1 - Warm Budget Ch0 Dimm1 +/** Offset 0x04C9 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh0Dimm1; -/** Offset 0x04C2 - Warm Budget Ch1 Dimm0 +/** Offset 0x04CA - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm0; -/** Offset 0x04C3 - Warm Budget Ch1 Dimm1 +/** Offset 0x04CB - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 WarmBudgetCh1Dimm1; -/** Offset 0x04C4 - Hot Budget Ch0 Dimm0 +/** Offset 0x04CC - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm0; -/** Offset 0x04C5 - Hot Budget Ch0 Dimm1 +/** Offset 0x04CD - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh0Dimm1; -/** Offset 0x04C6 - Hot Budget Ch1 Dimm0 +/** Offset 0x04CE - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm0; -/** Offset 0x04C7 - Hot Budget Ch1 Dimm1 +/** Offset 0x04CF - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM **/ UINT8 HotBudgetCh1Dimm1; -/** Offset 0x04C8 - Idle Energy Ch0Dimm0 +/** Offset 0x04D0 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm0; -/** Offset 0x04C9 - Idle Energy Ch0Dimm1 +/** Offset 0x04D1 - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh0Dimm1; -/** Offset 0x04CA - Idle Energy Ch1Dimm0 +/** Offset 0x04D2 - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm0; -/** Offset 0x04CB - Idle Energy Ch1Dimm1 +/** Offset 0x04D3 - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) **/ UINT8 IdleEnergyCh1Dimm1; -/** Offset 0x04CC - PowerDown Energy Ch0Dimm0 +/** Offset 0x04D4 - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm0; -/** Offset 0x04CD - PowerDown Energy Ch0Dimm1 +/** Offset 0x04D5 - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh0Dimm1; -/** Offset 0x04CE - PowerDown Energy Ch1Dimm0 +/** Offset 0x04D6 - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm0; -/** Offset 0x04CF - PowerDown Energy Ch1Dimm1 +/** Offset 0x04D7 - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) **/ UINT8 PdEnergyCh1Dimm1; -/** Offset 0x04D0 - Activate Energy Ch0Dimm0 +/** Offset 0x04D8 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm0; -/** Offset 0x04D1 - Activate Energy Ch0Dimm1 +/** Offset 0x04D9 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh0Dimm1; -/** Offset 0x04D2 - Activate Energy Ch1Dimm0 +/** Offset 0x04DA - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm0; -/** Offset 0x04D3 - Activate Energy Ch1Dimm1 +/** Offset 0x04DB - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def) **/ UINT8 ActEnergyCh1Dimm1; -/** Offset 0x04D4 - Read Energy Ch0Dimm0 +/** Offset 0x04DC - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm0; -/** Offset 0x04D5 - Read Energy Ch0Dimm1 +/** Offset 0x04DD - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh0Dimm1; -/** Offset 0x04D6 - Read Energy Ch1Dimm0 +/** Offset 0x04DE - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm0; -/** Offset 0x04D7 - Read Energy Ch1Dimm1 +/** Offset 0x04DF - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def) **/ UINT8 RdEnergyCh1Dimm1; -/** Offset 0x04D8 - Write Energy Ch0Dimm0 +/** Offset 0x04E0 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm0; -/** Offset 0x04D9 - Write Energy Ch0Dimm1 +/** Offset 0x04E1 - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh0Dimm1; -/** Offset 0x04DA - Write Energy Ch1Dimm0 +/** Offset 0x04E2 - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm0; -/** Offset 0x04DB - Write Energy Ch1Dimm1 +/** Offset 0x04E3 - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def) **/ UINT8 WrEnergyCh1Dimm1; -/** Offset 0x04DC - Throttler CKEMin Timer +/** Offset 0x04E4 - Throttler CKEMin Timer Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x30 **/ UINT8 ThrtCkeMinTmr; -/** Offset 0x04DD - Cke Rank Mapping +/** Offset 0x04E5 - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies which rank CKE[i] goes to. **/ UINT8 CkeRankMapping; -/** Offset 0x04DE - Rapl Power Floor Ch0 +/** Offset 0x04E6 - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh0; -/** Offset 0x04DF - Rapl Power Floor Ch1 +/** Offset 0x04E7 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def) **/ UINT8 RaplPwrFlCh1; -/** Offset 0x04E0 - Command Rate Support +/** Offset 0x04E8 - Command Rate Support CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS **/ UINT8 EnCmdRate; -/** Offset 0x04E1 - REFRESH_2X_MODE +/** Offset 0x04E9 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only **/ UINT8 Refresh2X; -/** Offset 0x04E2 - Energy Performance Gain +/** Offset 0x04EA - Energy Performance Gain Enable/disable(default) Energy Performance Gain. $EN_DIS **/ UINT8 EpgEnable; -/** Offset 0x04E3 - Row Hammer Solution +/** Offset 0x04EB - Row Hammer Solution Type of method used to prevent Row Hammer. Default is Hardware RHP 0:Hardware RHP, 1:2x Refresh **/ UINT8 RhSolution; -/** Offset 0x04E4 - User Manual Threshold +/** Offset 0x04EC - User Manual Threshold Disabled: Predefined threshold will be used.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserThresholdEnable; -/** Offset 0x04E5 - User Manual Budget +/** Offset 0x04ED - User Manual Budget Disabled: Configuration of memories will defined the Budget value.\n Enabled: User Input will be used. $EN_DIS **/ UINT8 UserBudgetEnable; -/** Offset 0x04E6 - TcritMax +/** Offset 0x04EE - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax has to be greater than THIGHMax .\n Critical temperature will be TcritMax **/ UINT8 TsodTcritMax; -/** Offset 0x04E7 - Event mode +/** Offset 0x04EF - Event mode Disable:Comparator mode.\n Enable:Interrupt mode $EN_DIS **/ UINT8 TsodEventMode; -/** Offset 0x04E8 - EVENT polarity +/** Offset 0x04F0 - EVENT polarity Disable:Active LOW.\n Enable:Active HIGH $EN_DIS **/ UINT8 TsodEventPolarity; -/** Offset 0x04E9 - Critical event only +/** Offset 0x04F1 - Critical event only Disable:Trips on alarm or critical.\n Enable:Trips only if criticaal temperature is reached $EN_DIS **/ UINT8 TsodCriticalEventOnly; -/** Offset 0x04EA - Event output control +/** Offset 0x04F2 - Event output control Disable:Event output disable.\n Enable:Event output enabled $EN_DIS **/ UINT8 TsodEventOutputControl; -/** Offset 0x04EB - Alarm window lock bit +/** Offset 0x04F3 - Alarm window lock bit Disable:Alarm trips are not locked and can be changed.\n Enable:Alarm trips are locked and cannot be changed $EN_DIS **/ UINT8 TsodAlarmwindowLockBit; -/** Offset 0x04EC - Critical trip lock bit +/** Offset 0x04F4 - Critical trip lock bit Disable:Critical trip is not locked and can be changed.\n Enable:Critical trip is locked and cannot be changed $EN_DIS **/ UINT8 TsodCriticaltripLockBit; -/** Offset 0x04ED - Shutdown mode +/** Offset 0x04F5 - Shutdown mode Disable:Temperature sensor enable.\n Enable:Temperature sensor disable $EN_DIS **/ UINT8 TsodShutdownMode; -/** Offset 0x04EE - ThighMax +/** Offset 0x04F6 - ThighMax Thigh = ThighMax (Default is 93) **/ UINT8 TsodThigMax; -/** Offset 0x04EF - User Manual Thig and Tcrit +/** Offset 0x04F7 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of memories and 1x or 2xrefresh rate.\n Enabled: User Input will define for Thigh and Tcrit. @@ -2221,32 +2252,32 @@ typedef struct { **/ UINT8 TsodManualEnable; -/** Offset 0x04F0 - Force OLTM or 2X Refresh when needed +/** Offset 0x04F8 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.\n Enabled: = Force 2x Refresh. $EN_DIS **/ UINT8 ForceOltmOrRefresh2x; -/** Offset 0x04F1 - Pwr Down Idle Timer +/** Offset 0x04F9 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means AUTO: 64 for ULX/ULT, 128 for DT/Halo **/ UINT8 PwdwnIdleCounter; -/** Offset 0x04F2 - Bitmask of ranks that have CA bus terminated +/** Offset 0x04FA - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, Rank0 is terminating and Rank1 is non-terminating **/ UINT8 CmdRanksTerminated; -/** Offset 0x04F3 - GDXC MOT enable +/** Offset 0x04FB - GDXC MOT enable GDXC MOT enable. $EN_DIS **/ UINT8 GdxcEnable; -/** Offset 0x04F4 - PcdSerialDebugLevel +/** Offset 0x04FC - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -2255,148 +2286,154 @@ typedef struct { **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x04F5 - Fivr Faults +/** Offset 0x04FD - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrFaults; -/** Offset 0x04F6 - Fivr Efficiency +/** Offset 0x04FE - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 FivrEfficiency; -/** Offset 0x04F7 - Safe Mode Support +/** Offset 0x04FF - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x04F8 - Ask MRC to clear memory content +/** Offset 0x0500 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. $EN_DIS **/ UINT8 CleanMemory; -/** Offset 0x04F9 - LpDdrDqDqsReTraining +/** Offset 0x0501 - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS **/ UINT8 LpDdrDqDqsReTraining; -/** Offset 0x04FA - Post Code Output Port +/** Offset 0x0502 - Post Code Output Port This option configures Post Code Output Port **/ UINT16 PostCodeOutputPort; -/** Offset 0x04FC - RMTLoopCount +/** Offset 0x0504 - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO **/ UINT8 RMTLoopCount; -/** Offset 0x04FD - BER Support +/** Offset 0x0505 - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation. 0:Disable, 1:Enable **/ UINT8 EnBER; -/** Offset 0x04FE - Dual Dimm Per-Channel Board Type +/** Offset 0x0506 - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used to limit maximum frequency for some SKUs. 0:1DPC, 1:2DPC **/ UINT8 DualDimmPerChannelBoardType; -/** Offset 0x04FF - DDR4 Mixed U-DIMM 2DPC Limitation +/** Offset 0x0507 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. Disable=0, Enable(Default)=1 $EN_DIS **/ UINT8 Ddr4MixedUDimm2DpcLimit; -/** Offset 0x0500 - CFL Reserved +/** Offset 0x0508 - CFL Reserved Reserved FspmConfig CFL $EN_DIS **/ UINT8 ReservedFspmUpdCfl[2]; -/** Offset 0x0502 - Memory Test on Warm Boot +/** Offset 0x050A - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable **/ UINT8 MemTestOnWarmBoot; -/** Offset 0x0503 - Throttler CKEMin Timer - LPDDR +/** Offset 0x050B - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). Default is 0x40 **/ UINT8 ThrtCkeMinTmrLpddr; -/** Offset 0x0504 - State of X2APIC_OPT_OUT bit in the DMAR table +/** Offset 0x050C - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS **/ UINT8 X2ApicOptOut; -/** Offset 0x0505 +/** Offset 0x050D - MRC Force training on Warm + Enables/Disable the MRC training on warm boot + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x050E **/ UINT8 UnusedUpdSpace10[2]; -/** Offset 0x0507 +/** Offset 0x0510 **/ - UINT8 ReservedFspmUpd[9]; + UINT8 ReservedFspmUpd[8]; } FSP_M_CONFIG; /** Fsp M Test Configuration **/ typedef struct { -/** Offset 0x0510 +/** Offset 0x0518 **/ UINT32 Signature; -/** Offset 0x0514 - Skip external display device scanning +/** Offset 0x051C - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x0515 - Generate BIOS Data ACPI Table +/** Offset 0x051D - Generate BIOS Data ACPI Table Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it $EN_DIS **/ UINT8 BdatEnable; -/** Offset 0x0516 - Detect External Graphics device for LegacyOpROM +/** Offset 0x051E - Detect External Graphics device for LegacyOpROM Detect and report if external graphics device only support LegacyOpROM or not (to support CSM auto-enable). Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 ScanExtGfxForLegacyOpRom; -/** Offset 0x0517 - Lock PCU Thermal Management registers +/** Offset 0x051F - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x0518 - DMI Max Link Speed +/** Offset 0x0520 - DMI Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 **/ UINT8 DmiMaxLinkSpeed; -/** Offset 0x0519 - DMI Equalization Phase 2 +/** Offset 0x0521 - DMI Equalization Phase 2 DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): AUTO - Use the current default method 0:Disable phase2, 1:Enable phase2, 2:Auto **/ UINT8 DmiGen3EqPh2Enable; -/** Offset 0x051A - DMI Gen3 Equalization Phase3 +/** Offset 0x0522 - DMI Gen3 Equalization Phase3 DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2406,35 +2443,35 @@ typedef struct { **/ UINT8 DmiGen3EqPh3Method; -/** Offset 0x051B - Phase2 EQ enable on the PEG 0:1:0. +/** Offset 0x0523 - Phase2 EQ enable on the PEG 0:1:0. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg0Gen3EqPh2Enable; -/** Offset 0x051C - Phase2 EQ enable on the PEG 0:1:1. +/** Offset 0x0524 - Phase2 EQ enable on the PEG 0:1:1. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg1Gen3EqPh2Enable; -/** Offset 0x051D - Phase2 EQ enable on the PEG 0:1:2. +/** Offset 0x0525 - Phase2 EQ enable on the PEG 0:1:2. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg2Gen3EqPh2Enable; -/** Offset 0x051E - Phase2 EQ enable on the PEG 0:1:3. +/** Offset 0x0526 - Phase2 EQ enable on the PEG 0:1:3. Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): Enable phase 2, Auto(0x2)(Default): Use the current default method 0:Disable, 1:Enable, 2:Auto **/ UINT8 Peg3Gen3EqPh2Enable; -/** Offset 0x051F - Phase3 EQ method on the PEG 0:1:0. +/** Offset 0x0527 - Phase3 EQ method on the PEG 0:1:0. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2444,7 +2481,7 @@ typedef struct { **/ UINT8 Peg0Gen3EqPh3Method; -/** Offset 0x0520 - Phase3 EQ method on the PEG 0:1:1. +/** Offset 0x0528 - Phase3 EQ method on the PEG 0:1:1. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2454,7 +2491,7 @@ typedef struct { **/ UINT8 Peg1Gen3EqPh3Method; -/** Offset 0x0521 - Phase3 EQ method on the PEG 0:1:2. +/** Offset 0x0529 - Phase3 EQ method on the PEG 0:1:2. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2464,7 +2501,7 @@ typedef struct { **/ UINT8 Peg2Gen3EqPh3Method; -/** Offset 0x0522 - Phase3 EQ method on the PEG 0:1:3. +/** Offset 0x052A - Phase3 EQ method on the PEG 0:1:3. PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static @@ -2474,14 +2511,14 @@ typedef struct { **/ UINT8 Peg3Gen3EqPh3Method; -/** Offset 0x0523 - Enable/Disable PEG GEN3 Static EQ Phase1 programming +/** Offset 0x052B - Enable/Disable PEG GEN3 Static EQ Phase1 programming Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming $EN_DIS **/ UINT8 PegGen3ProgramStaticEq; -/** Offset 0x0524 - PEG Gen3 SwEq Always Attempt +/** Offset 0x052C - PEG Gen3 SwEq Always Attempt Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test and generate new EQ values every boot, not recommended @@ -2489,7 +2526,7 @@ typedef struct { **/ UINT8 Gen3SwEqAlwaysAttempt; -/** Offset 0x0525 - Select number of TxEq presets to test in the PCIe/DMI SwEq +/** Offset 0x052D - Select number of TxEq presets to test in the PCIe/DMI SwEq Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the current default method (Default)Auto will test Presets 7, 3, and 5. It is possible @@ -2499,7 +2536,7 @@ typedef struct { **/ UINT8 Gen3SwEqNumberOfPresets; -/** Offset 0x0526 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq +/** Offset 0x052E - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): Use the current default @@ -2507,7 +2544,7 @@ typedef struct { **/ UINT8 Gen3SwEqEnableVocTest; -/** Offset 0x0527 - PCIe Rx Compliance Testing Mode +/** Offset 0x052F - PCIe Rx Compliance Testing Mode Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; it should only be set when doing PCIe compliance testing @@ -2515,12 +2552,12 @@ typedef struct { **/ UINT8 PegRxCemTestingMode; -/** Offset 0x0528 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled +/** Offset 0x0530 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 **/ UINT8 PegRxCemLoopbackLane; -/** Offset 0x0529 - Generate PCIe BDAT Margin Table +/** Offset 0x0531 - Generate PCIe BDAT Margin Table Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin data generation, Enable(0x1): Generate PCIe BDAT margin data @@ -2528,7 +2565,7 @@ typedef struct { **/ UINT8 PegGenerateBdatMarginTable; -/** Offset 0x052A - PCIe Non-Protocol Awareness for Rx Compliance Testing +/** Offset 0x0532 - PCIe Non-Protocol Awareness for Rx Compliance Testing Set this policy to enable the generation and addition of PCIe margin data to the BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for @@ -2537,7 +2574,7 @@ typedef struct { **/ UINT8 PegRxCemNonProtocolAwareness; -/** Offset 0x052B - PCIe Override RxCTLE +/** Offset 0x0533 - PCIe Override RxCTLE Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2545,7 +2582,7 @@ typedef struct { **/ UINT8 PegGen3RxCtleOverride; -/** Offset 0x052C - Rsvd +/** Offset 0x0534 - Rsvd Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmodified @@ -2553,284 +2590,284 @@ typedef struct { **/ UINT8 PegGen3Rsvd; -/** Offset 0x052D - PEG Gen3 Root port preset values per lane +/** Offset 0x0535 - PEG Gen3 Root port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 PegGen3RootPortPreset[20]; -/** Offset 0x0541 - PEG Gen3 End port preset values per lane +/** Offset 0x0549 - PEG Gen3 End port preset values per lane Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane **/ UINT8 PegGen3EndPointPreset[20]; -/** Offset 0x0555 - PEG Gen3 End port Hint values per lane +/** Offset 0x055D - PEG Gen3 End port Hint values per lane Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane **/ UINT8 PegGen3EndPointHint[20]; -/** Offset 0x0569 +/** Offset 0x0571 **/ UINT8 UnusedUpdSpace11; -/** Offset 0x056A - Jitter Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x0572 - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterDwellTime; -/** Offset 0x056C - Jitter Error Target for PCIe Gen3 Software Equalization +/** Offset 0x0574 - Jitter Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 1. @warning Do not change from the default **/ UINT16 Gen3SwEqJitterErrorTarget; -/** Offset 0x056E - VOC Dwell Time for PCIe Gen3 Software Equalization +/** Offset 0x0576 - VOC Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 10000. @warning Do not change from the default **/ UINT16 Gen3SwEqVocDwellTime; -/** Offset 0x0570 - VOC Error Target for PCIe Gen3 Software Equalization +/** Offset 0x0578 - VOC Error Target for PCIe Gen3 Software Equalization Range: 0-65535, default is 2. @warning Do not change from the default **/ UINT16 Gen3SwEqVocErrorTarget; -/** Offset 0x0572 - Panel Power Enable +/** Offset 0x057A - Panel Power Enable Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel). 0=Disable, 1(Default)=Enable $EN_DIS **/ UINT8 PanelPowerEnable; -/** Offset 0x0573 - BdatTestType +/** Offset 0x057B - BdatTestType Indicates the type of Memory Training data to populate into the BDAT ACPI table. 0:Rank Margin Tool, 1:Margin2D **/ UINT8 BdatTestType; -/** Offset 0x0574 - Disable VT-d +/** Offset 0x057C - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisable; -/** Offset 0x0575 +/** Offset 0x057D **/ UINT8 UnusedUpdSpace12; -/** Offset 0x0576 - Delta T12 Power Cycle Delay required in ms +/** Offset 0x057E - Delta T12 Power Cycle Delay required in ms Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate T12 Delay to max 500ms 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay **/ UINT16 DeltaT12PowerCycleDelayPreMem; -/** Offset 0x0578 - SaPreMemTestRsvd +/** Offset 0x0580 - SaPreMemTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SaPreMemTestRsvd[9]; -/** Offset 0x0581 +/** Offset 0x0589 **/ UINT8 UnusedUpdSpace13; -/** Offset 0x0582 - TotalFlashSize +/** Offset 0x058A - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable **/ UINT16 TotalFlashSize; -/** Offset 0x0584 - BiosSize +/** Offset 0x058C - BiosSize Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable **/ UINT16 BiosSize; -/** Offset 0x0586 - TxtAcheckRequest +/** Offset 0x058E - TxtAcheckRequest Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. $EN_DIS **/ UINT8 TxtAcheckRequest; -/** Offset 0x0587 - SecurityTestRsvd +/** Offset 0x058F - SecurityTestRsvd Reserved for SA Pre-Mem Test $EN_DIS **/ UINT8 SecurityTestRsvd[3]; -/** Offset 0x058A - Smbus dynamic power gating +/** Offset 0x0592 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. $EN_DIS **/ UINT8 SmbusDynamicPowerGating; -/** Offset 0x058B - Disable and Lock Watch Dog Register +/** Offset 0x0593 - Disable and Lock Watch Dog Register Set 1 to clear WDT status, then disable and lock WDT registers. $EN_DIS **/ UINT8 WdtDisableAndLock; -/** Offset 0x058C - SMBUS SPD Write Disable +/** Offset 0x0594 - SMBUS SPD Write Disable Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write Disable bit. For security recommendations, SPD write disable bit must be set. $EN_DIS **/ UINT8 SmbusSpdWriteDisable; -/** Offset 0x058D - ReservedPchPreMemTest +/** Offset 0x0595 - ReservedPchPreMemTest Reserved for Pch Pre-Mem Test $EN_DIS **/ UINT8 ReservedPchPreMemTest[16]; -/** Offset 0x059D - Force ME DID Init Status +/** Offset 0x05A5 - Force ME DID Init Status Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set ME DID init stat value $EN_DIS **/ UINT8 DidInitStat; -/** Offset 0x059E - CPU Replaced Polling Disable +/** Offset 0x05A6 - CPU Replaced Polling Disable Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop $EN_DIS **/ UINT8 DisableCpuReplacedPolling; -/** Offset 0x059F - ME DID Message +/** Offset 0x05A7 - ME DID Message Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent the DID message from being sent) $EN_DIS **/ UINT8 SendDidMsg; -/** Offset 0x05A0 - Check HECI message before send +/** Offset 0x05A8 - Check HECI message before send Test, 0: disable, 1: enable, Enable/Disable message check. $EN_DIS **/ UINT8 DisableMessageCheck; -/** Offset 0x05A1 - Skip MBP HOB +/** Offset 0x05A9 - Skip MBP HOB Test, 0: disable, 1: enable, Enable/Disable MOB HOB. $EN_DIS **/ UINT8 SkipMbpHob; -/** Offset 0x05A2 - HECI2 Interface Communication +/** Offset 0x05AA - HECI2 Interface Communication Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. $EN_DIS **/ UINT8 HeciCommunication2; -/** Offset 0x05A3 - Enable KT device +/** Offset 0x05AB - Enable KT device Test, 0: disable, 1: enable, Enable or Disable KT device. $EN_DIS **/ UINT8 KtDeviceEnable; -/** Offset 0x05A4 - tRd2RdSG +/** Offset 0x05AC - tRd2RdSG Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2RdSG; -/** Offset 0x05A5 - tRd2RdDG +/** Offset 0x05AD - tRd2RdDG Delay between Read-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDG; -/** Offset 0x05A6 - tRd2RdDR +/** Offset 0x05AE - tRd2RdDR Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDR; -/** Offset 0x05A7 - tRd2RdDD +/** Offset 0x05AF - tRd2RdDD Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2RdDD; -/** Offset 0x05A8 - tWr2RdSG +/** Offset 0x05B0 - tWr2RdSG Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86. **/ UINT8 tWr2RdSG; -/** Offset 0x05A9 - tWr2RdDG +/** Offset 0x05B1 - tWr2RdDG Delay between Write-to-Read commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDG; -/** Offset 0x05AA - tWr2RdDR +/** Offset 0x05B2 - tWr2RdDR Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDR; -/** Offset 0x05AB - tWr2RdDD +/** Offset 0x05B3 - tWr2RdDD Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2RdDD; -/** Offset 0x05AC - tWr2WrSG +/** Offset 0x05B4 - tWr2WrSG Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tWr2WrSG; -/** Offset 0x05AD - tWr2WrDG +/** Offset 0x05B5 - tWr2WrDG Delay between Write-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDG; -/** Offset 0x05AE - tWr2WrDR +/** Offset 0x05B6 - tWr2WrDR Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDR; -/** Offset 0x05AF - tWr2WrDD +/** Offset 0x05B7 - tWr2WrDD Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tWr2WrDD; -/** Offset 0x05B0 - tRd2WrSG +/** Offset 0x05B8 - tRd2WrSG Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54. **/ UINT8 tRd2WrSG; -/** Offset 0x05B1 - tRd2WrDG +/** Offset 0x05B9 - tRd2WrDG Delay between Read-to-Write commands in different Bank Group for DDR4. All other DDR technologies should set this equal to SG. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDG; -/** Offset 0x05B2 - tRd2WrDR +/** Offset 0x05BA - tRd2WrDR Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDR; -/** Offset 0x05B3 - tRd2WrDD +/** Offset 0x05BB - tRd2WrDD Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54. **/ UINT8 tRd2WrDD; -/** Offset 0x05B4 - tRRD_L +/** Offset 0x05BC - tRRD_L Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_L; -/** Offset 0x05B5 - tRRD_S +/** Offset 0x05BD - tRRD_S Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 31 **/ UINT8 tRRD_S; -/** Offset 0x05B6 - tWTR_L +/** Offset 0x05BE - tWTR_L Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 60 **/ UINT8 tWTR_L; -/** Offset 0x05B7 - tWTR_S +/** Offset 0x05BF - tWTR_S Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only. 0: AUTO, max: 28 **/ UINT8 tWTR_S; -/** Offset 0x05B8 +/** Offset 0x05C0 **/ UINT8 ReservedFspmTestUpd[4]; } FSP_M_TEST_CONFIG; @@ -2851,11 +2888,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x0510 +/** Offset 0x0518 **/ FSP_M_TEST_CONFIG FspmTestConfig; -/** Offset 0x05BC +/** Offset 0x05C4 **/ UINT32 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index c595fd398c..e6f891987e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -37,49 +37,49 @@ are permitted provided that the following conditions are met: #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ @@ -356,11 +356,16 @@ typedef struct { **/ UINT32 BltBufferSize; -/** Offset 0x0084 - SaPostMemProductionRsvd +/** Offset 0x0084 - Program GT Chicken bits + Progarm the GT chicken bits in GTTMMADR + 0xD00 BITS [3:1] +**/ + UINT8 ProgramGtChickenBits; + +/** Offset 0x0085 - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS **/ - UINT8 SaPostMemProductionRsvd[35]; + UINT8 SaPostMemProductionRsvd[34]; /** Offset 0x00A7 - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for @@ -801,983 +806,982 @@ typedef struct { **/ UINT8 SerialIoUartAutoFlow[3]; -/** Offset 0x01C6 +/** Offset 0x01C6 - Serial IO UART Pin Mux + Applies only to UART0 muxed with CNVI 0 = GPIO C8 to C11 1 = GPIO F5 - + F7 (PCH LP) J5 - J7 (PCH H) **/ - UINT8 UnusedUpdSpace9[2]; + UINT8 SerialIoUartPinMux[3]; -/** Offset 0x01C8 - SerialIoUartRxPinMux - Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for - possible values. -**/ - UINT32 SerialIoUartRxPinMux[3]; - -/** Offset 0x01D4 - SerialIoUartTxPinMux - Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for - possible values. -**/ - UINT32 SerialIoUartTxPinMux[3]; - -/** Offset 0x01E0 - SerialIoUartRtsPinMux - Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 SerialIoUartRtsPinMux[3]; - -/** Offset 0x01EC - SerialIoUartCtsPinMux - Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 SerialIoUartCtsPinMux[3]; - -/** Offset 0x01F8 - UART Number For Debug Purpose +/** Offset 0x01C9 - UART Number For Debug Purpose UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:UART0, 1:UART1, 2:UART2 **/ UINT8 SerialIoDebugUartNumber; -/** Offset 0x01F9 - Serial IO UART DBG2 table +/** Offset 0x01CA - Serial IO UART DBG2 table Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; 1: Enable. **/ UINT8 SerialIoUartDbg2[3]; -/** Offset 0x01FC - Enable eMMC Controller +/** Offset 0x01CD - Enable eMMC Controller Enable/disable eMMC Controller. $EN_DIS **/ UINT8 ScsEmmcEnabled; -/** Offset 0x01FD - Enable eMMC HS400 Mode +/** Offset 0x01CE - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. $EN_DIS **/ UINT8 ScsEmmcHs400Enabled; -/** Offset 0x01FE - Enable SdCard Controller +/** Offset 0x01CF - Enable SdCard Controller Enable/disable SD Card Controller. $EN_DIS **/ UINT8 ScsSdCardEnabled; -/** Offset 0x01FF - Show SPI controller +/** Offset 0x01D0 - Show SPI controller Enable/disable to show SPI controller. $EN_DIS **/ UINT8 ShowSpiController; -/** Offset 0x0200 - Enable SATA SALP Support +/** Offset 0x01D1 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. $EN_DIS **/ UINT8 SataSalpSupport; -/** Offset 0x0201 - Enable SATA ports +/** Offset 0x01D2 - Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsEnable[8]; -/** Offset 0x0209 - Enable SATA DEVSLP Feature +/** Offset 0x01DA - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 SataPortsDevSlp[8]; -/** Offset 0x0211 - Enable USB2 ports +/** Offset 0x01E2 - Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb20Enable[16]; -/** Offset 0x0221 - Enable USB3 ports +/** Offset 0x01F2 - Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ UINT8 PortUsb30Enable[10]; -/** Offset 0x022B - Enable xDCI controller +/** Offset 0x01FC - Enable xDCI controller Enable/disable to xDCI controller. $EN_DIS **/ UINT8 XdciEnable; -/** Offset 0x022C - Address of PCH_DEVICE_INTERRUPT_CONFIG table. +/** Offset 0x01FD +**/ + UINT8 UnusedUpdSpace9[3]; + +/** Offset 0x0200 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. **/ UINT32 DevIntConfigPtr; -/** Offset 0x0230 - Number of DevIntConfig Entry +/** Offset 0x0204 - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr must not be NULL. **/ UINT8 NumOfDevIntConfig; -/** Offset 0x0231 - PIRQx to IRQx Map Config +/** Offset 0x0205 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy 8259 PCI mode. **/ UINT8 PxRcConfig[8]; -/** Offset 0x0239 - Select GPIO IRQ Route +/** Offset 0x020D - Select GPIO IRQ Route GPIO IRQ Select. The valid value is 14 or 15. **/ UINT8 GpioIrqRoute; -/** Offset 0x023A - Select SciIrqSelect +/** Offset 0x020E - Select SciIrqSelect SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. **/ UINT8 SciIrqSelect; -/** Offset 0x023B - Select TcoIrqSelect +/** Offset 0x020F - Select TcoIrqSelect TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. **/ UINT8 TcoIrqSelect; -/** Offset 0x023C - Enable/Disable Tco IRQ +/** Offset 0x0210 - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS **/ UINT8 TcoIrqEnable; -/** Offset 0x023D - PCH HDA Verb Table Entry Number +/** Offset 0x0211 - PCH HDA Verb Table Entry Number Number of Entries in Verb Table. **/ UINT8 PchHdaVerbTableEntryNum; -/** Offset 0x023E +/** Offset 0x0212 **/ UINT8 UnusedUpdSpace10[2]; -/** Offset 0x0240 - PCH HDA Verb Table Pointer +/** Offset 0x0214 - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table. **/ UINT32 PchHdaVerbTablePtr; -/** Offset 0x0244 - PCH HDA Codec Sx Wake Capability +/** Offset 0x0218 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx **/ UINT8 PchHdaCodecSxWakeCapability; -/** Offset 0x0245 - Enable SATA +/** Offset 0x0219 - Enable SATA Enable/disable SATA controller. $EN_DIS **/ UINT8 SataEnable; -/** Offset 0x0246 - SATA Mode +/** Offset 0x021A - SATA Mode Select SATA controller working mode. 0:AHCI, 1:RAID **/ UINT8 SataMode; -/** Offset 0x0247 - USB Per Port HS Preemphasis Bias +/** Offset 0x021B - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. **/ UINT8 Usb2AfePetxiset[16]; -/** Offset 0x0257 - USB Per Port HS Transmitter Bias +/** Offset 0x022B - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. **/ UINT8 Usb2AfeTxiset[16]; -/** Offset 0x0267 - USB Per Port HS Transmitter Emphasis +/** Offset 0x023B - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. **/ UINT8 Usb2AfePredeemp[16]; -/** Offset 0x0277 - USB Per Port Half Bit Pre-emphasis +/** Offset 0x024B - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. One byte for each port. **/ UINT8 Usb2AfePehalfbit[16]; -/** Offset 0x0287 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment +/** Offset 0x025B - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDeEmphEnable[10]; -/** Offset 0x0291 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting +/** Offset 0x0265 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. **/ UINT8 Usb3HsioTxDeEmph[10]; -/** Offset 0x029B - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x026F - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmpEnable[10]; -/** Offset 0x02A5 - USB 3.0 TX Output Downscale Amplitude Adjustment +/** Offset 0x0279 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. One byte for each port. **/ UINT8 Usb3HsioTxDownscaleAmp[10]; -/** Offset 0x02AF - Enable LAN +/** Offset 0x0283 - Enable xHCI LTR override + Enables override of recommended LTR values for xHCI + $EN_DIS +**/ + UINT8 PchUsbLtrOverrideEnable; + +/** Offset 0x0284 - xHCI High Idle Time LTR override + Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting +**/ + UINT32 PchUsbLtrHighIdleTimeOverride; + +/** Offset 0x0288 - xHCI Medium Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting +**/ + UINT32 PchUsbLtrMediumIdleTimeOverride; + +/** Offset 0x028C - xHCI Low Idle Time LTR override + Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting +**/ + UINT32 PchUsbLtrLowIdleTimeOverride; + +/** Offset 0x0290 - Enable LAN Enable/disable LAN controller. $EN_DIS **/ UINT8 PchLanEnable; -/** Offset 0x02B0 - Enable HD Audio Link +/** Offset 0x0291 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHda; -/** Offset 0x02B1 - Enable HD Audio DMIC0 Link +/** Offset 0x0292 - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic0; -/** Offset 0x02B2 - Enable HD Audio DMIC1 Link +/** Offset 0x0293 - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. $EN_DIS **/ UINT8 PchHdaAudioLinkDmic1; -/** Offset 0x02B3 - Enable HD Audio SSP0 Link +/** Offset 0x0294 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp0; -/** Offset 0x02B4 - Enable HD Audio SSP1 Link +/** Offset 0x0295 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp1; -/** Offset 0x02B5 - Enable HD Audio SSP2 Link +/** Offset 0x0296 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link. $EN_DIS **/ UINT8 PchHdaAudioLinkSsp2; -/** Offset 0x02B6 - Enable HD Audio SoundWire#1 Link +/** Offset 0x0297 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link. Muxed with HDA. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw1; -/** Offset 0x02B7 - Enable HD Audio SoundWire#2 Link +/** Offset 0x0298 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link. Muxed with SSP1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw2; -/** Offset 0x02B8 - Enable HD Audio SoundWire#3 Link +/** Offset 0x0299 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw3; -/** Offset 0x02B9 - Enable HD Audio SoundWire#4 Link +/** Offset 0x029A - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. $EN_DIS **/ UINT8 PchHdaAudioLinkSndw4; -/** Offset 0x02BA - Soundwire Clock Buffer GPIO RCOMP Setting +/** Offset 0x029B - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. $EN_DIS **/ UINT8 PchHdaSndwBufferRcomp; -/** Offset 0x02BB -**/ - UINT8 UnusedUpdSpace11; - -/** Offset 0x02BC - PTM for PCIE RP Mask +/** Offset 0x029C - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpPtmMask; -/** Offset 0x02C0 - DPC for PCIE RP Mask +/** Offset 0x02A0 - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcMask; -/** Offset 0x02C4 - DPC Extensions PCIE RP Mask +/** Offset 0x02A4 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpDpcExtensionsMask; -/** Offset 0x02C8 - USB PDO Programming +/** Offset 0x02A8 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming during later phase. 1: enable, 0: disable $EN_DIS **/ UINT8 UsbPdoProgramming; -/** Offset 0x02C9 +/** Offset 0x02A9 **/ - UINT8 UnusedUpdSpace12[3]; + UINT8 UnusedUpdSpace11[3]; -/** Offset 0x02CC - Power button debounce configuration +/** Offset 0x02AC - Power button debounce configuration Debounce time for PWRBTN in microseconds. For values not supported by HW, they will be rounded down to closest supported on. 0: disable, 250-1024000us: supported range **/ UINT32 PmcPowerButtonDebounce; -/** Offset 0x02D0 - PCH eSPI Master and Slave BME enabled +/** Offset 0x02B0 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS **/ UINT8 PchEspiBmeMasterSlaveEnabled; -/** Offset 0x02D1 - PCH SATA use RST Legacy OROM +/** Offset 0x02B1 - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS **/ UINT8 SataRstLegacyOrom; -/** Offset 0x02D2 +/** Offset 0x02B2 **/ - UINT8 UnusedUpdSpace13[2]; + UINT8 UnusedUpdSpace12[2]; -/** Offset 0x02D4 - Trace Hub Memory Base +/** Offset 0x02B4 - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly. **/ UINT32 TraceHubMemBase; -/** Offset 0x02D8 - PMC Debug Message Enable +/** Offset 0x02B8 - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix $EN_DIS **/ UINT8 PmcDbgMsgEn; -/** Offset 0x02D9 +/** Offset 0x02B9 **/ - UINT8 UnusedUpdSpace14[3]; + UINT8 UnusedUpdSpace13[3]; -/** Offset 0x02DC - Pointer of ChipsetInit Binary +/** Offset 0x02BC - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer. **/ UINT32 ChipsetInitBinPtr; -/** Offset 0x02E0 - Length of ChipsetInit Binary +/** Offset 0x02C0 - Length of ChipsetInit Binary ChipsetInit Binary Length. **/ UINT32 ChipsetInitBinLen; -/** Offset 0x02E4 - Enable Ufs Controller +/** Offset 0x02C4 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. $EN_DIS **/ UINT8 ScsUfsEnabled; -/** Offset 0x02E5 - CNVi Configuration +/** Offset 0x02C5 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. [Auto Detection] assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. 0:Disable, 1:Auto **/ UINT8 CnviMode; -/** Offset 0x02E6 - CNVi BT Core +/** Offset 0x02C6 - CNVi BT Core Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtCore; -/** Offset 0x02E7 - CNVi BT Audio Offload +/** Offset 0x02C7 - CNVi BT Audio Offload Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE $EN_DIS **/ UINT8 CnviBtAudioOffload; -/** Offset 0x02E8 - SdCard power enable polarity +/** Offset 0x02C8 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high **/ UINT8 SdCardPowerEnableActiveHigh; -/** Offset 0x02E9 - PCH USB2 PHY Power Gating enable +/** Offset 0x02C9 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS **/ UINT8 PchUsb2PhySusPgEnable; -/** Offset 0x02EA - PCH USB OverCurrent mapping enable +/** Offset 0x02CA - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS **/ UINT8 PchUsbOverCurrentEnable; -/** Offset 0x02EB - Espi Lgmr Memory Range decode +/** Offset 0x02CB - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS **/ UINT8 PchEspiLgmrEnable; -/** Offset 0x02EC - PCHHOT# pin +/** Offset 0x02CC - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable $EN_DIS **/ UINT8 PchHotEnable; -/** Offset 0x02ED - SATA LED +/** Offset 0x02CD - SATA LED SATA LED indicating SATA controller activity. 0: disable, 1: enable $EN_DIS **/ UINT8 SataLedEnable; -/** Offset 0x02EE - VRAlert# Pin +/** Offset 0x02CE - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmVrAlert; -/** Offset 0x02EF - SLP_S0 VM Dynamic Control +/** Offset 0x02CF - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0VmRuntimeControl; -/** Offset 0x02F0 - SLP_S0 VM 0.70V Support +/** Offset 0x02D0 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm070VSupport; -/** Offset 0x02F1 - SLP_S0 VM 0.75V Support +/** Offset 0x02D1 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable $EN_DIS **/ UINT8 PchPmSlpS0Vm075VSupport; -/** Offset 0x02F2 - PCH PCIe root port connection type +/** Offset 0x02D2 - PCH PCIe root port connection type 0: built-in device, 1:slot **/ UINT8 PcieRpSlotImplemented[24]; -/** Offset 0x030A - Usage type for ClkSrc +/** Offset 0x02EA - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[16]; -/** Offset 0x031A - ClkReq-to-ClkSrc mapping +/** Offset 0x02FA - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[16]; -/** Offset 0x032A - PCIE RP Access Control Services Extended Capability +/** Offset 0x030A - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability **/ UINT8 PcieRpAcsEnabled[24]; -/** Offset 0x0342 - PCIE RP Clock Power Management +/** Offset 0x0322 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism **/ UINT8 PcieRpEnableCpm[24]; -/** Offset 0x035A - PCIE RP Detect Timeout Ms +/** Offset 0x033A - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port. **/ UINT16 PcieRpDetectTimeoutMs[24]; -/** Offset 0x038A - ModPHY SUS Power Domain Dynamic Gating +/** Offset 0x036A - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on PCH-H. 0: disable, 1: enable $EN_DIS **/ UINT8 PmcModPhySusPgEnable; -/** Offset 0x038B - SlpS0WithGbeSupport +/** Offset 0x036B - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping CPU and 1 for all other CPUs. 0: Disable, 1: Enable $EN_DIS **/ UINT8 SlpS0WithGbeSupport; -/** Offset 0x038C - Enable Power Optimizer +/** Offset 0x036C - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. $EN_DIS **/ UINT8 PchPwrOptEnable; -/** Offset 0x038D - PCH Flash Protection Ranges Write Enble +/** Offset 0x036D - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware. **/ UINT8 PchWriteProtectionEnable[5]; -/** Offset 0x0392 - PCH Flash Protection Ranges Read Enble +/** Offset 0x0372 - PCH Flash Protection Ranges Read Enble Read is blocked by hardware. **/ UINT8 PchReadProtectionEnable[5]; -/** Offset 0x0397 +/** Offset 0x0377 **/ - UINT8 UnusedUpdSpace15[1]; + UINT8 UnusedUpdSpace14[1]; -/** Offset 0x0398 - PCH Protect Range Limit +/** Offset 0x0378 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison. **/ UINT16 PchProtectedRangeLimit[5]; -/** Offset 0x03A2 - PCH Protect Range Base +/** Offset 0x0382 - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. **/ UINT16 PchProtectedRangeBase[5]; -/** Offset 0x03AC - Enable Pme +/** Offset 0x038C - Enable Pme Enable Azalia wake-on-ring. $EN_DIS **/ UINT8 PchHdaPme; -/** Offset 0x03AD - VC Type +/** Offset 0x038D - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. 0: VC0, 1: VC1 **/ UINT8 PchHdaVcType; -/** Offset 0x03AE - HD Audio Link Frequency +/** Offset 0x038E - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. 0: 6MHz, 1: 12MHz, 2: 24MHz **/ UINT8 PchHdaLinkFrequency; -/** Offset 0x03AF - iDisp-Link Frequency +/** Offset 0x038F - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x03B0 - iDisp-Link T-mode +/** Offset 0x0390 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. 0: 2T, 1: 1T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x03B1 - Universal Audio Architecture compliance for DSP enabled system +/** Offset 0x0391 - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). $EN_DIS **/ UINT8 PchHdaDspUaaCompliance; -/** Offset 0x03B2 - iDisplay Audio Codec disconnection +/** Offset 0x0392 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x03B3 - USB LFPS Filter selection +/** Offset 0x0393 - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns, 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns. **/ UINT8 PchUsbHsioFilterSel[10]; -/** Offset 0x03BD - Enable PCH Io Apic Entry 24-119 +/** Offset 0x039D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIoApicEntry24_119; -/** Offset 0x03BE - PCH Io Apic ID +/** Offset 0x039E - PCH Io Apic ID This member determines IOAPIC ID. Default is 0x02. **/ UINT8 PchIoApicId; -/** Offset 0x03BF - Enable PCH ISH SPI GPIO pins assigned +/** Offset 0x039F - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshSpiGpioAssign; -/** Offset 0x03C0 - Enable PCH ISH UART0 GPIO pins assigned +/** Offset 0x03A0 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart0GpioAssign; -/** Offset 0x03C1 - Enable PCH ISH UART1 GPIO pins assigned +/** Offset 0x03A1 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshUart1GpioAssign; -/** Offset 0x03C2 - Enable PCH ISH I2C0 GPIO pins assigned +/** Offset 0x03A2 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c0GpioAssign; -/** Offset 0x03C3 - Enable PCH ISH I2C1 GPIO pins assigned +/** Offset 0x03A3 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c1GpioAssign; -/** Offset 0x03C4 - Enable PCH ISH I2C2 GPIO pins assigned +/** Offset 0x03A4 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshI2c2GpioAssign; -/** Offset 0x03C5 - Enable PCH ISH GP_0 GPIO pin assigned +/** Offset 0x03A5 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp0GpioAssign; -/** Offset 0x03C6 - Enable PCH ISH GP_1 GPIO pin assigned +/** Offset 0x03A6 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp1GpioAssign; -/** Offset 0x03C7 - Enable PCH ISH GP_2 GPIO pin assigned +/** Offset 0x03A7 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp2GpioAssign; -/** Offset 0x03C8 - Enable PCH ISH GP_3 GPIO pin assigned +/** Offset 0x03A8 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp3GpioAssign; -/** Offset 0x03C9 - Enable PCH ISH GP_4 GPIO pin assigned +/** Offset 0x03A9 - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp4GpioAssign; -/** Offset 0x03CA - Enable PCH ISH GP_5 GPIO pin assigned +/** Offset 0x03AA - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp5GpioAssign; -/** Offset 0x03CB - Enable PCH ISH GP_6 GPIO pin assigned +/** Offset 0x03AB - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp6GpioAssign; -/** Offset 0x03CC - Enable PCH ISH GP_7 GPIO pin assigned +/** Offset 0x03AC - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchIshGp7GpioAssign; -/** Offset 0x03CD - PCH ISH PDT Unlock Msg +/** Offset 0x03AD - PCH ISH PDT Unlock Msg 0: False; 1: True. $EN_DIS **/ UINT8 PchIshPdtUnlock; -/** Offset 0x03CE - Enable PCH Lan LTR capabilty of PCH internal LAN +/** Offset 0x03AE - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PchLanLtrEnable; -/** Offset 0x03CF - Enable LOCKDOWN BIOS LOCK +/** Offset 0x03AF - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. $EN_DIS **/ UINT8 PchLockDownBiosLock; -/** Offset 0x03D0 - PCH Compatibility Revision ID +/** Offset 0x03B0 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. $EN_DIS **/ UINT8 PchCrid; -/** Offset 0x03D1 - RTC CMOS MEMORY LOCK +/** Offset 0x03B1 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. $EN_DIS **/ UINT8 PchLockDownRtcMemoryLock; -/** Offset 0x03D2 - Enable PCIE RP HotPlug +/** Offset 0x03B2 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available. **/ UINT8 PcieRpHotPlug[24]; -/** Offset 0x03EA - Enable PCIE RP Pm Sci +/** Offset 0x03CA - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled. **/ UINT8 PcieRpPmSci[24]; -/** Offset 0x0402 - Enable PCIE RP Ext Sync +/** Offset 0x03E2 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled. **/ UINT8 PcieRpExtSync[24]; -/** Offset 0x041A - Enable PCIE RP Transmitter Half Swing +/** Offset 0x03FA - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled. **/ UINT8 PcieRpTransmitterHalfSwing[24]; -/** Offset 0x0432 - Enable PCIE RP Clk Req Detect +/** Offset 0x0412 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management. **/ UINT8 PcieRpClkReqDetect[24]; -/** Offset 0x044A - PCIE RP Advanced Error Report +/** Offset 0x042A - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled. **/ UINT8 PcieRpAdvancedErrorReporting[24]; -/** Offset 0x0462 - PCIE RP Unsupported Request Report +/** Offset 0x0442 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled. **/ UINT8 PcieRpUnsupportedRequestReport[24]; -/** Offset 0x047A - PCIE RP Fatal Error Report +/** Offset 0x045A - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled. **/ UINT8 PcieRpFatalErrorReport[24]; -/** Offset 0x0492 - PCIE RP No Fatal Error Report +/** Offset 0x0472 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled. **/ UINT8 PcieRpNoFatalErrorReport[24]; -/** Offset 0x04AA - PCIE RP Correctable Error Report +/** Offset 0x048A - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled. **/ UINT8 PcieRpCorrectableErrorReport[24]; -/** Offset 0x04C2 - PCIE RP System Error On Fatal Error +/** Offset 0x04A2 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnFatalError[24]; -/** Offset 0x04DA - PCIE RP System Error On Non Fatal Error +/** Offset 0x04BA - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled. **/ UINT8 PcieRpSystemErrorOnNonFatalError[24]; -/** Offset 0x04F2 - PCIE RP System Error On Correctable Error +/** Offset 0x04D2 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled. **/ UINT8 PcieRpSystemErrorOnCorrectableError[24]; -/** Offset 0x050A - PCIE RP Max Payload +/** Offset 0x04EA - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. **/ UINT8 PcieRpMaxPayload[24]; -/** Offset 0x0522 - PCH USB3 RX HSIO Tuning parameters +/** Offset 0x0502 - PCH USB3 RX HSIO Tuning parameters Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset **/ UINT8 PchUsbHsioRxTuningParameters[10]; -/** Offset 0x052C - PCH USB3 HSIO Rx Tuning Enable +/** Offset 0x050C - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable, 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable **/ UINT8 PchUsbHsioRxTuningEnable[10]; -/** Offset 0x0536 - PCIE RP Pcie Speed +/** Offset 0x0516 - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED). **/ UINT8 PcieRpPcieSpeed[24]; -/** Offset 0x054E - PCIE RP Gen3 Equalization Phase Method +/** Offset 0x052E - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; 1: hardware equalization; 4: Fixed Coeficients. **/ UINT8 PcieRpGen3EqPh3Method[24]; -/** Offset 0x0566 - PCIE RP Physical Slot Number +/** Offset 0x0546 - PCIE RP Physical Slot Number Indicates the slot number for the root port. Default is the value as root port index. **/ UINT8 PcieRpPhysicalSlotNumber[24]; -/** Offset 0x057E - PCIE RP Completion Timeout +/** Offset 0x055E - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. **/ UINT8 PcieRpCompletionTimeout[24]; -/** Offset 0x0596 - PCIE RP Aspm +/** Offset 0x0576 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAspmAutoConfig. **/ UINT8 PcieRpAspm[24]; -/** Offset 0x05AE - PCIE RP L1 Substates +/** Offset 0x058E - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default is PchPcieL1SubstatesL1_1_2. **/ UINT8 PcieRpL1Substates[24]; -/** Offset 0x05C6 - PCIE RP Ltr Enable +/** Offset 0x05A6 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism. **/ UINT8 PcieRpLtrEnable[24]; -/** Offset 0x05DE - PCIE RP Ltr Config Lock +/** Offset 0x05BE - PCIE RP Ltr Config Lock 0: Disable; 1: Enable. **/ UINT8 PcieRpLtrConfigLock[24]; -/** Offset 0x05F6 - PCIE Eq Ph3 Lane Param Cm +/** Offset 0x05D6 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. **/ UINT8 PcieEqPh3LaneParamCm[24]; -/** Offset 0x060E - PCIE Eq Ph3 Lane Param Cp +/** Offset 0x05EE - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. **/ UINT8 PcieEqPh3LaneParamCp[24]; -/** Offset 0x0626 - PCIE Sw Eq CoeffList Cm +/** Offset 0x0606 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. Coefficient C-1. **/ UINT8 PcieSwEqCoeffListCm[5]; -/** Offset 0x062B - PCIE Sw Eq CoeffList Cp +/** Offset 0x060B - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. Coefficient C+1. **/ UINT8 PcieSwEqCoeffListCp[5]; -/** Offset 0x0630 - PCIE Disable RootPort Clock Gating +/** Offset 0x0610 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieDisableRootPortClockGating; -/** Offset 0x0631 - PCIE Enable Peer Memory Write +/** Offset 0x0611 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. $EN_DIS **/ UINT8 PcieEnablePeerMemoryWrite; -/** Offset 0x0632 - PCIE Compliance Test Mode +/** Offset 0x0612 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. $EN_DIS **/ UINT8 PcieComplianceTestMode; -/** Offset 0x0633 - PCIE Rp Function Swap +/** Offset 0x0613 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. $EN_DIS **/ UINT8 PcieRpFunctionSwap; -/** Offset 0x0634 - Teton Glacier Cycle Router +/** Offset 0x0614 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system **/ UINT8 TetonGlacierCR; -/** Offset 0x0635 - PCH Pm PME_B0_S5_DIS +/** Offset 0x0615 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. $EN_DIS **/ UINT8 PchPmPmeB0S5Dis; -/** Offset 0x0636 - PCIE IMR +/** Offset 0x0616 - PCIE IMR Enables Isolated Memory Region for PCIe. $EN_DIS **/ UINT8 PcieRpImrEnabled; -/** Offset 0x0637 - PCIE IMR port number +/** Offset 0x0617 - PCIE IMR port number Selects PCIE root port number for IMR feature. **/ UINT8 PcieRpImrSelection; -/** Offset 0x0638 - Teton Glacier Detection and Configuration Mode - Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Static - Configuration 2: Dynamic Configuration. Default is 0: Disabled - 0: Disabled, 1: Static Configuration, 2: Dynamic Configuration +/** Offset 0x0618 - Teton Glacier Detection and Configuration Mode + Enables support for Teton Glacier hybrid storage device. 0: Disabled; 1: Dynamic + Configuration. Default is 0: Disabled + 0: Disabled, 1: Dynamic Configuration **/ UINT8 TetonGlacierMode; -/** Offset 0x0639 - PCH Pm Wol Enable Override +/** Offset 0x0619 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. $EN_DIS **/ UINT8 PchPmWolEnableOverride; -/** Offset 0x063A - PCH Pm Pcie Wake From DeepSx +/** Offset 0x061A - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. $EN_DIS **/ UINT8 PchPmPcieWakeFromDeepSx; -/** Offset 0x063B - PCH Pm WoW lan Enable +/** Offset 0x061B - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanEnable; -/** Offset 0x063C - PCH Pm WoW lan DeepSx Enable +/** Offset 0x061C - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. $EN_DIS **/ UINT8 PchPmWoWlanDeepSxEnable; -/** Offset 0x063D - PCH Pm Lan Wake From DeepSx +/** Offset 0x061D - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. $EN_DIS **/ UINT8 PchPmLanWakeFromDeepSx; -/** Offset 0x063E - PCH Pm Deep Sx Pol +/** Offset 0x061E - PCH Pm Deep Sx Pol Deep Sx Policy. $EN_DIS **/ UINT8 PchPmDeepSxPol; -/** Offset 0x063F - PCH Pm Slp S3 Min Assert +/** Offset 0x061F - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. **/ UINT8 PchPmSlpS3MinAssert; -/** Offset 0x0640 - PCH Pm Slp S4 Min Assert +/** Offset 0x0620 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. **/ UINT8 PchPmSlpS4MinAssert; -/** Offset 0x0641 - PCH Pm Slp Sus Min Assert +/** Offset 0x0621 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. **/ UINT8 PchPmSlpSusMinAssert; -/** Offset 0x0642 - PCH Pm Slp A Min Assert +/** Offset 0x0622 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. **/ UINT8 PchPmSlpAMinAssert; -/** Offset 0x0643 - SLP_S0# Override +/** Offset 0x0623 - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion when debug is enabled. \n @@ -1787,7 +1791,7 @@ typedef struct { **/ UINT8 SlpS0Override; -/** Offset 0x0644 - S0ix Override Settings +/** Offset 0x0624 - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type. 'No Change' will keep PMC default settings. Or select the desired debug probe type for S0ix Override settings.\n @@ -1798,498 +1802,498 @@ typedef struct { **/ UINT8 SlpS0DisQForDebug; -/** Offset 0x0645 - USB Overcurrent Override for DbC +/** Offset 0x0625 - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. Enable when DbC is used to avoid signaling conflicts. $EN_DIS **/ UINT8 PchEnableDbcObs; -/** Offset 0x0646 - PCH Legacy IO Low Latency Enable +/** Offset 0x0626 - PCH Legacy IO Low Latency Enable Set to enable low latency of legacy IO. 0: Disable, 1: Enable $EN_DIS **/ UINT8 PchLegacyIoLowLatency; -/** Offset 0x0647 - PCH Pm Lpc Clock Run +/** Offset 0x0627 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. Default value is Disabled $EN_DIS **/ UINT8 PchPmLpcClockRun; -/** Offset 0x0648 - PCH Pm Slp Strch Sus Up +/** Offset 0x0628 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. $EN_DIS **/ UINT8 PchPmSlpStrchSusUp; -/** Offset 0x0649 - PCH Pm Slp Lan Low Dc +/** Offset 0x0629 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. $EN_DIS **/ UINT8 PchPmSlpLanLowDc; -/** Offset 0x064A - PCH Pm Pwr Btn Override Period +/** Offset 0x062A - PCH Pm Pwr Btn Override Period PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. **/ UINT8 PchPmPwrBtnOverridePeriod; -/** Offset 0x064B - PCH Pm Disable Dsx Ac Present Pulldown +/** Offset 0x062B - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. $EN_DIS **/ UINT8 PchPmDisableDsxAcPresentPulldown; -/** Offset 0x064C - PCH Pm Disable Native Power Button +/** Offset 0x062C - PCH Pm Disable Native Power Button Power button native mode disable. $EN_DIS **/ UINT8 PchPmDisableNativePowerButton; -/** Offset 0x064D - PCH Pm Slp S0 Enable +/** Offset 0x062D - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. $EN_DIS **/ UINT8 PchPmSlpS0Enable; -/** Offset 0x064E - PCH Pm ME_WAKE_STS +/** Offset 0x062E - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmMeWakeSts; -/** Offset 0x064F - PCH Pm WOL_OVR_WK_STS +/** Offset 0x062F - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. $EN_DIS **/ UINT8 PchPmWolOvrWkSts; -/** Offset 0x0650 - PCH Pm Reset Power Cycle Duration +/** Offset 0x0630 - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. Please refer to EDS for all support settings. 0 is default, 1 is 1 second, 2 is 2 seconds, ... **/ UINT8 PchPmPwrCycDur; -/** Offset 0x0651 - PCH Pm Pcie Pll Ssc +/** Offset 0x0631 - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No BIOS override. **/ UINT8 PchPmPciePllSsc; -/** Offset 0x0652 - PCH Sata Pwr Opt Enable +/** Offset 0x0632 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x0653 - PCH Sata eSATA Speed Limit +/** Offset 0x0633 - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. $EN_DIS **/ UINT8 EsataSpeedLimit; -/** Offset 0x0654 - PCH Sata Speed Limit +/** Offset 0x0634 - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. **/ UINT8 SataSpeedLimit; -/** Offset 0x0655 - Enable SATA Port HotPlug +/** Offset 0x0635 - Enable SATA Port HotPlug Enable SATA Port HotPlug. **/ UINT8 SataPortsHotPlug[8]; -/** Offset 0x065D - Enable SATA Port Interlock Sw +/** Offset 0x063D - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw. **/ UINT8 SataPortsInterlockSw[8]; -/** Offset 0x0665 - Enable SATA Port External +/** Offset 0x0645 - Enable SATA Port External Enable SATA Port External. **/ UINT8 SataPortsExternal[8]; -/** Offset 0x066D - Enable SATA Port SpinUp +/** Offset 0x064D - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device. **/ UINT8 SataPortsSpinUp[8]; -/** Offset 0x0675 - Enable SATA Port Solid State Drive +/** Offset 0x0655 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD. **/ UINT8 SataPortsSolidStateDrive[8]; -/** Offset 0x067D - Enable SATA Port Enable Dito Config +/** Offset 0x065D - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). **/ UINT8 SataPortsEnableDitoConfig[8]; -/** Offset 0x0685 - Enable SATA Port DmVal +/** Offset 0x0665 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x068D +/** Offset 0x066D **/ - UINT8 UnusedUpdSpace16[1]; + UINT8 UnusedUpdSpace15[1]; -/** Offset 0x068E - Enable SATA Port DmVal +/** Offset 0x066E - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x069E - Enable SATA Port ZpOdd +/** Offset 0x067E - Enable SATA Port ZpOdd Support zero power ODD. **/ UINT8 SataPortsZpOdd[8]; -/** Offset 0x06A6 - PCH Sata Rst Raid Device Id +/** Offset 0x0686 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. 0:Client, 1:Alternate, 2:Server **/ UINT8 SataRstRaidDeviceId; -/** Offset 0x06A7 - PCH Sata Rst Raid0 +/** Offset 0x0687 - PCH Sata Rst Raid0 RAID0. $EN_DIS **/ UINT8 SataRstRaid0; -/** Offset 0x06A8 - PCH Sata Rst Raid1 +/** Offset 0x0688 - PCH Sata Rst Raid1 RAID1. $EN_DIS **/ UINT8 SataRstRaid1; -/** Offset 0x06A9 - PCH Sata Rst Raid10 +/** Offset 0x0689 - PCH Sata Rst Raid10 RAID10. $EN_DIS **/ UINT8 SataRstRaid10; -/** Offset 0x06AA - PCH Sata Rst Raid5 +/** Offset 0x068A - PCH Sata Rst Raid5 RAID5. $EN_DIS **/ UINT8 SataRstRaid5; -/** Offset 0x06AB - PCH Sata Rst Irrt +/** Offset 0x068B - PCH Sata Rst Irrt Intel Rapid Recovery Technology. $EN_DIS **/ UINT8 SataRstIrrt; -/** Offset 0x06AC - PCH Sata Rst Orom Ui Banner +/** Offset 0x068C - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. $EN_DIS **/ UINT8 SataRstOromUiBanner; -/** Offset 0x06AD - PCH Sata Rst Orom Ui Delay +/** Offset 0x068D - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). **/ UINT8 SataRstOromUiDelay; -/** Offset 0x06AE - PCH Sata Rst Hdd Unlock +/** Offset 0x068E - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. $EN_DIS **/ UINT8 SataRstHddUnlock; -/** Offset 0x06AF - PCH Sata Rst Led Locate +/** Offset 0x068F - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. $EN_DIS **/ UINT8 SataRstLedLocate; -/** Offset 0x06B0 - PCH Sata Rst Irrt Only +/** Offset 0x0690 - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. $EN_DIS **/ UINT8 SataRstIrrtOnly; -/** Offset 0x06B1 - PCH Sata Rst Smart Storage +/** Offset 0x0691 - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. $EN_DIS **/ UINT8 SataRstSmartStorage; -/** Offset 0x06B2 - PCH Sata Rst Pcie Storage Remap enable +/** Offset 0x0692 - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping. **/ UINT8 SataRstPcieEnable[3]; -/** Offset 0x06B5 - PCH Sata Rst Pcie Storage Port +/** Offset 0x0695 - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). **/ UINT8 SataRstPcieStoragePort[3]; -/** Offset 0x06B8 - PCH Sata Rst Pcie Device Reset Delay +/** Offset 0x0698 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms **/ UINT8 SataRstPcieDeviceResetDelay[3]; -/** Offset 0x06BB - Enable eMMC HS400 Training +/** Offset 0x069B - Enable eMMC HS400 Training Deprecated. $EN_DIS **/ UINT8 PchScsEmmcHs400TuningRequired; -/** Offset 0x06BC - Set HS400 Tuning Data Valid +/** Offset 0x069C - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. $EN_DIS **/ UINT8 PchScsEmmcHs400DllDataValid; -/** Offset 0x06BD - Rx Strobe Delay Control +/** Offset 0x069D - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). **/ UINT8 PchScsEmmcHs400RxStrobeDll1; -/** Offset 0x06BE - Tx Data Delay Control +/** Offset 0x069E - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). **/ UINT8 PchScsEmmcHs400TxDataDll; -/** Offset 0x06BF - I/O Driver Strength +/** Offset 0x069F - I/O Driver Strength Deprecated. 0:33 Ohm, 1:40 Ohm, 2:50 Ohm **/ UINT8 PchScsEmmcHs400DriverStrength; -/** Offset 0x06C0 - Enable Serial IRQ +/** Offset 0x06A0 - Enable Serial IRQ Determines if enable Serial IRQ. $EN_DIS **/ UINT8 PchSirqEnable; -/** Offset 0x06C1 - Serial IRQ Mode Select +/** Offset 0x06A1 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. $EN_DIS **/ UINT8 PchSirqMode; -/** Offset 0x06C2 - Start Frame Pulse Width +/** Offset 0x06A2 - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk **/ UINT8 PchStartFramePulse; -/** Offset 0x06C3 - Reserved +/** Offset 0x06A3 - Reserved Reserved $EN_DIS **/ UINT8 ReservedForFuture1; -/** Offset 0x06C4 - Thermal Device SMI Enable +/** Offset 0x06A4 - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. $EN_DIS **/ UINT8 PchTsmicLock; -/** Offset 0x06C5 +/** Offset 0x06A5 **/ - UINT8 UnusedUpdSpace17; + UINT8 UnusedUpdSpace16; -/** Offset 0x06C6 - Thermal Throttling Custimized T0Level Value +/** Offset 0x06A6 - Thermal Throttling Custimized T0Level Value Custimized T0Level value. **/ UINT16 PchT0Level; -/** Offset 0x06C8 - Thermal Throttling Custimized T1Level Value +/** Offset 0x06A8 - Thermal Throttling Custimized T1Level Value Custimized T1Level value. **/ UINT16 PchT1Level; -/** Offset 0x06CA - Thermal Throttling Custimized T2Level Value +/** Offset 0x06AA - Thermal Throttling Custimized T2Level Value Custimized T2Level value. **/ UINT16 PchT2Level; -/** Offset 0x06CC - Enable The Thermal Throttle +/** Offset 0x06AC - Enable The Thermal Throttle Enable the thermal throttle function. $EN_DIS **/ UINT8 PchTTEnable; -/** Offset 0x06CD - PMSync State 13 +/** Offset 0x06AD - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. $EN_DIS **/ UINT8 PchTTState13Enable; -/** Offset 0x06CE - Thermal Throttle Lock +/** Offset 0x06AE - Thermal Throttle Lock Thermal Throttle Lock. $EN_DIS **/ UINT8 PchTTLock; -/** Offset 0x06CF - Thermal Throttling Suggested Setting +/** Offset 0x06AF - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 TTSuggestedSetting; -/** Offset 0x06D0 - Enable PCH Cross Throttling +/** Offset 0x06B0 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS **/ UINT8 TTCrossThrottling; -/** Offset 0x06D1 - DMI Thermal Sensor Autonomous Width Enable +/** Offset 0x06B1 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. $EN_DIS **/ UINT8 PchDmiTsawEn; -/** Offset 0x06D2 - DMI Thermal Sensor Suggested Setting +/** Offset 0x06B2 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. $EN_DIS **/ UINT8 DmiSuggestedSetting; -/** Offset 0x06D3 - Thermal Sensor 0 Target Width +/** Offset 0x06B3 - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS0TW; -/** Offset 0x06D4 - Thermal Sensor 1 Target Width +/** Offset 0x06B4 - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS1TW; -/** Offset 0x06D5 - Thermal Sensor 2 Target Width +/** Offset 0x06B5 - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS2TW; -/** Offset 0x06D6 - Thermal Sensor 3 Target Width +/** Offset 0x06B6 - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 **/ UINT8 DmiTS3TW; -/** Offset 0x06D7 - Port 0 T1 Multipler +/** Offset 0x06B7 - Port 0 T1 Multipler Port 0 T1 Multipler. **/ UINT8 SataP0T1M; -/** Offset 0x06D8 - Port 0 T2 Multipler +/** Offset 0x06B8 - Port 0 T2 Multipler Port 0 T2 Multipler. **/ UINT8 SataP0T2M; -/** Offset 0x06D9 - Port 0 T3 Multipler +/** Offset 0x06B9 - Port 0 T3 Multipler Port 0 T3 Multipler. **/ UINT8 SataP0T3M; -/** Offset 0x06DA - Port 0 Tdispatch +/** Offset 0x06BA - Port 0 Tdispatch Port 0 Tdispatch. **/ UINT8 SataP0TDisp; -/** Offset 0x06DB - Port 1 T1 Multipler +/** Offset 0x06BB - Port 1 T1 Multipler Port 1 T1 Multipler. **/ UINT8 SataP1T1M; -/** Offset 0x06DC - Port 1 T2 Multipler +/** Offset 0x06BC - Port 1 T2 Multipler Port 1 T2 Multipler. **/ UINT8 SataP1T2M; -/** Offset 0x06DD - Port 1 T3 Multipler +/** Offset 0x06BD - Port 1 T3 Multipler Port 1 T3 Multipler. **/ UINT8 SataP1T3M; -/** Offset 0x06DE - Port 1 Tdispatch +/** Offset 0x06BE - Port 1 Tdispatch Port 1 Tdispatch. **/ UINT8 SataP1TDisp; -/** Offset 0x06DF - Port 0 Tinactive +/** Offset 0x06BF - Port 0 Tinactive Port 0 Tinactive. **/ UINT8 SataP0Tinact; -/** Offset 0x06E0 - Port 0 Alternate Fast Init Tdispatch +/** Offset 0x06C0 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP0TDispFinit; -/** Offset 0x06E1 - Port 1 Tinactive +/** Offset 0x06C1 - Port 1 Tinactive Port 1 Tinactive. **/ UINT8 SataP1Tinact; -/** Offset 0x06E2 - Port 1 Alternate Fast Init Tdispatch +/** Offset 0x06C2 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. $EN_DIS **/ UINT8 SataP1TDispFinit; -/** Offset 0x06E3 - Sata Thermal Throttling Suggested Setting +/** Offset 0x06C3 - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. $EN_DIS **/ UINT8 SataThermalSuggestedSetting; -/** Offset 0x06E4 - Enable Memory Thermal Throttling +/** Offset 0x06C4 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. $EN_DIS **/ UINT8 PchMemoryThrottlingEnable; -/** Offset 0x06E5 - Memory Thermal Throttling +/** Offset 0x06C5 - Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPmsyncEnable[2]; -/** Offset 0x06E7 - Enable Memory Thermal Throttling +/** Offset 0x06C7 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryC0TransmitEnable[2]; -/** Offset 0x06E9 - Enable Memory Thermal Throttling +/** Offset 0x06C9 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. **/ UINT8 PchMemoryPinSelection[2]; -/** Offset 0x06EB +/** Offset 0x06CB **/ - UINT8 UnusedUpdSpace18; + UINT8 UnusedUpdSpace17; -/** Offset 0x06EC - Thermal Device Temperature +/** Offset 0x06CC - Thermal Device Temperature Decides the temperature. **/ UINT16 PchTemperatureHotLevel; -/** Offset 0x06EE - Enable xHCI Compliance Mode +/** Offset 0x06CE - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default. $EN_DIS **/ UINT8 PchEnableComplianceMode; -/** Offset 0x06EF - USB2 Port Over Current Pin +/** Offset 0x06CF - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x06FF - USB3 Port Over Current Pin +/** Offset 0x06DF - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0709 - Enable 8254 Static Clock Gating +/** Offset 0x06E9 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support boot legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -2297,19 +2301,19 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x070A - PCH Sata Rst Optane Memory +/** Offset 0x06EA - PCH Sata Rst Optane Memory Optane Memory $EN_DIS **/ UINT8 SataRstOptaneMemory; -/** Offset 0x070B - PCH Sata Rst CPU Attached Storage +/** Offset 0x06EB - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS **/ UINT8 SataRstCpuAttachedStorage; -/** Offset 0x070C - Enable 8254 Static Clock Gating On S3 +/** Offset 0x06EC - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -2317,11 +2321,11 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x070D +/** Offset 0x06ED **/ - UINT8 UnusedUpdSpace19[3]; + UINT8 UnusedUpdSpace18[3]; -/** Offset 0x0710 - Pch PCIE device override table pointer +/** Offset 0x06F0 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. This is a pointer points to a 32bit address. And it's only used in PostMem phase. Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId @@ -2329,7 +2333,7 @@ typedef struct { **/ UINT32 PchPcieDeviceOverrideTablePtr; -/** Offset 0x0714 - Enable TCO timer. +/** Offset 0x06F4 - Enable TCO timer. When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer emulation must be enabled, and WDAT table must not be exposed to the OS. @@ -2337,7 +2341,7 @@ typedef struct { **/ UINT8 EnableTcoTimer; -/** Offset 0x0715 - Enable PS_ON. +/** Offset 0x06F5 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -2345,107 +2349,155 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0716 - Pmc Cpu C10 Gate Pin Enable +/** Offset 0x06F6 - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. $EN_DIS **/ UINT8 PmcCpuC10GatePinEnable; -/** Offset 0x0717 - Pch Dmi Aspm Ctrl +/** Offset 0x06F7 - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto **/ UINT8 PchDmiAspmCtrl; -/** Offset 0x0718 - ReservedPchPostMem +/** Offset 0x06F8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTranEnable[10]; + +/** Offset 0x0702 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3 + USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], Default + = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate3UniqTran[10]; + +/** Offset 0x070C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTranEnable[10]; + +/** Offset 0x0716 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2 + USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate2UniqTran[10]; + +/** Offset 0x0720 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTranEnable[10]; + +/** Offset 0x072A - USB 3.0 TX Output Unique Transition Bit Scale for rate 1 + USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate1UniqTran[10]; + +/** Offset 0x0734 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0 + Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each + value in array can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTranEnable[10]; + +/** Offset 0x073E - USB 3.0 TX Output Unique Transition Bit Scale for rate 0 + USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24], + Default = 4Ch. One byte for each port. +**/ + UINT8 Usb3HsioTxRate0UniqTran[10]; + +/** Offset 0x0748 - ReservedPchPostMem Reserved for Pch Post-Mem $EN_DIS **/ UINT8 ReservedPchPostMem[16]; -/** Offset 0x0728 - BgpdtHash[4] +/** Offset 0x0758 - BgpdtHash[4] BgpdtHash values **/ UINT64 BgpdtHash[4]; -/** Offset 0x0748 - BiosGuardAttr +/** Offset 0x0778 - BiosGuardAttr BiosGuardAttr default values **/ UINT32 BiosGuardAttr; -/** Offset 0x074C +/** Offset 0x077C **/ - UINT8 UnusedUpdSpace20[4]; + UINT8 UnusedUpdSpace19[4]; -/** Offset 0x0750 - BiosGuardModulePtr +/** Offset 0x0780 - BiosGuardModulePtr BiosGuardModulePtr default values **/ UINT64 BiosGuardModulePtr; -/** Offset 0x0758 - SendEcCmd +/** Offset 0x0788 - SendEcCmd SendEcCmd function pointer. \n @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode **/ UINT64 SendEcCmd; -/** Offset 0x0760 - EcCmdProvisionEav +/** Offset 0x0790 - EcCmdProvisionEav Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC **/ UINT8 EcCmdProvisionEav; -/** Offset 0x0761 - EcCmdLock +/** Offset 0x0791 - EcCmdLock EcCmdLock default values. Locks Ephemeral Authorization Value sent previously **/ UINT8 EcCmdLock; -/** Offset 0x0762 +/** Offset 0x0792 **/ - UINT8 UnusedUpdSpace21[6]; + UINT8 UnusedUpdSpace20[6]; -/** Offset 0x0768 - SgxEpoch0 +/** Offset 0x0798 - SgxEpoch0 SgxEpoch0 default values **/ UINT64 SgxEpoch0; -/** Offset 0x0770 - SgxEpoch1 +/** Offset 0x07A0 - SgxEpoch1 SgxEpoch1 default values **/ UINT64 SgxEpoch1; -/** Offset 0x0778 - SgxSinitNvsData +/** Offset 0x07A8 - SgxSinitNvsData SgxSinitNvsData default values **/ UINT8 SgxSinitNvsData; -/** Offset 0x0779 - Si Config CSM Flag. +/** Offset 0x07A9 - Si Config CSM Flag. Platform specific common policies that used by several silicon components. CSM status flag. $EN_DIS **/ UINT8 SiCsmFlag; -/** Offset 0x077A +/** Offset 0x07AA **/ - UINT8 UnusedUpdSpace22[2]; + UINT8 UnusedUpdSpace21[2]; -/** Offset 0x077C - SVID SDID table Poniter. +/** Offset 0x07AC - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. **/ UINT32 SiSsidTablePtr; -/** Offset 0x0780 - Number of ssid table. +/** Offset 0x07B0 - Number of ssid table. SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. **/ UINT16 SiNumberOfSsidTableEntry; -/** Offset 0x0782 - SATA RST Interrupt Mode +/** Offset 0x07B2 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. 0:Msix, 1:Msi, 2:Legacy **/ UINT8 SataRstInterrupt; -/** Offset 0x0783 - ME Unconfig on RTC clear +/** Offset 0x07B3 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. 2: Cmos is clear, status unkonwn. 3: Reserved 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos @@ -2453,11 +2505,11 @@ typedef struct { **/ UINT8 MeUnconfigOnRtcClear; -/** Offset 0x0784 +/** Offset 0x07B4 **/ - UINT8 UnusedUpdSpace23[3]; + UINT8 UnusedUpdSpace22[3]; -/** Offset 0x0787 +/** Offset 0x07B7 **/ UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; @@ -2466,74 +2518,74 @@ typedef struct { **/ typedef struct { -/** Offset 0x0788 +/** Offset 0x07B8 **/ UINT32 Signature; -/** Offset 0x078C - Enable/Disable Device 7 +/** Offset 0x07BC - Enable/Disable Device 7 Enable: Device 7 enabled, Disable (Default): Device 7 disabled $EN_DIS **/ UINT8 ChapDeviceEnable; -/** Offset 0x078D - Skip PAM register lock +/** Offset 0x07BD - Skip PAM register lock Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC $EN_DIS **/ UINT8 SkipPamLock; -/** Offset 0x078E - EDRAM Test Mode +/** Offset 0x07BE - EDRAM Test Mode Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): PAM registers will be locked by RC 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode **/ UINT8 EdramTestMode; -/** Offset 0x078F - DMI Extended Sync Control +/** Offset 0x07BF - DMI Extended Sync Control Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended Sync Control $EN_DIS **/ UINT8 DmiExtSync; -/** Offset 0x0790 - DMI IOT Control +/** Offset 0x07C0 - DMI IOT Control Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control $EN_DIS **/ UINT8 DmiIot; -/** Offset 0x0791 - PEG Max Payload size per root port +/** Offset 0x07C1 - PEG Max Payload size per root port 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B **/ UINT8 PegMaxPayload[4]; -/** Offset 0x0795 - Enable/Disable IGFX RenderStandby +/** Offset 0x07C5 - Enable/Disable IGFX RenderStandby Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby $EN_DIS **/ UINT8 RenderStandby; -/** Offset 0x0796 - Enable/Disable IGFX PmSupport +/** Offset 0x07C6 - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0797 - Enable/Disable CdynmaxClamp +/** Offset 0x07C7 - Enable/Disable CdynmaxClamp Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp $EN_DIS **/ UINT8 CdynmaxClampEnable; -/** Offset 0x0798 - Disable VT-d +/** Offset 0x07C8 - Disable VT-d 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) $EN_DIS **/ UINT8 VtdDisableDeprecated; -/** Offset 0x0799 - GT Frequency Limit +/** Offset 0x07C9 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -2547,19 +2599,19 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x079A - Disable Turbo GT +/** Offset 0x07CA - Disable Turbo GT 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency $EN_DIS **/ UINT8 DisableTurboGt; -/** Offset 0x079B - SaPostMemTestRsvd +/** Offset 0x07CB - SaPostMemTestRsvd Reserved for SA Post-Mem Test $EN_DIS **/ UINT8 SaPostMemTestRsvd[11]; -/** Offset 0x07A6 - 1-Core Ratio Limit +/** Offset 0x07D6 - 1-Core Ratio Limit 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit, @@ -2567,79 +2619,79 @@ typedef struct { **/ UINT8 OneCoreRatioLimit; -/** Offset 0x07A7 - 2-Core Ratio Limit +/** Offset 0x07D7 - 2-Core Ratio Limit 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 TwoCoreRatioLimit; -/** Offset 0x07A8 - 3-Core Ratio Limit +/** Offset 0x07D8 - 3-Core Ratio Limit 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 ThreeCoreRatioLimit; -/** Offset 0x07A9 - 4-Core Ratio Limit +/** Offset 0x07D9 - 4-Core Ratio Limit 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 **/ UINT8 FourCoreRatioLimit; -/** Offset 0x07AA - Enable or Disable HWP +/** Offset 0x07DA - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x07AB - Hardware Duty Cycle Control +/** Offset 0x07DB - Hardware Duty Cycle Control Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved $EN_DIS **/ UINT8 HdcControl; -/** Offset 0x07AC - Package Long duration turbo mode time +/** Offset 0x07DC - Package Long duration turbo mode time Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PowerLimit1Time; -/** Offset 0x07AD - Short Duration Turbo Mode +/** Offset 0x07DD - Short Duration Turbo Mode Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable $EN_DIS **/ UINT8 PowerLimit2; -/** Offset 0x07AE - Turbo settings Lock +/** Offset 0x07DE - Turbo settings Lock Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable $EN_DIS **/ UINT8 TurboPowerLimitLock; -/** Offset 0x07AF - Package PL3 time window +/** Offset 0x07DF - Package PL3 time window Package PL3 time window range for this policy from 0 to 64ms **/ UINT8 PowerLimit3Time; -/** Offset 0x07B0 - Package PL3 Duty Cycle +/** Offset 0x07E0 - Package PL3 Duty Cycle Package PL3 Duty Cycle; Valid Range is 0 to 100 **/ UINT8 PowerLimit3DutyCycle; -/** Offset 0x07B1 - Package PL3 Lock +/** Offset 0x07E1 - Package PL3 Lock Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit3Lock; -/** Offset 0x07B2 - Package PL4 Lock +/** Offset 0x07E2 - Package PL4 Lock Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable $EN_DIS **/ UINT8 PowerLimit4Lock; -/** Offset 0x07B3 - TCC Activation Offset +/** Offset 0x07E3 - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For Y SKU, the recommended default for this policy is 15, @@ -2647,7 +2699,7 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x07B4 - Tcc Offset Clamp Enable/Disable +/** Offset 0x07E4 - Tcc Offset Clamp Enable/Disable Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle below P1.For Y SKU, the recommended default for this policy is 1: Enabled, For all other SKUs the recommended default are 0: Disabled. @@ -2655,345 +2707,345 @@ typedef struct { **/ UINT8 TccOffsetClamp; -/** Offset 0x07B5 - Tcc Offset Lock +/** Offset 0x07E5 - Tcc Offset Lock Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature target; 0: Disabled; 1: Enabled. $EN_DIS **/ UINT8 TccOffsetLock; -/** Offset 0x07B6 - Custom Ratio State Entries +/** Offset 0x07E6 - Custom Ratio State Entries The number of custom ratio state entries, ranges from 0 to 40 for a valid custom ratio table.Sets the number of custom P-states. At least 2 states must be present **/ UINT8 NumberOfEntries; -/** Offset 0x07B7 - Custom Short term Power Limit time window +/** Offset 0x07E7 - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom1PowerLimit1Time; -/** Offset 0x07B8 - Custom Turbo Activation Ratio +/** Offset 0x07E8 - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 **/ UINT8 Custom1TurboActivationRatio; -/** Offset 0x07B9 - Custom Config Tdp Control +/** Offset 0x07E9 - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom1ConfigTdpControl; -/** Offset 0x07BA - Custom Short term Power Limit time window +/** Offset 0x07EA - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom2PowerLimit1Time; -/** Offset 0x07BB - Custom Turbo Activation Ratio +/** Offset 0x07EB - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 **/ UINT8 Custom2TurboActivationRatio; -/** Offset 0x07BC - Custom Config Tdp Control +/** Offset 0x07EC - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom2ConfigTdpControl; -/** Offset 0x07BD - Custom Short term Power Limit time window +/** Offset 0x07ED - Custom Short term Power Limit time window Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128, 0 = AUTO **/ UINT8 Custom3PowerLimit1Time; -/** Offset 0x07BE - Custom Turbo Activation Ratio +/** Offset 0x07EE - Custom Turbo Activation Ratio Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 **/ UINT8 Custom3TurboActivationRatio; -/** Offset 0x07BF - Custom Config Tdp Control +/** Offset 0x07EF - Custom Config Tdp Control Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2 **/ UINT8 Custom3ConfigTdpControl; -/** Offset 0x07C0 - ConfigTdp mode settings Lock +/** Offset 0x07F0 - ConfigTdp mode settings Lock Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ConfigTdpLock; -/** Offset 0x07C1 - Load Configurable TDP SSDT +/** Offset 0x07F1 - Load Configurable TDP SSDT Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ConfigTdpBios; -/** Offset 0x07C2 - PL1 Enable value +/** Offset 0x07F2 - PL1 Enable value PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit1; -/** Offset 0x07C3 - PL1 timewindow +/** Offset 0x07F3 - PL1 timewindow PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 **/ UINT8 PsysPowerLimit1Time; -/** Offset 0x07C4 - PL2 Enable Value +/** Offset 0x07F4 - PL2 Enable Value PL2 Enable activates the PL2 value to limit average platform power.0: Disable; 1: Enable. $EN_DIS **/ UINT8 PsysPowerLimit2; -/** Offset 0x07C5 - Enable or Disable MLC Streamer Prefetcher +/** Offset 0x07F5 - Enable or Disable MLC Streamer Prefetcher Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MlcStreamerPrefetcher; -/** Offset 0x07C6 - Enable or Disable MLC Spatial Prefetcher +/** Offset 0x07F6 - Enable or Disable MLC Spatial Prefetcher Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable $EN_DIS **/ UINT8 MlcSpatialPrefetcher; -/** Offset 0x07C7 - Enable or Disable Monitor /MWAIT instructions +/** Offset 0x07F7 - Enable or Disable Monitor /MWAIT instructions Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MonitorMwaitEnable; -/** Offset 0x07C8 - Enable or Disable initialization of machine check registers +/** Offset 0x07F8 - Enable or Disable initialization of machine check registers Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MachineCheckEnable; -/** Offset 0x07C9 - Deprecated DO NOT USE Enable or Disable processor debug features +/** Offset 0x07F9 - Deprecated DO NOT USE Enable or Disable processor debug features @deprecated Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceEnable; -/** Offset 0x07CA - Lock or Unlock debug interface features +/** Offset 0x07FA - Lock or Unlock debug interface features Lock or Unlock debug interface features; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DebugInterfaceLockEnable; -/** Offset 0x07CB - AP Idle Manner of waiting for SIPI +/** Offset 0x07FB - AP Idle Manner of waiting for SIPI AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. 1: HALT loop, 2: MWAIT loop, 3: RUN loop **/ UINT8 ApIdleManner; -/** Offset 0x07CC - Control on Processor Trace output scheme +/** Offset 0x07FC - Control on Processor Trace output scheme Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. 0: Single Range Output, 1: ToPA Output **/ UINT8 ProcessorTraceOutputScheme; -/** Offset 0x07CD - Enable or Disable Processor Trace feature +/** Offset 0x07FD - Enable or Disable Processor Trace feature Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcessorTraceEnable; -/** Offset 0x07CE +/** Offset 0x07FE **/ - UINT8 UnusedUpdSpace24[2]; + UINT8 UnusedUpdSpace23[2]; -/** Offset 0x07D0 - Base of memory region allocated for Processor Trace +/** Offset 0x0800 - Base of memory region allocated for Processor Trace Base address of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT64 ProcessorTraceMemBase; -/** Offset 0x07D8 - Memory region allocation for Processor Trace +/** Offset 0x0808 - Memory region allocation for Processor Trace Length in bytes of memory region allocated for Processor Trace. Processor Trace requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable **/ UINT32 ProcessorTraceMemLength; -/** Offset 0x07DC - Enable or Disable Voltage Optimization feature +/** Offset 0x080C - Enable or Disable Voltage Optimization feature Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable $EN_DIS **/ UINT8 VoltageOptimization; -/** Offset 0x07DD - Enable or Disable Intel SpeedStep Technology +/** Offset 0x080D - Enable or Disable Intel SpeedStep Technology Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable $EN_DIS **/ UINT8 Eist; -/** Offset 0x07DE - Enable or Disable Energy Efficient P-state +/** Offset 0x080E - Enable or Disable Energy Efficient P-state Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientPState; -/** Offset 0x07DF - Enable or Disable Energy Efficient Turbo +/** Offset 0x080F - Enable or Disable Energy Efficient Turbo Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; 1: Enable $EN_DIS **/ UINT8 EnergyEfficientTurbo; -/** Offset 0x07E0 - Enable or Disable T states +/** Offset 0x0810 - Enable or Disable T states Enable or Disable T states; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TStates; -/** Offset 0x07E1 - Enable or Disable Bi-Directional PROCHOT# +/** Offset 0x0811 - Enable or Disable Bi-Directional PROCHOT# Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable $EN_DIS **/ UINT8 BiProcHot; -/** Offset 0x07E2 - Enable or Disable PROCHOT# signal being driven externally +/** Offset 0x0812 - Enable or Disable PROCHOT# signal being driven externally Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableProcHotOut; -/** Offset 0x07E3 - Enable or Disable PROCHOT# Response +/** Offset 0x0813 - Enable or Disable PROCHOT# Response Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 ProcHotResponse; -/** Offset 0x07E4 - Enable or Disable VR Thermal Alert +/** Offset 0x0814 - Enable or Disable VR Thermal Alert Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 DisableVrThermalAlert; -/** Offset 0x07E5 - Enable or Disable Thermal Reporting +/** Offset 0x0815 - Enable or Disable Thermal Reporting Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 AutoThermalReporting; -/** Offset 0x07E6 - Enable or Disable Thermal Monitor +/** Offset 0x0816 - Enable or Disable Thermal Monitor Enable or Disable Thermal Monitor; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ThermalMonitor; -/** Offset 0x07E7 - Enable or Disable CPU power states (C-states) +/** Offset 0x0817 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x07E8 - Configure C-State Configuration Lock +/** Offset 0x0818 - Configure C-State Configuration Lock Configure C-State Configuration Lock; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PmgCstCfgCtrlLock; -/** Offset 0x07E9 - Enable or Disable Enhanced C-states +/** Offset 0x0819 - Enable or Disable Enhanced C-states Enable or Disable Enhanced C-states. 0: Disable; 1: Enable $EN_DIS **/ UINT8 C1e; -/** Offset 0x07EA - Enable or Disable Package Cstate Demotion +/** Offset 0x081A - Enable or Disable Package Cstate Demotion Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateDemotion; -/** Offset 0x07EB - Enable or Disable Package Cstate UnDemotion +/** Offset 0x081B - Enable or Disable Package Cstate UnDemotion Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable $EN_DIS **/ UINT8 PkgCStateUnDemotion; -/** Offset 0x07EC - Enable or Disable CState-Pre wake +/** Offset 0x081C - Enable or Disable CState-Pre wake Enable or Disable CState-Pre wake. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CStatePreWake; -/** Offset 0x07ED - Enable or Disable TimedMwait Support. +/** Offset 0x081D - Enable or Disable TimedMwait Support. Enable or Disable TimedMwait Support. 0: Disable; 1: Enable $EN_DIS **/ UINT8 TimedMwait; -/** Offset 0x07EE - Enable or Disable IO to MWAIT redirection +/** Offset 0x081E - Enable or Disable IO to MWAIT redirection Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 CstCfgCtrIoMwaitRedirection; -/** Offset 0x07EF - Set the Max Pkg Cstate +/** Offset 0x081F - Set the Max Pkg Cstate Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto **/ UINT8 PkgCStateLimit; -/** Offset 0x07F0 - TimeUnit for C-State Latency Control0 +/** Offset 0x0820 - TimeUnit for C-State Latency Control0 TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl0TimeUnit; -/** Offset 0x07F1 - TimeUnit for C-State Latency Control1 +/** Offset 0x0821 - TimeUnit for C-State Latency Control1 TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl1TimeUnit; -/** Offset 0x07F2 - TimeUnit for C-State Latency Control2 +/** Offset 0x0822 - TimeUnit for C-State Latency Control2 TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl2TimeUnit; -/** Offset 0x07F3 - TimeUnit for C-State Latency Control3 +/** Offset 0x0823 - TimeUnit for C-State Latency Control3 TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl3TimeUnit; -/** Offset 0x07F4 - TimeUnit for C-State Latency Control4 +/** Offset 0x0824 - TimeUnit for C-State Latency Control4 Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl4TimeUnit; -/** Offset 0x07F5 - TimeUnit for C-State Latency Control5 +/** Offset 0x0825 - TimeUnit for C-State Latency Control5 TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns **/ UINT8 CstateLatencyControl5TimeUnit; -/** Offset 0x07F6 - Interrupt Redirection Mode Select +/** Offset 0x0826 - Interrupt Redirection Mode Select Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4: PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change. **/ UINT8 PpmIrmSetting; -/** Offset 0x07F7 - Lock prochot configuration +/** Offset 0x0827 - Lock prochot configuration Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable $EN_DIS **/ UINT8 ProcHotLock; -/** Offset 0x07F8 - Configuration for boot TDP selection +/** Offset 0x0828 - Configuration for boot TDP selection Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP Up;0xFF : Deactivate **/ UINT8 ConfigTdpLevel; -/** Offset 0x07F9 - Race To Halt +/** Offset 0x0829 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency in order to enter pkg C-State faster to reduce overall power. (RTH is controlled through MSR 1FC bit 20)Disable; 1: Enable @@ -3001,19 +3053,19 @@ typedef struct { **/ UINT8 RaceToHalt; -/** Offset 0x07FA - Max P-State Ratio +/** Offset 0x082A - Max P-State Ratio Max P-State Ratio, Valid Range 0 to 0x7F **/ UINT8 MaxRatio; -/** Offset 0x07FB - P-state ratios for custom P-state table +/** Offset 0x082B - P-state ratios for custom P-state table P-state ratios for custom P-state table. NumberOfEntries has valid range between 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] are configurable. Valid Range of each entry is 0 to 0x7F **/ UINT8 StateRatio[40]; -/** Offset 0x0823 - P-state ratios for max 16 version of custom P-state table +/** Offset 0x0853 - P-state ratios for max 16 version of custom P-state table P-state ratios for max 16 version of custom P-state table. This table is used for OS versions limited to a max of 16 P-States. If the first entry of this table is 0, or if Number of Entries is 16 or less, then this table will be ignored, and @@ -3022,391 +3074,391 @@ typedef struct { **/ UINT8 StateRatioMax16[16]; -/** Offset 0x0833 +/** Offset 0x0863 **/ - UINT8 UnusedUpdSpace25; + UINT8 UnusedUpdSpace24; -/** Offset 0x0834 - Platform Power Pmax +/** Offset 0x0864 - Platform Power Pmax PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. Range 0-1024 Watts. Value of 800 = 100W **/ UINT16 PsysPmax; -/** Offset 0x0836 - Interrupt Response Time Limit of C-State LatencyContol0 +/** Offset 0x0866 - Interrupt Response Time Limit of C-State LatencyContol0 Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl0Irtl; -/** Offset 0x0838 - Interrupt Response Time Limit of C-State LatencyContol1 +/** Offset 0x0868 - Interrupt Response Time Limit of C-State LatencyContol1 Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl1Irtl; -/** Offset 0x083A - Interrupt Response Time Limit of C-State LatencyContol2 +/** Offset 0x086A - Interrupt Response Time Limit of C-State LatencyContol2 Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl2Irtl; -/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol3 +/** Offset 0x086C - Interrupt Response Time Limit of C-State LatencyContol3 Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl3Irtl; -/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol4 +/** Offset 0x086E - Interrupt Response Time Limit of C-State LatencyContol4 Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl4Irtl; -/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol5 +/** Offset 0x0870 - Interrupt Response Time Limit of C-State LatencyContol5 Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF **/ UINT16 CstateLatencyControl5Irtl; -/** Offset 0x0842 +/** Offset 0x0872 **/ - UINT8 UnusedUpdSpace26[2]; + UINT8 UnusedUpdSpace25[2]; -/** Offset 0x0844 - Package Long duration turbo mode power limit +/** Offset 0x0874 - Package Long duration turbo mode power limit Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit1; -/** Offset 0x0848 - Package Short duration turbo mode power limit +/** Offset 0x0878 - Package Short duration turbo mode power limit Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit2Power; -/** Offset 0x084C - Package PL3 power limit +/** Offset 0x087C - Package PL3 power limit Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PowerLimit3; -/** Offset 0x0850 - Package PL4 power limit +/** Offset 0x0880 - Package PL4 power limit Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 PowerLimit4; -/** Offset 0x0854 - Tcc Offset Time Window for RATL +/** Offset 0x0884 - Tcc Offset Time Window for RATL Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 1023875 in Step size of 125 **/ UINT32 TccOffsetTimeWindowForRatl; -/** Offset 0x0858 - Short term Power Limit value for custom cTDP level 1 +/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 1 Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit1; -/** Offset 0x085C - Long term Power Limit value for custom cTDP level 1 +/** Offset 0x088C - Long term Power Limit value for custom cTDP level 1 Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom1PowerLimit2; -/** Offset 0x0860 - Short term Power Limit value for custom cTDP level 2 +/** Offset 0x0890 - Short term Power Limit value for custom cTDP level 2 Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit1; -/** Offset 0x0864 - Long term Power Limit value for custom cTDP level 2 +/** Offset 0x0894 - Long term Power Limit value for custom cTDP level 2 Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom2PowerLimit2; -/** Offset 0x0868 - Short term Power Limit value for custom cTDP level 3 +/** Offset 0x0898 - Short term Power Limit value for custom cTDP level 3 Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit1; -/** Offset 0x086C - Long term Power Limit value for custom cTDP level 3 +/** Offset 0x089C - Long term Power Limit value for custom cTDP level 3 Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 Custom3PowerLimit2; -/** Offset 0x0870 - Platform PL1 power +/** Offset 0x08A0 - Platform PL1 power Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit1Power; -/** Offset 0x0874 - Platform PL2 power +/** Offset 0x08A4 - Platform PL2 power Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range 0 to 4095875 in Step size of 125 **/ UINT32 PsysPowerLimit2Power; -/** Offset 0x0878 - Set Three Strike Counter Disable +/** Offset 0x08A8 - Set Three Strike Counter Disable False (default): Three Strike counter will be incremented and True: Prevents Three Strike counter from incrementing; 0: False; 1: True. 0: False, 1: True **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0879 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT +/** Offset 0x08A9 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; -/** Offset 0x087A - 5-Core Ratio Limit +/** Offset 0x08AA - 5-Core Ratio Limit 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 FiveCoreRatioLimit; -/** Offset 0x087B - 6-Core Ratio Limit +/** Offset 0x08AB - 6-Core Ratio Limit 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SixCoreRatioLimit; -/** Offset 0x087C - 7-Core Ratio Limit +/** Offset 0x08AC - 7-Core Ratio Limit 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 SevenCoreRatioLimit; -/** Offset 0x087D - 8-Core Ratio Limit +/** Offset 0x08AD - 8-Core Ratio Limit 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255 0x0:0xFF **/ UINT8 EightCoreRatioLimit; -/** Offset 0x087E - Intel Turbo Boost Max Technology 3.0 +/** Offset 0x08AE - Intel Turbo Boost Max Technology 3.0 Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbm; -/** Offset 0x087F - Intel Turbo Boost Max Technology 3.0 Driver +/** Offset 0x08AF - Intel Turbo Boost Max Technology 3.0 Driver Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled $EN_DIS **/ UINT8 EnableItbmDriver; -/** Offset 0x0880 - Enable or Disable C1 Cstate Demotion +/** Offset 0x08B0 - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateAutoDemotion; -/** Offset 0x0881 - Enable or Disable C1 Cstate UnDemotion +/** Offset 0x08B1 - Enable or Disable C1 Cstate UnDemotion Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C1StateUnDemotion; -/** Offset 0x0882 - CpuWakeUpTimer +/** Offset 0x08B2 - CpuWakeUpTimer Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased to 180 seconds. 0: Disable; 1: Enable $EN_DIS **/ UINT8 CpuWakeUpTimer; -/** Offset 0x0883 - Minimum Ring ratio limit override +/** Offset 0x08B3 - Minimum Ring ratio limit override Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MinRingRatioLimit; -/** Offset 0x0884 - Minimum Ring ratio limit override +/** Offset 0x08B4 - Minimum Ring ratio limit override Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo ratio limit **/ UINT8 MaxRingRatioLimit; -/** Offset 0x0885 - Enable or Disable C3 Cstate Demotion +/** Offset 0x08B5 - Enable or Disable C3 Cstate Demotion Enable or Disable C3 Cstate Demotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateAutoDemotion; -/** Offset 0x0886 - Enable or Disable C3 Cstate UnDemotion +/** Offset 0x08B6 - Enable or Disable C3 Cstate UnDemotion Enable or Disable C3 Cstate UnDemotion. Disable; 1: Enable $EN_DIS **/ UINT8 C3StateUnDemotion; -/** Offset 0x0887 - ReservedCpuPostMemTest +/** Offset 0x08B7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ UINT8 ReservedCpuPostMemTest[19]; -/** Offset 0x089A - SgxSinitDataFromTpm +/** Offset 0x08CA - SgxSinitDataFromTpm SgxSinitDataFromTpm default values **/ UINT8 SgxSinitDataFromTpm; -/** Offset 0x089B - End of Post message +/** Offset 0x08CB - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; -/** Offset 0x089C - D0I3 Setting for HECI Disable +/** Offset 0x08CC - D0I3 Setting for HECI Disable Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all HECI devices $EN_DIS **/ UINT8 DisableD0I3SettingForHeci; -/** Offset 0x089D +/** Offset 0x08CD **/ - UINT8 UnusedUpdSpace27; + UINT8 UnusedUpdSpace26; -/** Offset 0x089E - HD Audio Reset Wait Timer +/** Offset 0x08CE - HD Audio Reset Wait Timer The delay timer after Azalia reset, the value is number of microseconds. Default is 600. **/ UINT16 PchHdaResetWaitTimer; -/** Offset 0x08A0 - Enable LOCKDOWN SMI +/** Offset 0x08D0 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x08A1 - Enable LOCKDOWN BIOS Interface +/** Offset 0x08D1 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x08A2 - Unlock all GPIO pads +/** Offset 0x08D2 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x08A3 - PCH Unlock SideBand access +/** Offset 0x08D3 - PCH Unlock SideBand access The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. $EN_DIS **/ UINT8 PchSbAccessUnlock; -/** Offset 0x08A4 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x08D4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[24]; -/** Offset 0x08D4 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0904 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[24]; -/** Offset 0x0904 - PCIE RP Snoop Latency Override Mode +/** Offset 0x0934 - PCIE RP Snoop Latency Override Mode Latency Tolerance Reporting, Snoop Latency Override Mode. **/ UINT8 PcieRpSnoopLatencyOverrideMode[24]; -/** Offset 0x091C - PCIE RP Snoop Latency Override Multiplier +/** Offset 0x094C - PCIE RP Snoop Latency Override Multiplier Latency Tolerance Reporting, Snoop Latency Override Multiplier. **/ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0934 - PCIE RP Snoop Latency Override Value +/** Offset 0x0964 - PCIE RP Snoop Latency Override Value Latency Tolerance Reporting, Snoop Latency Override Value. **/ UINT16 PcieRpSnoopLatencyOverrideValue[24]; -/** Offset 0x0964 - PCIE RP Non Snoop Latency Override Mode +/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Mode Latency Tolerance Reporting, Non-Snoop Latency Override Mode. **/ UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; -/** Offset 0x097C - PCIE RP Non Snoop Latency Override Multiplier +/** Offset 0x09AC - PCIE RP Non Snoop Latency Override Multiplier Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. **/ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; -/** Offset 0x0994 - PCIE RP Non Snoop Latency Override Value +/** Offset 0x09C4 - PCIE RP Non Snoop Latency Override Value Latency Tolerance Reporting, Non-Snoop Latency Override Value. **/ UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; -/** Offset 0x09C4 - PCIE RP Slot Power Limit Scale +/** Offset 0x09F4 - PCIE RP Slot Power Limit Scale Specifies scale used for slot power limit value. Leave as 0 to set to default. **/ UINT8 PcieRpSlotPowerLimitScale[24]; -/** Offset 0x09DC - PCIE RP Slot Power Limit Value +/** Offset 0x0A0C - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. **/ UINT16 PcieRpSlotPowerLimitValue[24]; -/** Offset 0x0A0C - PCIE RP Upstream Port Transmiter Preset +/** Offset 0x0A3C - PCIE RP Upstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 5. **/ UINT8 PcieRpUptp[24]; -/** Offset 0x0A24 - PCIE RP Downstream Port Transmiter Preset +/** Offset 0x0A54 - PCIE RP Downstream Port Transmiter Preset Used during Gen3 Link Equalization. Used for all lanes. Default is 7. **/ UINT8 PcieRpDptp[24]; -/** Offset 0x0A3C - PCIE RP Enable Port8xh Decode +/** Offset 0x0A6C - PCIE RP Enable Port8xh Decode This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; 1: Enable. $EN_DIS **/ UINT8 PcieEnablePort8xhDecode; -/** Offset 0x0A3D - PCIE Port8xh Decode Port Index +/** Offset 0x0A6D - PCIE Port8xh Decode Port Index The Index of PCIe Port that is selected for Port8xh Decode (0 Based). **/ UINT8 PchPciePort8xhDecodePortIndex; -/** Offset 0x0A3E - PCH Energy Reporting +/** Offset 0x0A6E - PCH Energy Reporting Disable/Enable PCH to CPU energy report feature. $EN_DIS **/ UINT8 PchPmDisableEnergyReport; -/** Offset 0x0A3F - PCH Sata Test Mode +/** Offset 0x0A6F - PCH Sata Test Mode Allow entrance to the PCH SATA test modes. $EN_DIS **/ UINT8 SataTestMode; -/** Offset 0x0A40 - PCH USB OverCurrent mapping lock enable +/** Offset 0x0A70 - PCH USB OverCurrent mapping lock enable If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. $EN_DIS **/ UINT8 PchXhciOcLock; -/** Offset 0x0A41 - ReservedPchPostMemTest +/** Offset 0x0A71 - ReservedPchPostMemTest Reserved for Pch Post-Mem Test $EN_DIS **/ UINT8 ReservedPchPostMemTest[16]; -/** Offset 0x0A51 - Mctp Broadcast Cycle +/** Offset 0x0A81 - Mctp Broadcast Cycle Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. $EN_DIS **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0A52 +/** Offset 0x0A82 **/ - UINT8 UnusedUpdSpace28[2]; + UINT8 UnusedUpdSpace27[2]; -/** Offset 0x0A54 +/** Offset 0x0A84 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3423,15 +3475,15 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0788 +/** Offset 0x07B8 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0A60 +/** Offset 0x0A90 **/ - UINT8 UnusedUpdSpace29[6]; + UINT8 UnusedUpdSpace28[6]; -/** Offset 0x0A66 +/** Offset 0x0A96 **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h index decbb99aa6..1ef1e76b0f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2019, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,11 +37,11 @@ are permitted provided that the following conditions are met: #pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F4450554C4349 /* 'ICLUPD_T' */ +#define FSPT_UPD_SIGNATURE 0x545F4450554C4349 /* 'ICLUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4349 /* 'ICLUPD_M' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4349 /* 'ICLUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F4450554C4349 /* 'ICLUPD_S' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C4349 /* 'ICLUPD_S' */ #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h index cbe2d3c61b..e42727bbfc 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2019, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -40,15 +40,2989 @@ are permitted provided that the following conditions are met: #include +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + + /** Fsp M Configuration **/ typedef struct { -} FSP_M_CONFIG; -/** Fsp M Test Configuration +/** Offset 0x0040 - Memory SPD Pointer Channel 0 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 **/ -typedef struct { -} FSP_M_TEST_CONFIG; + UINT32 MemorySpdPtr00; + +/** Offset 0x0044 - Memory SPD Pointer Channel 0 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr01; + +/** Offset 0x0048 - Memory SPD Pointer Channel 1 Dimm 0 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr10; + +/** Offset 0x004C - Memory SPD Pointer Channel 1 Dimm 1 + Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 +**/ + UINT32 MemorySpdPtr11; + +/** Offset 0x0050 - Spd Address Tabl + Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used + if SPD Address is 00 +**/ + UINT8 SpdAddressTable[4]; + +/** Offset 0x0054 - SPD Data Length + Length of SPD Data + 0x100:256 Bytes, 0x200:512 Bytes +**/ + UINT16 MemorySpdDataLen; + +/** Offset 0x0056 - Dq Byte Map CH0 + Dq byte mapping between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqByteMapCh0[12]; + +/** Offset 0x0062 - Dq Byte Map CH1 + Dq byte mapping between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqByteMapCh1[12]; + +/** Offset 0x006E - Dqs Map CPU to DRAM CH 0 + Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent +**/ + UINT8 DqsMapCpu2DramCh0[8]; + +/** Offset 0x0076 - Dqs Map CPU to DRAM CH 1 + Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent +**/ + UINT8 DqsMapCpu2DramCh1[8]; + +/** Offset 0x007E - RcompResister settings + Indicates RcompReister settings: Board-dependent +**/ + UINT16 RcompResistor[3]; + +/** Offset 0x0084 - RcompTarget settings + RcompTarget settings: board-dependent +**/ + UINT16 RcompTarget[5]; + +/** Offset 0x008E +**/ + UINT8 UnusedUpdSpace0[2]; + +/** Offset 0x0090 - Platform Reserved Memory Size + The minimum platform memory size required to pass control into DXE +**/ + UINT64 PlatformMemorySize; + +/** Offset 0x0098 - PcdSerialDebugLevel + Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info, 5:Load Error Warnings Info and Verbose +**/ + UINT8 PcdSerialDebugLevel; + +/** Offset 0x0099 - Ask MRC to clear memory content + Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. + $EN_DIS +**/ + UINT8 CleanMemory; + +/** Offset 0x009A - Smram Mask + The SMM Regions AB-SEG and/or H-SEG reserved + 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both +**/ + UINT8 SmramMask; + +/** Offset 0x009B - Dqs Pins Interleaved Setting + Indicates DqPinsInterleaved setting: board-dependent + $EN_DIS +**/ + UINT8 DqPinsInterleaved; + +/** Offset 0x009C - SA GV + System Agent dynamic frequency support and when enabled memory will be training + at three different frequencies. + 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled +**/ + UINT8 SaGv; + +/** Offset 0x009D +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x009E - DDR Frequency Limit + Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, + 2133, 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 DdrFreqLimit; + +/** Offset 0x00A0 - Channel A DIMM Control + Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmChannel0; + +/** Offset 0x00A1 - Channel B DIMM Control + Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. + 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs +**/ + UINT8 DisableDimmChannel1; + +/** Offset 0x00A2 - MRC Safe Config + Enables/Disable MRC Safe Config + $EN_DIS +**/ + UINT8 MrcSafeConfig; + +/** Offset 0x00A3 - LPDDR4 Write DQ/DQS Retraining + Enables/Disable LPDDR4 Write DQ/DQS Retraining + $EN_DIS +**/ + UINT8 Lp4DqsOscEn; + +/** Offset 0x00A4 - Training Trace + This option enables the trained state tracing feature in MRC. This feature will + print out the key training parameters state across major training steps. + $EN_DIS +**/ + UINT8 TrainTrace; + +/** Offset 0x00A5 - Rank Margin Tool per Task + This option enables the user to execute Rank Margin Tool per major training step + in the MRC. + $EN_DIS +**/ + UINT8 RmtPerTask; + +/** Offset 0x00A6 - LowSupplyEnData + Enable: Enable Low Supply for LPDDR4 Data, Disable(Default) + $EN_DIS +**/ + UINT8 LowSupplyEnData; + +/** Offset 0x00A7 - LowSupplyEnCcc + Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default) + $EN_DIS +**/ + UINT8 LowSupplyEnCcc; + +/** Offset 0x00A8 - Memory Test on Warm Boot + Run Base Memory Test on Warm Boot + 0:Disable, 1:Enable +**/ + UINT8 MemTestOnWarmBoot; + +/** Offset 0x00A9 +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x00AA - Low Frequency + SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, + 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 FreqSaGvLow; + +/** Offset 0x00AC - Mid Frequency + SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, + 2400, 2667, 2933 and 0 for Auto. + 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto +**/ + UINT16 FreqSaGvMid; + +/** Offset 0x00AE - DDR Speed Control + DDR Frequency and Gear control for all SAGV points. + 0:Auto, 1:Manual +**/ + UINT8 DdrSpeedControl; + +/** Offset 0x00AF - SA GV Low Gear + Gear Selection for SAGV Low point + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvLowGear2; + +/** Offset 0x00B0 - SA GV Mid Gear + Gear Selection for SAGV Mid point + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvMidGear2; + +/** Offset 0x00B1 - SA GV High Gear + Gear Selection for SAGV High point, or when SAGV is disabled + 0:Gear1, 1:Gear2 +**/ + UINT8 SaGvHighGear2; + +/** Offset 0x00B2 - Scrambler Support + This option enables data scrambling in memory. + $EN_DIS +**/ + UINT8 ScramblerSupport; + +/** Offset 0x00B3 - Safe Mode Support + This option configures the varous items in the IO and MC to be more conservative.(def=Disable) + $EN_DIS +**/ + UINT8 SafeMode; + +/** Offset 0x00B4 - Ddr4OneDpc + DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, + or on both (default) + 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled +**/ + UINT8 Ddr4OneDpc; + +/** Offset 0x00B5 - Probeless Trace + Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. + This also requires IED to be enabled. + $EN_DIS +**/ + UINT8 ProbelessTrace; + +/** Offset 0x00B6 - VREF_CA + CA Vref routing: board-dependent + 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, + 2:VREF_CA to CH_A and VREF_DQ_B to CH_B +**/ + UINT8 CaVrefConfig; + +/** Offset 0x00B7 - SPD Profile Selected + Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP + Profile 1, 3=XMP Profile 2 + 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 +**/ + UINT8 SpdProfileSelected; + +/** Offset 0x00B8 - Memory Voltage + Memory Voltage Override (Vddq). Default = no override + 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 + Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts +**/ + UINT16 VddVoltage; + +/** Offset 0x00BA - Memory Reference Clock + 100MHz, 133MHz. + 0:133MHz, 1:100MHz +**/ + UINT8 RefClk; + +/** Offset 0x00BB - Memory Ratio + Automatic or the frequency will equal ratio times reference clock. Set to Auto to + recalculate memory timings listed below. + 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 Ratio; + +/** Offset 0x00BC - tCL + CAS Latency, 0: AUTO, max: 31 +**/ + UINT8 tCL; + +/** Offset 0x00BD - tCWL + Min CAS Write Latency Delay Time, 0: AUTO, max: 34 +**/ + UINT8 tCWL; + +/** Offset 0x00BE - tFAW + Min Four Activate Window Delay Time, 0: AUTO, max: 63 +**/ + UINT16 tFAW; + +/** Offset 0x00C0 - tRAS + RAS Active Time, 0: AUTO, max: 64 +**/ + UINT16 tRAS; + +/** Offset 0x00C2 - tRCD/tRP + RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 +**/ + UINT8 tRCDtRP; + +/** Offset 0x00C3 +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x00C4 - tREFI + Refresh Interval, 0: AUTO, max: 65535 +**/ + UINT16 tREFI; + +/** Offset 0x00C6 - tRFC + Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 +**/ + UINT16 tRFC; + +/** Offset 0x00C8 - tRRD + Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 +**/ + UINT8 tRRD; + +/** Offset 0x00C9 - tRTP + Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal + values: 5, 6, 7, 8, 9, 10, 12 +**/ + UINT8 tRTP; + +/** Offset 0x00CA - tWR + Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, + 20, 24, 30, 34, 40 + 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, + 34:34, 40:40 +**/ + UINT8 tWR; + +/** Offset 0x00CB - tWTR + Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 +**/ + UINT8 tWTR; + +/** Offset 0x00CC - NMode + System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N +**/ + UINT8 NModeSupport; + +/** Offset 0x00CD - DllBwEn[0] + DllBwEn[0], for 1067 (0..7) +**/ + UINT8 DllBwEn0; + +/** Offset 0x00CE - DllBwEn[1] + DllBwEn[1], for 1333 (0..7) +**/ + UINT8 DllBwEn1; + +/** Offset 0x00CF - DllBwEn[2] + DllBwEn[2], for 1600 (0..7) +**/ + UINT8 DllBwEn2; + +/** Offset 0x00D0 - DllBwEn[3] + DllBwEn[3], for 1867 and up (0..7) +**/ + UINT8 DllBwEn3; + +/** Offset 0x00D1 - ISVT IO Port Address + ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default +**/ + UINT8 IsvtIoPort; + +/** Offset 0x00D2 - HobBufferSize + Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB + total HOB size). + 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value +**/ + UINT8 HobBufferSize; + +/** Offset 0x00D3 - Early Command Training + Enables/Disable Early Command Training + $EN_DIS +**/ + UINT8 ECT; + +/** Offset 0x00D4 - SenseAmp Offset Training + Enables/Disable SenseAmp Offset Training + $EN_DIS +**/ + UINT8 SOT; + +/** Offset 0x00D5 - Early ReadMPR Timing Centering 2D + Enables/Disable Early ReadMPR Timing Centering 2D + $EN_DIS +**/ + UINT8 ERDMPRTC2D; + +/** Offset 0x00D6 - Read MPR Training + Enables/Disable Read MPR Training + $EN_DIS +**/ + UINT8 RDMPRT; + +/** Offset 0x00D7 - Receive Enable Training + Enables/Disable Receive Enable Training + $EN_DIS +**/ + UINT8 RCVET; + +/** Offset 0x00D8 - Jedec Write Leveling + Enables/Disable Jedec Write Leveling + $EN_DIS +**/ + UINT8 JWRL; + +/** Offset 0x00D9 - Early Write Time Centering 2D + Enables/Disable Early Write Time Centering 2D + $EN_DIS +**/ + UINT8 EWRTC2D; + +/** Offset 0x00DA - Early Read Time Centering 2D + Enables/Disable Early Read Time Centering 2D + $EN_DIS +**/ + UINT8 ERDTC2D; + +/** Offset 0x00DB - Write Timing Centering 1D + Enables/Disable Write Timing Centering 1D + $EN_DIS +**/ + UINT8 WRTC1D; + +/** Offset 0x00DC - Write Voltage Centering 1D + Enables/Disable Write Voltage Centering 1D + $EN_DIS +**/ + UINT8 WRVC1D; + +/** Offset 0x00DD - Read Timing Centering 1D + Enables/Disable Read Timing Centering 1D + $EN_DIS +**/ + UINT8 RDTC1D; + +/** Offset 0x00DE - Dimm ODT Training + Enables/Disable Dimm ODT Training + $EN_DIS +**/ + UINT8 DIMMODTT; + +/** Offset 0x00DF - DIMM RON Training + Enables/Disable DIMM RON Training + $EN_DIS +**/ + UINT8 DIMMRONT; + +/** Offset 0x00E0 - Write Slew Rate Training + Enables/Disable Write Slew Rate Training + $EN_DIS +**/ + UINT8 WRSRT; + +/** Offset 0x00E1 - Read ODT Training + Enables/Disable Read ODT Training + $EN_DIS +**/ + UINT8 RDODTT; + +/** Offset 0x00E2 - Read Equalization Training + Enables/Disable Read Equalization Training + $EN_DIS +**/ + UINT8 RDEQT; + +/** Offset 0x00E3 - Read Amplifier Training + Enables/Disable Read Amplifier Training + $EN_DIS +**/ + UINT8 RDAPT; + +/** Offset 0x00E4 - Write Timing Centering 2D + Enables/Disable Write Timing Centering 2D + $EN_DIS +**/ + UINT8 WRTC2D; + +/** Offset 0x00E5 - Read Timing Centering 2D + Enables/Disable Read Timing Centering 2D + $EN_DIS +**/ + UINT8 RDTC2D; + +/** Offset 0x00E6 - Write Voltage Centering 2D + Enables/Disable Write Voltage Centering 2D + $EN_DIS +**/ + UINT8 WRVC2D; + +/** Offset 0x00E7 - Read Voltage Centering 2D + Enables/Disable Read Voltage Centering 2D + $EN_DIS +**/ + UINT8 RDVC2D; + +/** Offset 0x00E8 - Command Voltage Centering + Enables/Disable Command Voltage Centering + $EN_DIS +**/ + UINT8 CMDVC; + +/** Offset 0x00E9 - Late Command Training + Enables/Disable Late Command Training + $EN_DIS +**/ + UINT8 LCT; + +/** Offset 0x00EA - Round Trip Latency Training + Enables/Disable Round Trip Latency Training + $EN_DIS +**/ + UINT8 RTL; + +/** Offset 0x00EB - Turn Around Timing Training + Enables/Disable Turn Around Timing Training + $EN_DIS +**/ + UINT8 TAT; + +/** Offset 0x00EC - Receive Enable Centering 1D + Enables/Disable Receive Enable Centering 1D + $EN_DIS +**/ + UINT8 RCVENC1D; + +/** Offset 0x00ED - Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 RMT; + +/** Offset 0x00EE - Margin Limit Check + Margin Limit Check. Choose level of margin check + 0:Disable, 1:L1, 2:L2, 3:Both +**/ + UINT8 MarginLimitCheck; + +/** Offset 0x00EF +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00F0 - Margin Limit L2 + % of L1 check for margin limit check +**/ + UINT16 MarginLimitL2; + +/** Offset 0x00F2 - Memory Test + Enables/Disable Memory Test + $EN_DIS +**/ + UINT8 MEMTST; + +/** Offset 0x00F3 - DIMM SPD Alias Test + Enables/Disable DIMM SPD Alias Test + $EN_DIS +**/ + UINT8 ALIASCHK; + +/** Offset 0x00F4 - Retrain Margin Check + Enables/Disable Retrain Margin Check + $EN_DIS +**/ + UINT8 RMC; + +/** Offset 0x00F5 - Write Drive Strength Up/Dn independently + Enables/Disable Write Drive Strength Up/Dn independently + $EN_DIS +**/ + UINT8 WRDSUDT; + +/** Offset 0x00F6 - Command Slew Rate Training + Enables/Disable Command Slew Rate Training + $EN_DIS +**/ + UINT8 CMDSR; + +/** Offset 0x00F7 - Command Drive Strength and Equalization 2D + Enables/Disable Command Drive Strength and Equalization 2D + $EN_DIS +**/ + UINT8 CMDDSEQ; + +/** Offset 0x00F8 - Command Normalization + Enables/Disable Command Normalization + $EN_DIS +**/ + UINT8 CMDNORM; + +/** Offset 0x00F9 - Early DQ Write Drive Strength and Equalization Training + Enables/Disable Early DQ Write Drive Strength and Equalization Training + $EN_DIS +**/ + UINT8 EWRDSEQ; + +/** Offset 0x00FA - Read Voltage Centering + Enables/Disable Read Voltage Centering + $EN_DIS +**/ + UINT8 RDVC1D; + +/** Offset 0x00FB - Write TCO Comp Training + Enables/Disable Write TCO Comp Training + $EN_DIS +**/ + UINT8 TXTCO; + +/** Offset 0x00FC - Clock TCO Comp Training + Enables/Disable Clock TCO Comp Training + $EN_DIS +**/ + UINT8 CLKTCO; + +/** Offset 0x00FD - Dimm ODT CA Training + Enables/Disable Dimm ODT CA Training + $EN_DIS +**/ + UINT8 DIMMODTCA; + +/** Offset 0x00FE - Write TCO Dqs Training + Enables/Disable Write TCO Dqs Training + $EN_DIS +**/ + UINT8 TXTCODQS; + +/** Offset 0x00FF - Duty Cycle Correction + Enables/Disable Duty Cycle Correction + $EN_DIS +**/ + UINT8 DCC; + +/** Offset 0x0100 - DQ DFE Training + Enable/Disable DQ DFE Training + $EN_DIS +**/ + UINT8 DQDFE; + +/** Offset 0x0101 - Sense Amplifier Correction Training + Enable/Disable Sense Amplifier Correction Training + $EN_DIS +**/ + UINT8 SOTC; + +/** Offset 0x0102 - ECC Support + Enables/Disable ECC Support + $EN_DIS +**/ + UINT8 EccSupport; + +/** Offset 0x0103 - Memory Remap + Enables/Disable Memory Remap + $EN_DIS +**/ + UINT8 RemapEnable; + +/** Offset 0x0104 - MRC Time Measure + Enable/Disable MRC Time Measure + $EN_DIS +**/ + UINT8 MrcTimeMeasure; + +/** Offset 0x0105 - MRC Fast Boot + Enable/Disable MRC Fast flow + $EN_DIS +**/ + UINT8 MrcFastBoot; + +/** Offset 0x0106 - MRC Force Training on Warm + Enables/Disable the MRC training on warm boot + $EN_DIS +**/ + UINT8 MrcTrainOnWarm; + +/** Offset 0x0107 - Rank Interleave support + Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at + the same time. + $EN_DIS +**/ + UINT8 RankInterleave; + +/** Offset 0x0108 - Enhanced Interleave support + Enables/Disable Enhanced Interleave support + $EN_DIS +**/ + UINT8 EnhancedInterleave; + +/** Offset 0x0109 - Memory Trace + Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of + equal size. This option may change TOLUD and REMAP values as needed. + $EN_DIS +**/ + UINT8 MemoryTrace; + +/** Offset 0x010A - Ch Hash Support + Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode + $EN_DIS +**/ + UINT8 ChHashEnable; + +/** Offset 0x010B - Extern Therm Status + Enables/Disable Extern Therm Status + $EN_DIS +**/ + UINT8 EnableExtts; + +/** Offset 0x010C - Closed Loop Therm Manage + Enables/Disable Closed Loop Therm Manage + $EN_DIS +**/ + UINT8 EnableCltm; + +/** Offset 0x010D - Open Loop Therm Manage + Enables/Disable Open Loop Therm Manage + $EN_DIS +**/ + UINT8 EnableOltm; + +/** Offset 0x010E - DDR PowerDown and idle counter + Enables/Disable DDR PowerDown and idle counter + $EN_DIS +**/ + UINT8 EnablePwrDn; + +/** Offset 0x010F - DDR PowerDown and idle counter - LPDDR + Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) + $EN_DIS +**/ + UINT8 EnablePwrDnLpddr; + +/** Offset 0x0110 - Use user provided power weights, scale factor, and channel power floor values + Enables/Disable Use user provided power weights, scale factor, and channel power + floor values + $EN_DIS +**/ + UINT8 UserPowerWeightsEn; + +/** Offset 0x0111 - RAPL PL Lock + Enables/Disable RAPL PL Lock + $EN_DIS +**/ + UINT8 RaplLim2Lock; + +/** Offset 0x0112 - RAPL PL 2 enable + Enables/Disable RAPL PL 2 enable + $EN_DIS +**/ + UINT8 RaplLim2Ena; + +/** Offset 0x0113 - RAPL PL 1 enable + Enables/Disable RAPL PL 1 enable + $EN_DIS +**/ + UINT8 RaplLim1Ena; + +/** Offset 0x0114 - SelfRefresh Enable + Enables/Disable SelfRefresh Enable + $EN_DIS +**/ + UINT8 SrefCfgEna; + +/** Offset 0x0115 - Throttler CKEMin Defeature - LPDDR + Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeatLpddr; + +/** Offset 0x0116 - Throttler CKEMin Defeature + Enables/Disable Throttler CKEMin Defeature + $EN_DIS +**/ + UINT8 ThrtCkeMinDefeat; + +/** Offset 0x0117 - Enable RH Prevention + Enables/Disable RH Prevention + $EN_DIS +**/ + UINT8 RhPrevention; + +/** Offset 0x0118 - Exit On Failure (MRC) + Enables/Disable Exit On Failure (MRC) + $EN_DIS +**/ + UINT8 ExitOnFailure; + +/** Offset 0x0119 - LPDDR Thermal Sensor + Enables/Disable LPDDR Thermal Sensor + $EN_DIS +**/ + UINT8 DdrThermalSensor; + +/** Offset 0x011A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedClock; + +/** Offset 0x011B - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP + $EN_DIS +**/ + UINT8 Ddr4DdpSharedZq; + +/** Offset 0x011C - Base reference clock value + Base reference clock value, in Hertz(Default is 125Hz) + 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz +**/ + UINT32 BClkFrequency; + +/** Offset 0x0120 - Ch Hash Interleaved Bit + Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave + the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 + 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 +**/ + UINT8 ChHashInterleaveBit; + +/** Offset 0x0121 +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0122 - Ch Hash Mask + Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to + BITS [19:6] Default is 0x30CC +**/ + UINT16 ChHashMask; + +/** Offset 0x0124 - Extended Bank Hashing + Eanble/Disable ExtendedBankHashing + $EN_DIS +**/ + UINT8 ExtendedBankHashing; + +/** Offset 0x0125 - Energy Scale Factor + Energy Scale Factor, Default is 4 +**/ + UINT8 EnergyScaleFact; + +/** Offset 0x0126 - EPG DIMM Idd3N + Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on + a per DIMM basis. Default is 26 +**/ + UINT16 Idd3n; + +/** Offset 0x0128 - EPG DIMM Idd3P + Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated + on a per DIMM basis. Default is 11 +**/ + UINT16 Idd3p; + +/** Offset 0x012A - RH Activation Probability + RH Activation Probability, Probability value is 1/2^(inputvalue) +**/ + UINT8 RhActProbability; + +/** Offset 0x012B - RAPL PL 2 WindowX + Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim2WindX; + +/** Offset 0x012C - RAPL PL 2 WindowY + Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim2WindY; + +/** Offset 0x012D - RAPL PL 1 WindowX + Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindX; + +/** Offset 0x012E - RAPL PL 1 WindowY + Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) +**/ + UINT8 RaplLim1WindY; + +/** Offset 0x012F +**/ + UINT8 UnusedUpdSpace6; + +/** Offset 0x0130 - RAPL PL 2 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim2Pwr; + +/** Offset 0x0132 - RAPL PL 1 Power + range[0;2^14-1]= [2047.875;0]in W, (224= Def) +**/ + UINT16 RaplLim1Pwr; + +/** Offset 0x0134 - Warm Threshold Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh0Dimm0; + +/** Offset 0x0135 - Warm Threshold Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh0Dimm1; + +/** Offset 0x0136 - Warm Threshold Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh1Dimm0; + +/** Offset 0x0137 - Warm Threshold Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 WarmThresholdCh1Dimm1; + +/** Offset 0x0138 - Hot Threshold Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh0Dimm0; + +/** Offset 0x0139 - Hot Threshold Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh0Dimm1; + +/** Offset 0x013A - Hot Threshold Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh1Dimm0; + +/** Offset 0x013B - Hot Threshold Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 +**/ + UINT8 HotThresholdCh1Dimm1; + +/** Offset 0x013C - Warm Budget Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh0Dimm0; + +/** Offset 0x013D - Warm Budget Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh0Dimm1; + +/** Offset 0x013E - Warm Budget Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh1Dimm0; + +/** Offset 0x013F - Warm Budget Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 WarmBudgetCh1Dimm1; + +/** Offset 0x0140 - Hot Budget Ch0 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh0Dimm0; + +/** Offset 0x0141 - Hot Budget Ch0 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh0Dimm1; + +/** Offset 0x0142 - Hot Budget Ch1 Dimm0 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh1Dimm0; + +/** Offset 0x0143 - Hot Budget Ch1 Dimm1 + range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM +**/ + UINT8 HotBudgetCh1Dimm1; + +/** Offset 0x0144 - Idle Energy Ch0Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh0Dimm0; + +/** Offset 0x0145 - Idle Energy Ch0Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh0Dimm1; + +/** Offset 0x0146 - Idle Energy Ch1Dimm0 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh1Dimm0; + +/** Offset 0x0147 - Idle Energy Ch1Dimm1 + Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) +**/ + UINT8 IdleEnergyCh1Dimm1; + +/** Offset 0x0148 - PowerDown Energy Ch0Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh0Dimm0; + +/** Offset 0x0149 - PowerDown Energy Ch0Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh0Dimm1; + +/** Offset 0x014A - PowerDown Energy Ch1Dimm0 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh1Dimm0; + +/** Offset 0x014B - PowerDown Energy Ch1Dimm1 + PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) +**/ + UINT8 PdEnergyCh1Dimm1; + +/** Offset 0x014C - Activate Energy Ch0Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh0Dimm0; + +/** Offset 0x014D - Activate Energy Ch0Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh0Dimm1; + +/** Offset 0x014E - Activate Energy Ch1Dimm0 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh1Dimm0; + +/** Offset 0x014F - Activate Energy Ch1Dimm1 + Activate Energy Contribution, range[255;0],(172= Def) +**/ + UINT8 ActEnergyCh1Dimm1; + +/** Offset 0x0150 - Read Energy Ch0Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh0Dimm0; + +/** Offset 0x0151 - Read Energy Ch0Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh0Dimm1; + +/** Offset 0x0152 - Read Energy Ch1Dimm0 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh1Dimm0; + +/** Offset 0x0153 - Read Energy Ch1Dimm1 + Read Energy Contribution, range[255;0],(212= Def) +**/ + UINT8 RdEnergyCh1Dimm1; + +/** Offset 0x0154 - Write Energy Ch0Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh0Dimm0; + +/** Offset 0x0155 - Write Energy Ch0Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh0Dimm1; + +/** Offset 0x0156 - Write Energy Ch1Dimm0 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh1Dimm0; + +/** Offset 0x0157 - Write Energy Ch1Dimm1 + Write Energy Contribution, range[255;0],(221= Def) +**/ + UINT8 WrEnergyCh1Dimm1; + +/** Offset 0x0158 - Throttler CKEMin Timer + Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). + Dfault is 0x30 +**/ + UINT8 ThrtCkeMinTmr; + +/** Offset 0x0159 - Cke Rank Mapping + Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies + which rank CKE[i] goes to. +**/ + UINT8 CkeRankMapping; + +/** Offset 0x015A - Rapl Power Floor Ch0 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh0; + +/** Offset 0x015B - Rapl Power Floor Ch1 + Power budget ,range[255;0],(0= 5.3W Def) +**/ + UINT8 RaplPwrFlCh1; + +/** Offset 0x015C - Command Rate Support + CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs + 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS +**/ + UINT8 EnCmdRate; + +/** Offset 0x015D - REFRESH_2X_MODE + 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot + 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only +**/ + UINT8 Refresh2X; + +/** Offset 0x015E - Energy Performance Gain + Enable/disable(default) Energy Performance Gain. + $EN_DIS +**/ + UINT8 EpgEnable; + +/** Offset 0x015F - Row Hammer Solution + Type of method used to prevent Row Hammer. Default is Hardware RHP + 0:Hardware RHP, 1:2x Refresh +**/ + UINT8 RhSolution; + +/** Offset 0x0160 - User Manual Threshold + Disabled: Predefined threshold will be used.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserThresholdEnable; + +/** Offset 0x0161 - User Manual Budget + Disabled: Configuration of memories will defined the Budget value.\n + Enabled: User Input will be used. + $EN_DIS +**/ + UINT8 UserBudgetEnable; + +/** Offset 0x0162 - TcritMax + Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax + has to be greater than THIGHMax .\n + Critical temperature will be TcritMax +**/ + UINT8 TsodTcritMax; + +/** Offset 0x0163 - Event mode + Disable:Comparator mode.\n + Enable:Interrupt mode + $EN_DIS +**/ + UINT8 TsodEventMode; + +/** Offset 0x0164 - EVENT polarity + Disable:Active LOW.\n + Enable:Active HIGH + $EN_DIS +**/ + UINT8 TsodEventPolarity; + +/** Offset 0x0165 - Critical event only + Disable:Trips on alarm or critical.\n + Enable:Trips only if criticaal temperature is reached + $EN_DIS +**/ + UINT8 TsodCriticalEventOnly; + +/** Offset 0x0166 - Event output control + Disable:Event output disable.\n + Enable:Event output enabled + $EN_DIS +**/ + UINT8 TsodEventOutputControl; + +/** Offset 0x0167 - Alarm window lock bit + Disable:Alarm trips are not locked and can be changed.\n + Enable:Alarm trips are locked and cannot be changed + $EN_DIS +**/ + UINT8 TsodAlarmwindowLockBit; + +/** Offset 0x0168 - Critical trip lock bit + Disable:Critical trip is not locked and can be changed.\n + Enable:Critical trip is locked and cannot be changed + $EN_DIS +**/ + UINT8 TsodCriticaltripLockBit; + +/** Offset 0x0169 - Shutdown mode + Disable:Temperature sensor enable.\n + Enable:Temperature sensor disable + $EN_DIS +**/ + UINT8 TsodShutdownMode; + +/** Offset 0x016A - ThighMax + Thigh = ThighMax (Default is 93) +**/ + UINT8 TsodThigMax; + +/** Offset 0x016B - User Manual Thig and Tcrit + Disabled(Default): Temperature will be given by the configuration of memories and + 1x or 2xrefresh rate.\n + Enabled: User Input will define for Thigh and Tcrit. + $EN_DIS +**/ + UINT8 TsodManualEnable; + +/** Offset 0x016C - Force OLTM or 2X Refresh when needed + Disabled(Default): = Force OLTM.\n + Enabled: = Force 2x Refresh. + $EN_DIS +**/ + UINT8 ForceOltmOrRefresh2x; + +/** Offset 0x016D - Pwr Down Idle Timer + The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means + AUTO: 64 for ULX/ULT, 128 for DT/Halo +**/ + UINT8 PwdwnIdleCounter; + +/** Offset 0x016E - Bitmask of ranks that have CA bus terminated + Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, + Rank0 is terminating and Rank1 is non-terminating +**/ + UINT8 CmdRanksTerminated; + +/** Offset 0x016F - RMTLoopCount + Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO +**/ + UINT8 RMTLoopCount; + +/** Offset 0x0170 - Throttler CKEMin Timer for LPDDR + LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH + (4). Dfault is 0x40 +**/ + UINT8 ThrtCkeMinTmrLpddr; + +/** Offset 0x0171 - Retrain on Fast Fail + Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled + $EN_DIS +**/ + UINT8 RetrainOnFastFail; + +/** Offset 0x0172 - Rank Margin Tool Per Bit + Enable/disable Rank Margin Tool Per Bit. + $EN_DIS +**/ + UINT8 RMTBIT; + +/** Offset 0x0173 +**/ + UINT8 MrcPreMemRsvd[14]; + +/** Offset 0x0181 - Over clocking support + Over clocking support; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 OcSupport; + +/** Offset 0x0182 - Over clocking Lock + Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 OcLock; + +/** Offset 0x0183 - Maximum Core Turbo Ratio Override + Maximum core turbo ratio override allows to increase CPU core frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 CoreMaxOcRatio; + +/** Offset 0x0184 - Core voltage mode + Core voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 CoreVoltageMode; + +/** Offset 0x0185 - Maximum clr turbo ratio override + Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the + fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 +**/ + UINT8 RingMaxOcRatio; + +/** Offset 0x0186 - Ring Downbin + Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always + lower than the core ratio.0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 RingDownBin; + +/** Offset 0x0187 - Ring voltage mode + Ring voltage mode; 0: Adaptive; 1: Override. + $EN_DIS +**/ + UINT8 RingVoltageMode; + +/** Offset 0x0188 - Ring voltage override + The ring voltage override which is applied to the entire range of cpu ring frequencies. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageOverride; + +/** Offset 0x018A - Ring Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 RingVoltageAdaptive; + +/** Offset 0x018C - Ring Turbo voltage Offset + The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 +**/ + UINT16 RingVoltageOffset; + +/** Offset 0x018E - core voltage override + The core voltage override which is applied to the entire range of cpu core frequencies. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageOverride; + +/** Offset 0x0190 - Core Turbo voltage Adaptive + Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. + Valid Range 0 to 2000 +**/ + UINT16 CoreVoltageAdaptive; + +/** Offset 0x0192 - Core Turbo voltage Offset + The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 +**/ + UINT16 CoreVoltageOffset; + +/** Offset 0x0194 - Core PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-63 +**/ + UINT8 CorePllVoltageOffset; + +/** Offset 0x0195 - GT PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-63 +**/ + UINT8 GtPllVoltageOffset; + +/** Offset 0x0196 - Ring PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-63 +**/ + UINT8 RingPllVoltageOffset; + +/** Offset 0x0197 - System Agent PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-63 +**/ + UINT8 SaPllVoltageOffset; + +/** Offset 0x0198 - Memory Controller PLL voltage offset + Core PLL voltage offset. 0: No offset. Range 0-63 +**/ + UINT8 McPllVoltageOffset; + +/** Offset 0x0199 - BCLK Adaptive Voltage Enable + When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: + Disable; 1: Enable + $EN_DIS +**/ + UINT8 BclkAdaptiveVoltage; + +/** Offset 0x019A - AVX2 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx2RatioOffset; + +/** Offset 0x019B - AVX3 Ratio Offset + 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio + vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. +**/ + UINT8 Avx3RatioOffset; + +/** Offset 0x019C - TjMax Offset + TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support + TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 +**/ + UINT8 TjMaxOffset; + +/** Offset 0x019D - Fivr Faults + Fivr Faults; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 FivrFaults; + +/** Offset 0x019E - Fivr Efficiency + Fivr Efficiency Management; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 FivrEfficiency; + +/** Offset 0x019F +**/ + UINT8 UnusedUpdSpace7; + +/** Offset 0x01A0 - VccIn Voltage Override + This will override VccIn output voltage level to the voltage value specified. Valid + Range 0 to 3000 +**/ + UINT16 VccInVoltageOverride; + +/** Offset 0x01A2 - Avx2 Voltage Guardband Scaling Factor + AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in + 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx2VoltageScaleFactor; + +/** Offset 0x01A3 - Avx512 Voltage Guardband Scaling Factor + AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 + in 1/100 units, where a value of 125 would apply a 1.25 scale factor. +**/ + UINT8 Avx512VoltageScaleFactor; + +/** Offset 0x01A4 - Non-Core High Voltage Mode + Enable High Voltage Mode in the non-core FIVR domains (Ring/GT). Used for LN2 cold + boot mitigation. 0 - Disable, 1 - Enable + $EN_DIS +**/ + UINT8 NonCoreHighVoltageMode; + +/** Offset 0x01A5 - Core High Voltage Mode + Enable High Voltage Mode in the core FIVR Domains. Used for LN2 cold boot mitigation. + 0 - Disable, 1 - Enable + $EN_DIS +**/ + UINT8 CoreHighVoltageMode; + +/** Offset 0x01A6 - Per Core Ratio Limit + Per Core Ratio Limit. Range 0 - 120. Default = 0, no BIOS programming of + per core ratio. +**/ + UINT8 PerCoreRatioLimit[8]; + +/** Offset 0x01AE - FIVR TDC + Enable or Disable FIVR TDC from PCODE. 0: Disable. 1: Enable. + $EN_DIS +**/ + UINT8 FivrTdc; + +/** Offset 0x01AF - Full Range Multiplier unlock enable + Enable or Disable communication between Punit and Core in 100MHz granularity. 0: + Disable. 1: Enable. + $EN_DIS +**/ + UINT8 FullRangeMultiplierUnlockEn; + +/** Offset 0x01B0 - SA PLL Freq override + Enable or Disable SA PLL Freq override to 1600MHz instead of 3200MHz on Desktop. + 0: Disable. 1: Enable. + $EN_DIS +**/ + UINT8 SaPllFreqOverride; + +/** Offset 0x01B1 - XHCI PLL override + Enable or Disable XHCI PLL override to use TMU PLL instead of SA PLL. 0: Disable. + 1: Enable. + $EN_DIS +**/ + UINT8 XhciPllOverride; + +/** Offset 0x01B2 - FIVR PS + Enable or Disable FIVR PS. 0: Disable. 1: Enable. + $EN_DIS +**/ + UINT8 FivrPs; + +/** Offset 0x01B3 - FIVR PROTECTION + Enable or Disable FIVR overvoltage and overcurrent protection. 0: Disable. + 1: Enable. + $EN_DIS +**/ + UINT8 FivrProtection; + +/** Offset 0x01B4 - TSC HW Fixup + Enable or Disable Core HW Fixup during TSC copy from PMA and APIC. 0: Disable. + 1: Enable. + $EN_DIS +**/ + UINT8 TscHwFixup; + +/** Offset 0x01B5 +**/ + UINT8 UnusedUpdSpace8; + +/** Offset 0x01B6 - VccIN VR MAX Voltage + The new VccIN VR MAX Voltage to allow requesting in U3.13V format. Valid Range is + in U3.13 from 0 to 7999V. +**/ + UINT16 VccinVrMaxVoltage; + +/** Offset 0x01B8 - Post Divider (PVD) Ratio Threshold + PVD Ratio Threshold. 0: No offset. Range 0-63 +**/ + UINT8 PvdRatioThreshold; + +/** Offset 0x01B9 - Hyper Threading Enable/Disable + Enable or Disable Hyper Threading; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 HyperThreading; + +/** Offset 0x01BA - Boot frequency + Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- + 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo + is selected BIOS will start in max non-turbo mode and switch to Turbo mode. + 0:0, 1:1, 2:2 +**/ + UINT8 BootFrequency; + +/** Offset 0x01BB - Number of active cores + Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: + 2 ;3: 3 + 0:All, 1:1, 2:2, 3:3 +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x01BC - Processor Early Power On Configuration FCLK setting + 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- + 2: 400 MHz. - 3: Reserved + 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved +**/ + UINT8 FClkFrequency; + +/** Offset 0x01BD - Set JTAG power in C10 and deeper power states + False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 + and deeper power states for debug purpose. 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 JtagC10PowerGateDisable; + +/** Offset 0x01BE - BIST on Reset + Enable or Disable BIST on Reset; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 BistOnReset; + +/** Offset 0x01BF - Enable or Disable VMX + Enable or Disable VMX; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 VmxEnable; + +/** Offset 0x01C0 - CPU ratio value + CPU ratio value. Valid Range 0 to 63 +**/ + UINT8 CpuRatio; + +/** Offset 0x01C1 - Enable or Disable TME + Enable or Disable TME; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TmeEnable; + +/** Offset 0x01C2 - Enable CPU CrashLog + Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CpuCrashLogEnable; + +/** Offset 0x01C3 - CPU Run Control + Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: + No Change + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DebugInterfaceEnable; + +/** Offset 0x01C4 - CPU Run Control Lock + Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DebugInterfaceLockEnable; + +/** Offset 0x01C5 - Skip Multi-Processor Initialization + When this is skipped, boot loader must initialize processors before SilicionInit + API. 0: Initialize; 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInitPreMem; + +/** Offset 0x01C6 +**/ + UINT8 CpuPreMemRsvd[13]; + +/** Offset 0x01D3 - Skip Stop PBET Timer Enable/Disable + Skip Stop PBET Timer; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 SkipStopPbet; + +/** Offset 0x01D4 - C6DRAM power gating feature + This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM + power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating + feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. + $EN_DIS +**/ + UINT8 EnableC6Dram; + +/** Offset 0x01D5 - BiosGuard + Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable + $EN_DIS +**/ + UINT8 BiosGuard; + +/** Offset 0x01D6 +**/ + UINT8 BiosGuardToolsInterface; + +/** Offset 0x01D7 - EnableSgx + Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control + 0: Disable, 1: Enable, 2: Software Control +**/ + UINT8 EnableSgx; + +/** Offset 0x01D8 - Txt + Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable + $EN_DIS +**/ + UINT8 Txt; + +/** Offset 0x01D9 +**/ + UINT8 UnusedUpdSpace9[3]; + +/** Offset 0x01DC - PrmrrSize + Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable +**/ + UINT32 PrmrrSize; + +/** Offset 0x01E0 - TxtAcheckRequest + Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. + $EN_DIS +**/ + UINT8 TxtAcheckRequest; + +/** Offset 0x01E1 +**/ + UINT8 UnusedUpdSpace10; + +/** Offset 0x01E2 - BiosSize + Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable +**/ + UINT16 BiosSize; + +/** Offset 0x01E4 - SinitMemorySize + Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable +**/ + UINT32 SinitMemorySize; + +/** Offset 0x01E8 - TxtHeapMemorySize + Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable +**/ + UINT32 TxtHeapMemorySize; + +/** Offset 0x01EC +**/ + UINT8 UnusedUpdSpace11[4]; + +/** Offset 0x01F0 - TxtDprMemoryBase + Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable +**/ + UINT64 TxtDprMemoryBase; + +/** Offset 0x01F8 - TxtDprMemorySize + Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable +**/ + UINT32 TxtDprMemorySize; + +/** Offset 0x01FC - BiosAcmBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 BiosAcmBase; + +/** Offset 0x0200 - BiosAcmSize + Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable +**/ + UINT32 BiosAcmSize; + +/** Offset 0x0204 - TgaSize + Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable +**/ + UINT32 TgaSize; + +/** Offset 0x0208 - TxtLcpPdBase + Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable +**/ + UINT64 TxtLcpPdBase; + +/** Offset 0x0210 - TxtLcpPdSize + Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable +**/ + UINT64 TxtLcpPdSize; + +/** Offset 0x0218 - ApStartupBase + Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable +**/ + UINT32 ApStartupBase; + +/** Offset 0x021C - IsTPMPresence + IsTPMPresence default values +**/ + UINT8 IsTPMPresence; + +/** Offset 0x021D +**/ + UINT8 SecurityPreMemRsvd[16]; + +/** Offset 0x022D +**/ + UINT8 UnusedUpdSpace12[3]; + +/** Offset 0x0230 - Intel Enhanced Debug + Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied + 0 : Disable, 0x400000 : Enable +**/ + UINT32 IedSize; + +/** Offset 0x0234 - Board Type + MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile + Halo, 7=UP Server + 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server +**/ + UINT8 UserBd; + +/** Offset 0x0235 - State of X2APIC_OPT_OUT bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 X2ApicOptOut; + +/** Offset 0x0236 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table + 0=Disable/Clear, 1=Enable/Set + $EN_DIS +**/ + UINT8 DmaControlGuarantee; + +/** Offset 0x0237 +**/ + UINT8 UnusedUpdSpace13[1]; + +/** Offset 0x0238 - Base addresses for VT-d function MMIO access + Base addresses for VT-d MMIO access per VT-d engine +**/ + UINT32 VtdBaseAddress[9]; + +/** Offset 0x025C - Disable VT-d + 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) + $EN_DIS +**/ + UINT8 VtdDisable; + +/** Offset 0x025D - Internal Graphics Pre-allocated Memory + Size of memory preallocated for internal graphics. + 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, + 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, + 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB +**/ + UINT8 IgdDvmt50PreAlloc; + +/** Offset 0x025E - Internal Graphics + Enable/disable internal graphics. + $EN_DIS +**/ + UINT8 InternalGfx; + +/** Offset 0x025F - Aperture Size + Select the Aperture Size. + 0:128 MB, 1:256 MB, 2:512 MB +**/ + UINT8 ApertureSize; + +/** Offset 0x0260 - Selection of the primary display device + 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics + 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics +**/ + UINT8 PrimaryDisplay; + +/** Offset 0x0261 +**/ + UINT8 UnusedUpdSpace14[3]; + +/** Offset 0x0264 - Temporary MMIO address for GTTMMADR + The reference code will use this as Temporary MMIO address space to access GTTMMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr + to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO + + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) +**/ + UINT32 GttMmAdr; + +/** Offset 0x0268 - Temporary MMIO address for GMADR + The reference code will use this as Temporary MMIO address space to access GMADR + Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to + (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress + - 0x1) (Where ApertureSize = 256MB) +**/ + UINT32 GmAdr; + +/** Offset 0x026C - Selection of iGFX GTT Memory size + 1=2MB, 2=4MB, 3=8MB, Default is 3 + 1:2MB, 2:4MB, 3:8MB +**/ + UINT16 GttSize; + +/** Offset 0x026E - Selection of PSMI Region size + 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 + 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB +**/ + UINT8 PsmiRegionSize; + +/** Offset 0x026F - Selection of PSMI Support On/Off + 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support + $EN_DIS +**/ + UINT8 GtPsmiSupport; + +/** Offset 0x0270 - Panel Power Enable + Control for enabling/disabling VDD force bit (Required only for early enabling of + eDP panel). 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 PanelPowerEnable; + +/** Offset 0x0271 - PCIe root port Function number for Hybrid Graphics dGPU + Root port Index number to indicate which PCIe root port has dGPU +**/ + UINT8 RootPortIndex; + +/** Offset 0x0272 +**/ + UINT8 UnusedUpdSpace15[2]; + +/** Offset 0x0274 - Hybrid Graphics GPIO information for PEG 0 + Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs +**/ + UINT32 SaRtd3Pcie0Gpio[24]; + +/** Offset 0x02D4 - Hybrid Graphics GPIO information for PEG 1 + Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs +**/ + UINT32 SaRtd3Pcie1Gpio[24]; + +/** Offset 0x0334 - Hybrid Graphics GPIO information for PEG 2 + Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs +**/ + UINT32 SaRtd3Pcie2Gpio[24]; + +/** Offset 0x0394 - Hybrid Graphics GPIO information for PEG 3 + Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs +**/ + UINT32 SaRtd3Pcie3Gpio[24]; + +/** Offset 0x03F4 - HG dGPU Power Delay + HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is + 300=300 microseconds +**/ + UINT16 HgDelayAfterPwrEn; + +/** Offset 0x03F6 - HG dGPU Reset Delay + HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 + microseconds +**/ + UINT16 HgDelayAfterHoldReset; + +/** Offset 0x03F8 - MMIO size adjustment for AUTO mode + Positive number means increasing MMIO size, Negative value means decreasing MMIO + size: 0 (Default)=no change to AUTO mode MMIO size +**/ + UINT16 MmioSizeAdjustment; + +/** Offset 0x03FA - MMIO Size + Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB +**/ + UINT16 MmioSize; + +/** Offset 0x03FC - Tseg Size + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build + 0x0400000:4MB, 0x01000000:16MB +**/ + UINT32 TsegSize; + +/** Offset 0x0400 - Enable/Disable MRC TXT dependency + When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): + MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization + $EN_DIS +**/ + UINT8 TxtImplemented; + +/** Offset 0x0401 - Skip external display device scanning + Enable: Do not scan for external display device, Disable (Default): Scan external + display devices + $EN_DIS +**/ + UINT8 SkipExtGfxScan; + +/** Offset 0x0402 - Generate BIOS Data ACPI Table + Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it + $EN_DIS +**/ + UINT8 BdatEnable; + +/** Offset 0x0403 - BdatTestType + Indicates the type of Memory Training data to populate into the BDAT ACPI table. + 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D +**/ + UINT8 BdatTestType; + +/** Offset 0x0404 - Detect External Graphics device for LegacyOpROM + Detect and report if external graphics device only support LegacyOpROM or not (to + support CSM auto-enable). Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 ScanExtGfxForLegacyOpRom; + +/** Offset 0x0405 - Lock PCU Thermal Management registers + Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 + $EN_DIS +**/ + UINT8 LockPTMregs; + +/** Offset 0x0406 - Enable/Disable DMI GEN3 Static EQ Phase1 programming + Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 DmiGen3ProgramStaticEq; + +/** Offset 0x0407 - Enable/Disable PEG 0 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + UINT8 Peg0Enable; + +/** Offset 0x0408 - Enable/Disable PEG 1 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + UINT8 Peg1Enable; + +/** Offset 0x0409 - Enable/Disable PEG 2 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + UINT8 Peg2Enable; + +/** Offset 0x040A - Enable/Disable PEG 3 + Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits + it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise + 0:Disable, 1:Enable, 2:AUTO +**/ + UINT8 Peg3Enable; + +/** Offset 0x040B - PEG 0 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 Peg0MaxLinkSpeed; + +/** Offset 0x040C - PEG 1 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 Peg1MaxLinkSpeed; + +/** Offset 0x040D - PEG 2 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 Peg2MaxLinkSpeed; + +/** Offset 0x040E - PEG 3 Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 Peg3MaxLinkSpeed; + +/** Offset 0x040F - PEG 0 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 + 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 +**/ + UINT8 Peg0MaxLinkWidth; + +/** Offset 0x0410 - PEG 1 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2, (0x3):Limit Link to x4 + 0:Auto, 1:x1, 2:x2, 3:x4 +**/ + UINT8 Peg1MaxLinkWidth; + +/** Offset 0x0411 - PEG 2 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2 + 0:Auto, 1:x1, 2:x2 +**/ + UINT8 Peg2MaxLinkWidth; + +/** Offset 0x0412 - PEG 3 Max Link Width + Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): + Limit Link to x2 + 0:Auto, 1:x1, 2:x2 +**/ + UINT8 Peg3MaxLinkWidth; + +/** Offset 0x0413 - Power down unused lanes on PEG 0 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + UINT8 Peg0PowerDownUnusedLanes; + +/** Offset 0x0414 - Power down unused lanes on PEG 1 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + UINT8 Peg1PowerDownUnusedLanes; + +/** Offset 0x0415 - Power down unused lanes on PEG 2 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + UINT8 Peg2PowerDownUnusedLanes; + +/** Offset 0x0416 - Power down unused lanes on PEG 3 + (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based + on the max possible link width + 0:No power saving, 1:Auto +**/ + UINT8 Peg3PowerDownUnusedLanes; + +/** Offset 0x0417 - PCIe ASPM programming will happen in relation to the Oprom + Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): + Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after + Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume + 0:Before, 1:After +**/ + UINT8 InitPcieAspmAfterOprom; + +/** Offset 0x0418 - PCIe Disable Spread Spectrum Clocking + PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, + Disable SSC(0X1) - Disable SSC per platform design or for compliance testing + 0:Normal Operation, 1:Disable SSC +**/ + UINT8 PegDisableSpreadSpectrumClocking; + +/** Offset 0x0419 - DMI Gen3 Root port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 DmiGen3RootPortPreset[8]; + +/** Offset 0x0421 - DMI Gen3 End port preset values per lane + Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 DmiGen3EndPointPreset[8]; + +/** Offset 0x0429 - DMI Gen3 End port Hint values per lane + Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 DmiGen3EndPointHint[8]; + +/** Offset 0x0431 - DMI Gen3 RxCTLEp per-Bundle control + Range: 0-15, 0 is default for each bundle, must be specified based upon platform design +**/ + UINT8 DmiGen3RxCtlePeaking[4]; + +/** Offset 0x0435 - PEG Gen3 RxCTLEp per-Bundle control + Range: 0-15, 12 is default for each bundle, must be specified based upon platform design +**/ + UINT8 PegGen3RxCtlePeaking[10]; + +/** Offset 0x043F +**/ + UINT8 UnusedUpdSpace16; + +/** Offset 0x0440 - Memory data pointer for saved preset search results + The reference code will store the Gen3 Preset Search results in the SaDataHob's + PegData structure (SA_PEG_DATA) and platform code can save/restore this data to + skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 +**/ + UINT32 PegDataPtr; + +/** Offset 0x0444 - PEG PERST# GPIO information + The reference code will use the information in this structure in order to reset + PCIe Gen3 devices during equalization, if necessary +**/ + UINT8 PegGpioData[28]; + +/** Offset 0x0460 - DeEmphasis control for DMI + DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB + 0: -6dB, 1: -3.5dB +**/ + UINT8 DmiDeEmphasis; + +/** Offset 0x0461 - PCIe Hot Plug Enable/Disable per port + 0(Default): Disable, 1: Enable +**/ + UINT8 PegRootPortHPE[4]; + +/** Offset 0x0465 - DMI Max Link Speed + Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 + Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 +**/ + UINT8 DmiMaxLinkSpeed; + +/** Offset 0x0466 - DMI Equalization Phase 2 + DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): + AUTO - Use the current default method + 0:Disable phase2, 1:Enable phase2, 2:Auto +**/ + UINT8 DmiGen3EqPh2Enable; + +/** Offset 0x0467 - DMI Gen3 Equalization Phase3 + DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 DmiGen3EqPh3Method; + +/** Offset 0x0468 - Phase2 EQ enable on the PEG 0:1:0. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Peg0Gen3EqPh2Enable; + +/** Offset 0x0469 - Phase2 EQ enable on the PEG 0:1:1. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Peg1Gen3EqPh2Enable; + +/** Offset 0x046A - Phase2 EQ enable on the PEG 0:1:2. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Peg2Gen3EqPh2Enable; + +/** Offset 0x046B - Phase2 EQ enable on the PEG 0:1:3. + Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): + Enable phase 2, Auto(0x2)(Default): Use the current default method + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Peg3Gen3EqPh2Enable; + +/** Offset 0x046C - Phase3 EQ method on the PEG 0:1:0. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 Peg0Gen3EqPh3Method; + +/** Offset 0x046D - Phase3 EQ method on the PEG 0:1:1. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 Peg1Gen3EqPh3Method; + +/** Offset 0x046E - Phase3 EQ method on the PEG 0:1:2. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 Peg2Gen3EqPh3Method; + +/** Offset 0x046F - Phase3 EQ method on the PEG 0:1:3. + PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, + HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software + Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static + EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just + Phase1), Disabled(0x4): Bypass Equalization Phase 3 + 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 +**/ + UINT8 Peg3Gen3EqPh3Method; + +/** Offset 0x0470 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static + Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 PegGen3ProgramStaticEq; + +/** Offset 0x0471 - PEG Gen3 SwEq Always Attempt + Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): + Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test + and generate new EQ values every boot, not recommended + 0:Disable, 1:Enable +**/ + UINT8 Gen3SwEqAlwaysAttempt; + +/** Offset 0x0472 - Select number of TxEq presets to test in the PCIe/DMI SwEq + Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test + Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the + current default method (Default)Auto will test Presets 7, 3, and 5. It is possible + for this default to change over time;using Auto will ensure Reference Code always + uses the latest default settings + 0:P7 P3 P5, 1:P0 to P9, 2:Auto +**/ + UINT8 Gen3SwEqNumberOfPresets; + +/** Offset 0x0473 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq + Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization + Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): + Use the current default + 0:Disable, 1:Enable, 2:Auto +**/ + UINT8 Gen3SwEqEnableVocTest; + +/** Offset 0x0474 - PCIe Rx Compliance Testing Mode + Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): + PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; + it should only be set when doing PCIe compliance testing + $EN_DIS +**/ + UINT8 PegRxCemTestingMode; + +/** Offset 0x0475 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled + the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 +**/ + UINT8 PegRxCemLoopbackLane; + +/** Offset 0x0476 - Generate PCIe BDAT Margin Table + Set this policy to enable the generation and addition of PCIe margin data to the + BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin + data generation, Enable(0x1): Generate PCIe BDAT margin data + $EN_DIS +**/ + UINT8 PegGenerateBdatMarginTable; + +/** Offset 0x0477 - PCIe Non-Protocol Awareness for Rx Compliance Testing + Set this policy to enable the generation and addition of PCIe margin data to the + BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, + Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for + compliance testing + $EN_DIS +**/ + UINT8 PegRxCemNonProtocolAwareness; + +/** Offset 0x0478 - PCIe Override RxCTLE + Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): + Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE + peak values unmodified + $EN_DIS +**/ + UINT8 PegGen3RxCtleOverride; + +/** Offset 0x0479 - PEG Gen3 Root port preset values per lane + Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane +**/ + UINT8 PegGen3RootPortPreset[20]; + +/** Offset 0x048D - PEG Gen3 End port preset values per lane + Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane +**/ + UINT8 PegGen3EndPointPreset[20]; + +/** Offset 0x04A1 - PEG Gen3 End port Hint values per lane + Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane +**/ + UINT8 PegGen3EndPointHint[20]; + +/** Offset 0x04B5 +**/ + UINT8 UnusedUpdSpace17; + +/** Offset 0x04B6 - Jitter Dwell Time for PCIe Gen3 Software Equalization + Range: 0-65535, default is 1000. @warning Do not change from the default +**/ + UINT16 Gen3SwEqJitterDwellTime; + +/** Offset 0x04B8 - Jitter Error Target for PCIe Gen3 Software Equalization + Range: 0-65535, default is 1. @warning Do not change from the default +**/ + UINT16 Gen3SwEqJitterErrorTarget; + +/** Offset 0x04BA - VOC Dwell Time for PCIe Gen3 Software Equalization + Range: 0-65535, default is 10000. @warning Do not change from the default +**/ + UINT16 Gen3SwEqVocDwellTime; + +/** Offset 0x04BC - VOC Error Target for PCIe Gen3 Software Equalization + Range: 0-65535, default is 2. @warning Do not change from the default +**/ + UINT16 Gen3SwEqVocErrorTarget; + +/** Offset 0x04BE - Enable/Disable SA IPU + Enable(Default): Enable SA IPU, Disable: Disable SA IPU + $EN_DIS +**/ + UINT8 SaIpuEnable; + +/** Offset 0x04BF - IPU IMR Configuration + 0:IPU Camera, 1:IPU Gen Default is 0 + 0:IPU Camera, 1:IPU Gen +**/ + UINT8 SaIpuImrConfiguration; + +/** Offset 0x04C0 - IMGU CLKOUT Configuration + The configuration of IMGU CLKOUT, 0: Disable;1: Enable. + $EN_DIS +**/ + UINT8 ImguClkOutEn[5]; + +/** Offset 0x04C5 - CPU Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode +**/ + UINT8 CpuTraceHubMode; + +/** Offset 0x04C6 - CPU Trace Hub Memory Region 0 + CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg0Size; + +/** Offset 0x04C7 - CPU Trace Hub Memory Region 1 + CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 CpuTraceHubMemReg1Size; + +/** Offset 0x04C8 - Enable/Disable SA OcSupport + Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport + $EN_DIS +**/ + UINT8 SaOcSupport; + +/** Offset 0x04C9 - GT slice Voltage Mode + 0(Default): Adaptive, 1: Override + 0: Adaptive, 1: Override +**/ + UINT8 GtVoltageMode; + +/** Offset 0x04CA - Maximum GTs turbo ratio override + 0(Default)=Minimal/Auto, 42=Maximum +**/ + UINT8 GtMaxOcRatio; + +/** Offset 0x04CB +**/ + UINT8 UnusedUpdSpace18; + +/** Offset 0x04CC - The voltage offset applied to GT slice + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 GtVoltageOffset; + +/** Offset 0x04CE - The GT slice voltage override which is applied to the entire range of GT frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtVoltageOverride; + +/** Offset 0x04D0 - adaptive voltage applied during turbo frequencies + 0(Default)=Minimal, 2000=Maximum +**/ + UINT16 GtExtraTurboVoltage; + +/** Offset 0x04D2 - voltage offset applied to the SA + 0(Default)=Minimal, 1000=Maximum +**/ + UINT16 SaVoltageOffset; + +/** Offset 0x04D4 - Realtime Memory Timing + 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform + realtime memory timing changes after MRC_DONE. + 0: Disabled, 1: Enabled +**/ + UINT8 RealtimeMemoryTiming; + +/** Offset 0x04D5 - TCSS Thunderbolt PCIE Root Port 0 Enable + Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie0En; + +/** Offset 0x04D6 - TCSS Thunderbolt PCIE Root Port 1 Enable + Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie1En; + +/** Offset 0x04D7 - TCSS Thunderbolt PCIE Root Port 2 Enable + Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie2En; + +/** Offset 0x04D8 - TCSS Thunderbolt PCIE Root Port 3 Enable + Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssItbtPcie3En; + +/** Offset 0x04D9 - TCSS USB HOST (xHCI) Enable + Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below + $EN_DIS +**/ + UINT8 TcssXhciEn; + +/** Offset 0x04DA - TCSS USB DEVICE (xDCI) Enable + Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled + $EN_DIS +**/ + UINT8 TcssXdciEn; + +/** Offset 0x04DB - TCSS DMA0 Enable + Set TCSS DMA0. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma0En; + +/** Offset 0x04DC - TCSS DMA1 Enable + Set TCSS DMA1. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssDma1En; + +/** Offset 0x04DD - This is policy to control iTBT PCIe Multiple Segment setting. + When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the + TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PcieMultipleSegmentEnabled; + +/** Offset 0x04DE - Enable/Disable SA CRID + Enable: SA CRID, Disable (Default): SA CRID + $EN_DIS +**/ + UINT8 CridEnable; + +/** Offset 0x04DF - TCSS USB Port Enable + Bitmap for per port enabling +**/ + UINT8 UsbTcPortEnPreMem; + +/** Offset 0x04E0 - PEG IMR support + This option configures the IMR support for PEG.(def=Disable) + $EN_DIS +**/ + UINT8 PegImrEnable; + +/** Offset 0x04E1 - PEG Root port number for IMR. + PEG Root port number for IMR. +**/ + UINT8 PegImrRpSelection; + +/** Offset 0x04E2 - PEG IMR size + The size of IMR to be allocated for PEG EndPoint device +**/ + UINT16 PegImrSize; + +/** Offset 0x04E4 - Enable above 4GB MMIO resource support + Enable/disable above 4GB MMIO resource support + $EN_DIS +**/ + UINT8 EnableAbove4GBMmio; + +/** Offset 0x04E5 +**/ + UINT8 SaPreMemRsvd[31]; + +/** Offset 0x0504 - HECI Timeouts + 0: Disable, 1: Enable (Default) timeout check for HECI + $EN_DIS +**/ + UINT8 HeciTimeouts; + +/** Offset 0x0505 - Force ME DID Init Status + Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set + ME DID init stat value + $EN_DIS +**/ + UINT8 DidInitStat; + +/** Offset 0x0506 - CPU Replaced Polling Disable + Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop + $EN_DIS +**/ + UINT8 DisableCpuReplacedPolling; + +/** Offset 0x0507 - ME DID Message + Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent + the DID message from being sent) + $EN_DIS +**/ + UINT8 SendDidMsg; + +/** Offset 0x0508 - Check HECI message before send + Test, 0: disable, 1: enable, Enable/Disable message check. + $EN_DIS +**/ + UINT8 DisableMessageCheck; + +/** Offset 0x0509 - Skip MBP HOB + Test, 0: disable, 1: enable, Enable/Disable MOB HOB. + $EN_DIS +**/ + UINT8 SkipMbpHob; + +/** Offset 0x050A - HECI2 Interface Communication + Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. + $EN_DIS +**/ + UINT8 HeciCommunication2; + +/** Offset 0x050B - Enable KT device + Test, 0: disable, 1: enable, Enable or Disable KT device. + $EN_DIS +**/ + UINT8 KtDeviceEnable; + +/** Offset 0x050C - HECI1 BAR address + BAR address of HECI1 +**/ + UINT32 Heci1BarAddress; + +/** Offset 0x0510 - HECI2 BAR address + BAR address of HECI2 +**/ + UINT32 Heci2BarAddress; + +/** Offset 0x0514 - HECI3 BAR address + BAR address of HECI3 +**/ + UINT32 Heci3BarAddress; + +/** Offset 0x0518 +**/ + UINT8 MePreMemRsvd[16]; + +/** Offset 0x0528 - PCH Trace Hub Mode + Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' + if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. + 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode +**/ + UINT8 PchTraceHubMode; + +/** Offset 0x0529 - PCH Trace Hub Memory Region 0 buffer Size + Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg0Size; + +/** Offset 0x052A - PCH Trace Hub Memory Region 1 buffer Size + Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, + 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. + 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB +**/ + UINT8 PchTraceHubMemReg1Size; + +/** Offset 0x052B - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + UINT8 SmbusEnable; + +/** Offset 0x052C - Enable SMBus ARP support + Enable SMBus ARP support. + $EN_DIS +**/ + UINT8 SmbusArpEnable; + +/** Offset 0x052D - Smbus dynamic power gating + Disable or Enable Smbus dynamic power gating. + $EN_DIS +**/ + UINT8 SmbusDynamicPowerGating; + +/** Offset 0x052E - SMBUS SPD Write Disable + Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write + Disable bit. For security recommendations, SPD write disable bit must be set. + $EN_DIS +**/ + UINT8 SmbusSpdWriteDisable; + +/** Offset 0x052F - Enable SMBus Alert Pin + Enable SMBus Alert Pin. + $EN_DIS +**/ + UINT8 PchSmbAlertEnable; + +/** Offset 0x0530 - SMBUS Base Address + SMBUS Base Address (IO space). +**/ + UINT16 PchSmbusIoBase; + +/** Offset 0x0532 - Number of RsvdSmbusAddressTable. + The number of elements in the RsvdSmbusAddressTable. +**/ + UINT8 PchNumRsvdSmbusAddresses; + +/** Offset 0x0533 +**/ + UINT8 UnusedUpdSpace19; + +/** Offset 0x0534 - Point of RsvdSmbusAddressTable + Array of addresses reserved for non-ARP-capable SMBus devices. +**/ + UINT32 RsvdSmbusAddressTablePtr; + +/** Offset 0x0538 - DCI Enable + Determine if to enable DCI debug from host + $EN_DIS +**/ + UINT8 DciEn; + +/** Offset 0x0539 - Enable DCI ModPHY Pwoer Gate + Enable ModPHY Pwoer Gate when DCI is enabled + $EN_DIS +**/ + UINT8 DciModphyPg; + +/** Offset 0x053A - DCI DbC Mode + Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: + Set both USB2/3DBCEN; No Change: Comply with HW value,for PCH-LP ICL U/Y board + with D0 stepping need to Disable it by default + 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change +**/ + UINT8 DciDbcMode; + +/** Offset 0x053B - USB3 Type-C UFP2DFP Kernel/Platform Debug Support + This BIOS option enables kernel and platform debug for USB3 interface over a UFP + Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. + 0:Disabled, 1:Enabled, 2:No Change +**/ + UINT8 DciUsb3TypecUfpDbg; + +/** Offset 0x053C - Enable PCIE RP Mask + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 + for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpEnableMask; + +/** Offset 0x0540 - Enable PCIe IMR + 0:Disable, 1:Enable + $EN_DIS +**/ + UINT8 PcieImrEnabled; + +/** Offset 0x0541 +**/ + UINT8 UnusedUpdSpace20; + +/** Offset 0x0542 - Size of PCIe IMR. + Size of PCIe IMR in megabytes +**/ + UINT16 PcieImrSize; + +/** Offset 0x0544 - Root port number for IMR. + Root port number for IMR. +**/ + UINT8 ImrRpSelection; + +/** Offset 0x0545 - Enable PCH HSIO PCIE Rx Set Ctle + Enable PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtleEnable[24]; + +/** Offset 0x055D - PCH HSIO PCIE Rx Set Ctle Value + PCH PCIe Gen 3 Set CTLE Value. +**/ + UINT8 PchPcieHsioRxSetCtle[24]; + +/** Offset 0x0575 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; + +/** Offset 0x058D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; + +/** Offset 0x05A5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; + +/** Offset 0x05BD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; + +/** Offset 0x05D5 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; + +/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value + PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; + +/** Offset 0x0605 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; + +/** Offset 0x061D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value + PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen1DeEmph[24]; + +/** Offset 0x0635 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; + +/** Offset 0x064D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; + +/** Offset 0x0665 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; + +/** Offset 0x067D - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value + PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. +**/ + UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; + +/** Offset 0x0695 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; + +/** Offset 0x069D - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen1EqBoostMag[8]; + +/** Offset 0x06A5 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; + +/** Offset 0x06AD - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen2EqBoostMag[8]; + +/** Offset 0x06B5 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; + +/** Offset 0x06BD - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value + PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. +**/ + UINT8 PchSataHsioRxGen3EqBoostMag[8]; + +/** Offset 0x06C5 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; + +/** Offset 0x06CD - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen1DownscaleAmp[8]; + +/** Offset 0x06D5 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; + +/** Offset 0x06DD - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen2DownscaleAmp[8]; + +/** Offset 0x06E5 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; + +/** Offset 0x06ED - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value + PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. +**/ + UINT8 PchSataHsioTxGen3DownscaleAmp[8]; + +/** Offset 0x06F5 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen1DeEmphEnable[8]; + +/** Offset 0x06FD - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen1DeEmph[8]; + +/** Offset 0x0705 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen2DeEmphEnable[8]; + +/** Offset 0x070D - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen2DeEmph[8]; + +/** Offset 0x0715 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override + 0: Disable; 1: Enable. +**/ + UINT8 PchSataHsioTxGen3DeEmphEnable[8]; + +/** Offset 0x071D - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting + PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. +**/ + UINT8 PchSataHsioTxGen3DeEmph[8]; + +/** Offset 0x0725 - ChipsetInit HECI message + DEPRECATED + $EN_DIS +**/ + UINT8 ChipsetInitMessage; + +/** Offset 0x0726 - Bypass ChipsetInit sync reset. + DEPRECATED + $EN_DIS +**/ + UINT8 BypassPhySyncReset; + +/** Offset 0x0727 - PCH LPC Enhance the port 8xh decoding + Original LPC only decodes one byte of port 80h. + $EN_DIS +**/ + UINT8 PchLpcEnhancePort8xhDecoding; + +/** Offset 0x0728 - PCH Port80 Route + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + $EN_DIS +**/ + UINT8 PchPort80Route; + +/** Offset 0x0729 - Disable and Lock Watch Dog Register + Set 1 to clear WDT status, then disable and lock WDT registers. + $EN_DIS +**/ + UINT8 WdtDisableAndLock; + +/** Offset 0x072A - Enable Intel HD Audio (Azalia) + 0: Disable, 1: Enable (Default) Azalia controller + $EN_DIS +**/ + UINT8 PchHdaEnable; + +/** Offset 0x072B - Enable PCH ISH Controller + 0: Disable, 1: Enable (Default) ISH Controller + $EN_DIS +**/ + UINT8 PchIshEnable; + +/** Offset 0x072C - Platform Debug Consent + To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. + Enabling this BIOS option may alter the default value of other debug-related BIOS + options.\Manual: Do not use Platform Debug Consent to override other debug-relevant + policies, but the user must set each debug option manually, aimed at advanced users.\n + Note: DCI OOB (aka BSSB) uses CCA probe + 0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled + (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual +**/ + UINT8 PlatformDebugConsent; + +/** Offset 0x072D - Debug Interfaces + Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, + BIT2 - Not used. +**/ + UINT8 PcdDebugInterfaceFlags; + +/** Offset 0x072E - Serial Io Uart Debug Controller Number + Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT + Core interface, it cannot be used for debug purpose. + 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 +**/ + UINT8 SerialIoUartDebugControllerNumber; + +/** Offset 0x072F - Serial Io Uart Debug Auto Flow + Enables UART hardware flow control, CTS and RTS lines. + $EN_DIS +**/ + UINT8 SerialIoUartDebugAutoFlow; + +/** Offset 0x0730 - Serial Io Uart Debug BaudRate + Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, + 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 +**/ + UINT32 SerialIoUartDebugBaudRate; + +/** Offset 0x0734 - Serial Io Uart Debug Parity + Set default Parity. + 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartDebugParity; + +/** Offset 0x0735 - Serial Io Uart Debug Stop Bits + Set default stop bits. + 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits +**/ + UINT8 SerialIoUartDebugStopBits; + +/** Offset 0x0736 - Serial Io Uart Debug Data Bits + Set default word length. 0: Default, 5,6,7,8 + 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS +**/ + UINT8 SerialIoUartDebugDataBits; + +/** Offset 0x0737 - ISA Serial Base selection + Select ISA Serial Base address. Default is 0x3F8. + 0:0x3F8, 1:0x2F8 +**/ + UINT8 PcdIsaSerialUartBase; + +/** Offset 0x0738 - PcdSerialDebugBaudRate + Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. + 3:9600, 4:19200, 6:56700, 7:115200 +**/ + UINT8 PcdSerialDebugBaudRate; + +/** Offset 0x0739 +**/ + UINT8 UnusedUpdSpace21; + +/** Offset 0x073A - Post Code Output Port + This option configures Post Code Output Port +**/ + UINT16 PostCodeOutputPort; + +/** Offset 0x073C +**/ + UINT8 PchPreMemRsvd[32]; + +/** Offset 0x075C - Write Drive Strength/Equalization 2D + Enables/Disable Write Drive Strength/Equalization 2D + $EN_DIS +**/ + UINT8 WRDSEQT; + +/** Offset 0x075D +**/ + UINT8 UnusedUpdSpace22[4]; + +/** Offset 0x0761 +**/ + UINT8 ReservedFspmUpd[15]; +} FSP_M_CONFIG; /** Fsp M UPD Configuration **/ @@ -66,17 +3040,13 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; -/** Offset 0x051F +/** Offset 0x0770 **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace23[6]; -/** Offset 0x0520 +/** Offset 0x0776 **/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x05BC -**/ - UINT32 UpdTerminator; + UINT16 UpdTerminator; } FSPM_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h index 37356a142a..4aa5008356 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2019, Intel Corporation. All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -37,15 +37,3552 @@ are permitted provided that the following conditions are met: #pragma pack(1) + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + + /** Fsp S Configuration **/ typedef struct { -} FSP_S_CONFIG; -/** Fsp S Test Configuration +/** Offset 0x0020 - Si Config CSM Flag. + Platform specific common policies that used by several silicon components. CSM status flag. + $EN_DIS **/ -typedef struct { -} FSP_S_TEST_CONFIG; + UINT8 SiCsmFlag; + +/** Offset 0x0021 +**/ + UINT8 UnusedUpdSpace0[3]; + +/** Offset 0x0024 - SVID SDID table Poniter. + The address of the table of SVID SDID to customize each SVID SDID entry. +**/ + UINT32 SiSsidTablePtr; + +/** Offset 0x0028 - Number of ssid table. + SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. +**/ + UINT16 SiNumberOfSsidTableEntry; + +/** Offset 0x002A +**/ + UINT8 SiPostMemRsvd[16]; + +/** Offset 0x003A +**/ + UINT8 UnusedUpdSpace1[2]; + +/** Offset 0x003C - MicrocodeRegionBase + Memory Base of Microcode Updates +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0040 - MicrocodeRegionSize + Size of Microcode Updates +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0044 - Enable or Disable TXT + Enable or Disable TXT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TxtEnable; + +/** Offset 0x0045 - Advanced Encryption Standard (AES) feature + Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 AesEnable; + +/** Offset 0x0046 - Deprecated Skip Multi-Processor Initialization + {@deprecated SkipMpInit has been moved to FspmUpd as SkipMpInitPreMem. 0: Initialize; + 1: Skip + $EN_DIS +**/ + UINT8 SkipMpInit; + +/** Offset 0x0047 - PpinSupport to view Protected Processor Inventory Number + Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this + flag is set) for PPIN Support + 0: Disable, 1: Enable, 2: Auto +**/ + UINT8 PpinSupport; + +/** Offset 0x0048 - Turbo Mode + Enable/Disable Turbo mode. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 TurboMode; + +/** Offset 0x0049 - Power State 3 enable/disable + PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. + For all VR Indexes +**/ + UINT8 Psi3Enable; + +/** Offset 0x004A - Power State 4 enable/disable + PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For + all VR Indexes +**/ + UINT8 Psi4Enable; + +/** Offset 0x004B +**/ + UINT8 UnusedUpdSpace2; + +/** Offset 0x004C - Imon slope correction + PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. + Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes +**/ + UINT16 ImonSlope; + +/** Offset 0x004E - Imon offset correction + PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. + Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto +**/ + UINT16 ImonOffset; + +/** Offset 0x0050 - Enable/Disable BIOS configuration of VR + Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes +**/ + UINT8 VrConfigEnable; + +/** Offset 0x0051 - Thermal Design Current enable/disable + PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: + Enable.For all VR Indexes +**/ + UINT8 TdcEnable; + +/** Offset 0x0052 - HECI3 state + PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. + Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms + , 8 - 8ms , 10 - 10ms.For all VR Indexe +**/ + UINT8 TdcTimeWindow; + +/** Offset 0x0053 - Thermal Design Current Lock + PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For + all VR Indexes +**/ + UINT8 TdcLock; + +/** Offset 0x0054 - Thermal Design Current current limit + PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. + Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes +**/ + UINT16 TdcPowerLimit; + +/** Offset 0x0056 - AcLoadline + PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249. Intel Recommended Defaults vary by domain and SKU. +**/ + UINT16 AcLoadline; + +/** Offset 0x0058 - DcLoadline + PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is + 0-6249.Intel Recommended Defaults vary by domain and SKU. +**/ + UINT16 DcLoadline; + +/** Offset 0x005A - Power State 1 Threshold current + PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi1Threshold; + +/** Offset 0x005C - Power State 2 Threshold current + PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi2Threshold; + +/** Offset 0x005E - Power State 3 Threshold current + PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. +**/ + UINT16 Psi3Threshold; + +/** Offset 0x0060 - Icc Max limit + PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A +**/ + UINT16 IccMax; + +/** Offset 0x0062 - VR Voltage Limit + PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. +**/ + UINT16 VrVoltageLimit; + +/** Offset 0x0064 - Platform Psys slope correction + PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in + 1/100 increment values. Range is 0-200. 125 = 1.25 +**/ + UINT8 PsysSlope; + +/** Offset 0x0065 - Platform Psys offset correction + PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, + Range 0-255. Value of 100 = 100/4 = 25 offset +**/ + UINT8 PsysOffset; + +/** Offset 0x0066 - Acoustic Noise Mitigation feature + Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program + slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: + Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 AcousticNoiseMitigation; + +/** Offset 0x0067 - Pre Wake Randomization time + PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum pre-wake randomization + time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled. + Range 0-255 0. +**/ + UINT8 PreWake; + +/** Offset 0x0068 - Ramp Up Randomization time + PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum Ramp Up randomization + time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range + 0-255 0. +**/ + UINT8 RampUp; + +/** Offset 0x0069 - Ramp Down Randomization time + PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum Ramp Down randomization + time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range + 0-255 0. +**/ + UINT8 RampDown; + +/** Offset 0x006A - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain + Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation + feature enabled. 0: False; 1: True + $EN_DIS +**/ + UINT8 FastPkgCRampDisableFivr; + +/** Offset 0x006B - Slew Rate configuration for Deep Package C States for VR FIVR domain + Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic + Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 + 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 +**/ + UINT8 SlowSlewRateForFivr; + +/** Offset 0x006C - Enable VR specific mailbox command + VR specific mailbox commands. 00b - no VR specific command sent. 01b - A + VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific + command sent for PS4 exit issue. 11b - Reserved. + $EN_DIS +**/ + UINT8 SendVrMbxCmd; + +/** Offset 0x006D +**/ + UINT8 UnusedUpdSpace3; + +/** Offset 0x006E - FIVR RFI Frequency + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: + Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; + 0-1535 (Up to 153.5MHz) for 19MHz clock. +**/ + UINT16 FivrRfiFrequency; + +/** Offset 0x0070 - FIVR RFI Spread Spectrum + PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments, with range of + 0.2% to 10%. 2: 0.2%; Range: 0.2% to 10.0% (2-100). +**/ + UINT8 FivrSpreadSpectrum; + +/** Offset 0x0071 - Enable or Disable Minimum Voltage Override + Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 EnableMinVoltageOverride; + +/** Offset 0x0072 - Min Voltage for C8 + PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = + 1. Range 0 to 1999mV. 0: 0mV +**/ + UINT16 MinVoltageC8; + +/** Offset 0x0074 - Min Voltage for Runtime + PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride + = 1. Range 0 to 1999mV. 0: 0mV +**/ + UINT16 MinVoltageRuntime; + +/** Offset 0x0076 - Enable or Disable MLC Streamer Prefetcher + Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MlcStreamerPrefetcher; + +/** Offset 0x0077 - Enable or Disable MLC Spatial Prefetcher + Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 MlcSpatialPrefetcher; + +/** Offset 0x0078 - Enable or Disable Monitor /MWAIT instructions + Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MonitorMwaitEnable; + +/** Offset 0x0079 - Control on Processor Trace output scheme + Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. + 0: Single Range Output, 1: ToPA Output +**/ + UINT8 ProcessorTraceOutputScheme; + +/** Offset 0x007A - Enable or Disable Processor Trace feature + Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcessorTraceEnable; + +/** Offset 0x007B +**/ + UINT8 UnusedUpdSpace4[5]; + +/** Offset 0x0080 - Base of memory region allocated for Processor Trace + Base address of memory region allocated for Processor Trace. Processor Trace requires + 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable +**/ + UINT64 ProcessorTraceMemBase; + +/** Offset 0x0088 - Memory region allocation for Processor Trace + Length in bytes of memory region allocated for Processor Trace. Processor Trace + requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable +**/ + UINT32 ProcessorTraceMemLength; + +/** Offset 0x008C - Enable or Disable Voltage Optimization feature + Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 VoltageOptimization; + +/** Offset 0x008D - Set Three Strike Counter Disable + False (default): Three Strike counter will be incremented and True: Prevents Three + Strike counter from incrementing; 0: False; 1: True. + 0: False, 1: True +**/ + UINT8 ThreeStrikeCounterDisable; + +/** Offset 0x008E - Enable or Disable initialization of machine check registers + Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MachineCheckEnable; + +/** Offset 0x008F - AP Idle Manner of waiting for SIPI + AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. + 1: HALT loop, 2: MWAIT loop, 3: RUN loop +**/ + UINT8 ApIdleManner; + +/** Offset 0x0090 - 1-Core Ratio Limit + 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal + to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 +**/ + UINT8 OneCoreRatioLimit; + +/** Offset 0x0091 - 2-Core Ratio Limit + 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 TwoCoreRatioLimit; + +/** Offset 0x0092 - 3-Core Ratio Limit + 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 ThreeCoreRatioLimit; + +/** Offset 0x0093 - 4-Core Ratio Limit + 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 +**/ + UINT8 FourCoreRatioLimit; + +/** Offset 0x0094 - 5-Core Ratio Limit + 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 FiveCoreRatioLimit; + +/** Offset 0x0095 - 6-Core Ratio Limit + 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 SixCoreRatioLimit; + +/** Offset 0x0096 - 7-Core Ratio Limit + 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 SevenCoreRatioLimit; + +/** Offset 0x0097 - 8-Core Ratio Limit + 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused + 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal + to 1-Core Ratio Limit.Range is 0 to 83 + 0x0:0xFF +**/ + UINT8 EightCoreRatioLimit; + +/** Offset 0x0098 - Enable or Disable HWP + Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; + 2-3:Reserved + $EN_DIS +**/ + UINT8 Hwp; + +/** Offset 0x0099 - Hardware Duty Cycle Control + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved + $EN_DIS +**/ + UINT8 HdcControl; + +/** Offset 0x009A - Package Long duration turbo mode time + Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) + 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PowerLimit1Time; + +/** Offset 0x009B - Short Duration Turbo Mode + Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit2; + +/** Offset 0x009C - Turbo settings Lock + Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable + $EN_DIS +**/ + UINT8 TurboPowerLimitLock; + +/** Offset 0x009D - Package PL3 time window + Package PL3 time window range for this policy from 0 to 64ms +**/ + UINT8 PowerLimit3Time; + +/** Offset 0x009E - Package PL3 Duty Cycle + Package PL3 Duty Cycle; Valid Range is 0 to 100 +**/ + UINT8 PowerLimit3DutyCycle; + +/** Offset 0x009F - Package PL3 Lock + Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit3Lock; + +/** Offset 0x00A0 - Package PL4 Lock + Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable + $EN_DIS +**/ + UINT8 PowerLimit4Lock; + +/** Offset 0x00A1 - TCC Activation Offset + TCC Activation Offset. Offset from factory set TCC activation temperature at which + the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation + Temperature, in volts.For SKL Y SKU, the recommended default for this policy is + 10, For all other SKUs the recommended default are 0 +**/ + UINT8 TccActivationOffset; + +/** Offset 0x00A2 - Tcc Offset Clamp Enable/Disable + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle + below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, + For all other SKUs the recommended default are 0: Disabled. + $EN_DIS +**/ + UINT8 TccOffsetClamp; + +/** Offset 0x00A3 - Tcc Offset Lock + Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature + target; 0: Disabled; 1: Enabled. + $EN_DIS +**/ + UINT8 TccOffsetLock; + +/** Offset 0x00A4 - Package Long duration turbo mode power limit + Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + Valid Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit1; + +/** Offset 0x00A8 - Package Short duration turbo mode power limit + Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit2Power; + +/** Offset 0x00AC - Package PL3 power limit + Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 PowerLimit3; + +/** Offset 0x00B0 - Package PL4 power limit + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 1023875 in Step size of 125 +**/ + UINT32 PowerLimit4; + +/** Offset 0x00B4 - Tcc Offset Time Window for RATL + Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 1023875 in Step size of 125 +**/ + UINT32 TccOffsetTimeWindowForRatl; + +/** Offset 0x00B8 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 HwpInterruptControl; + +/** Offset 0x00B9 - Intel Turbo Boost Max Technology 3.0 + Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 EnableItbm; + +/** Offset 0x00BA - Intel Turbo Boost Max Technology 3.0 Driver + Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled + $EN_DIS +**/ + UINT8 EnableItbmDriver; + +/** Offset 0x00BB - Enable or Disable Per Core P State OS control + Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnablePerCorePState; + +/** Offset 0x00BC - Enable or Disable HwP Autonomous Per Core P State OS control + Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: + Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoPerCorePstate; + +/** Offset 0x00BD - Enable or Disable HwP Autonomous EPP Grouping + Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpAutoEppGrouping; + +/** Offset 0x00BE - Enable or Disable EPB override over PECI + Enable or Disable EPB override over PECI. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableEpbPeciOverride; + +/** Offset 0x00BF - Enable or Disable Fast MSR for IA32_HWP_REQUEST + Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;1: Enable + $EN_DIS +**/ + UINT8 EnableFastMsrHwpReq; + +/** Offset 0x00C0 - Minimum Ring ratio limit override + Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MinRingRatioLimit; + +/** Offset 0x00C1 - Maximum Ring ratio limit override + Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo + ratio limit +**/ + UINT8 MaxRingRatioLimit; + +/** Offset 0x00C2 - Custom Ratio State Entries + The number of custom ratio state entries, ranges from 0 to 40 for a valid custom + ratio table.Sets the number of custom P-states. At least 2 states must be present +**/ + UINT8 NumberOfEntries; + +/** Offset 0x00C3 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 +**/ + UINT8 Custom1PowerLimit1Time; + +/** Offset 0x00C4 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 +**/ + UINT8 Custom2PowerLimit1Time; + +/** Offset 0x00C5 - Custom Short term Power Limit time window + Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 +**/ + UINT8 Custom3PowerLimit1Time; + +/** Offset 0x00C6 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 +**/ + UINT8 Custom1TurboActivationRatio; + +/** Offset 0x00C7 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 +**/ + UINT8 Custom2TurboActivationRatio; + +/** Offset 0x00C8 - Custom Turbo Activation Ratio + Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 +**/ + UINT8 Custom3TurboActivationRatio; + +/** Offset 0x00C9 - ConfigTdp mode settings Lock + Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ConfigTdpLock; + +/** Offset 0x00CA - Load Configurable TDP SSDT + Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ConfigTdpBios; + +/** Offset 0x00CB - Max P-State Ratio + Max P-State Ratio, Valid Range 0 to 0x7F +**/ + UINT8 MaxRatio; + +/** Offset 0x00CC - P-state ratios for custom P-state table + P-state ratios for custom P-state table. NumberOfEntries has valid range between + 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] + are configurable. Valid Range of each entry is 0 to 0x7F +**/ + UINT8 StateRatio[40]; + +/** Offset 0x00F4 - Short term Power Limit value for custom cTDP level 1 + Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit1; + +/** Offset 0x00F8 - Long term Power Limit value for custom cTDP level 1 + Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom1PowerLimit2; + +/** Offset 0x00FC - Short term Power Limit value for custom cTDP level 2 + Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit1; + +/** Offset 0x0100 - Long term Power Limit value for custom cTDP level 2 + Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom2PowerLimit2; + +/** Offset 0x0104 - Short term Power Limit value for custom cTDP level 3 + Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit1; + +/** Offset 0x0108 - Long term Power Limit value for custom cTDP level 3 + Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid + Range 0 to 4095875 in Step size of 125 +**/ + UINT32 Custom3PowerLimit2; + +/** Offset 0x010C - PL1 Enable value + PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit1; + +/** Offset 0x010D - PL1 timewindow + PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 + , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 +**/ + UINT8 PsysPowerLimit1Time; + +/** Offset 0x010E - PL2 Enable Value + PL2 Enable activates the PL2 value to limit average platform power.0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PsysPowerLimit2; + +/** Offset 0x010F +**/ + UINT8 UnusedUpdSpace5; + +/** Offset 0x0110 - Platform Power Pmax + PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. + Range 0-1024 Watts. Value of 800 = 100W +**/ + UINT16 PsysPmax; + +/** Offset 0x0112 +**/ + UINT8 UnusedUpdSpace6[2]; + +/** Offset 0x0114 - Platform PL1 power + Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit1Power; + +/** Offset 0x0118 - Platform PL2 power + Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range + 0 to 4095875 in Step size of 125 +**/ + UINT32 PsysPowerLimit2Power; + +/** Offset 0x011C - Enable or Disable Intel SpeedStep Technology + Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Eist; + +/** Offset 0x011D - Enable or Disable Energy Efficient P-state + Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; + 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientPState; + +/** Offset 0x011E - Enable or Disable Energy Efficient Turbo + Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; + 1: Enable + $EN_DIS +**/ + UINT8 EnergyEfficientTurbo; + +/** Offset 0x011F - Enable or Disable T states + Enable or Disable T states; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 TStates; + +/** Offset 0x0120 - Enable or Disable Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 BiProcHot; + +/** Offset 0x0121 - Enable or Disable PROCHOT# signal being driven externally + Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableProcHotOut; + +/** Offset 0x0122 - Enable or Disable PROCHOT# Response + Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ProcHotResponse; + +/** Offset 0x0123 - Enable or Disable VR Thermal Alert + Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 DisableVrThermalAlert; + +/** Offset 0x0124 - Enable or Disable Thermal Reporting + Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 AutoThermalReporting; + +/** Offset 0x0125 - Enable or Disable Thermal Monitor + Enable or Disable Thermal Monitor; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ThermalMonitor; + +/** Offset 0x0126 - Enable or Disable CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 Cx; + +/** Offset 0x0127 - Configure C-State Configuration Lock + Configure C-State Configuration Lock; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmgCstCfgCtrlLock; + +/** Offset 0x0128 - Enable or Disable Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1e; + +/** Offset 0x0129 - Enable or Disable C1 Cstate Demotion + Enable or Disable C1 Cstate Demotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateAutoDemotion; + +/** Offset 0x012A - Enable or Disable C1 Cstate UnDemotion + Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable + $EN_DIS +**/ + UINT8 C1StateUnDemotion; + +/** Offset 0x012B - Enable or Disable Package Cstate Demotion + Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateDemotion; + +/** Offset 0x012C - Enable or Disable Package Cstate UnDemotion + Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 PkgCStateUnDemotion; + +/** Offset 0x012D - Enable or Disable CState-Pre wake + Enable or Disable CState-Pre wake. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 CStatePreWake; + +/** Offset 0x012E - Enable or Disable TimedMwait Support. + Enable or Disable TimedMwait Support. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 TimedMwait; + +/** Offset 0x012F - Enable or Disable IO to MWAIT redirection + Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 CstCfgCtrIoMwaitRedirection; + +/** Offset 0x0130 - Set the Max Pkg Cstate + Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep + C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , + 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto +**/ + UINT8 PkgCStateLimit; + +/** Offset 0x0131 - TimeUnit for C-State Latency Control1 + TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl1TimeUnit; + +/** Offset 0x0132 - TimeUnit for C-State Latency Control2 + TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl2TimeUnit; + +/** Offset 0x0133 - TimeUnit for C-State Latency Control3 + TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl3TimeUnit; + +/** Offset 0x0134 - TimeUnit for C-State Latency Control4 + Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl4TimeUnit; + +/** Offset 0x0135 - TimeUnit for C-State Latency Control5 + TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns + , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns +**/ + UINT8 CstateLatencyControl5TimeUnit; + +/** Offset 0x0136 - Interrupt Redirection Mode Select + Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: + No change. +**/ + UINT8 PpmIrmSetting; + +/** Offset 0x0137 - Lock prochot configuration + Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 ProcHotLock; + +/** Offset 0x0138 - Race To Halt + Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency + in order to enter pkg C-State faster to reduce overall power. (RTH is controlled + through MSR 1FC bit 20)Disable; 1: Enable + $EN_DIS +**/ + UINT8 RaceToHalt; + +/** Offset 0x0139 - Configuration for boot TDP selection + Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP + Up;0xFF : Deactivate +**/ + UINT8 ConfigTdpLevel; + +/** Offset 0x013A - Interrupt Response Time Limit of C-State LatencyContol1 + Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl1Irtl; + +/** Offset 0x013C - Interrupt Response Time Limit of C-State LatencyContol2 + Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl2Irtl; + +/** Offset 0x013E - Interrupt Response Time Limit of C-State LatencyContol3 + Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl3Irtl; + +/** Offset 0x0140 - Interrupt Response Time Limit of C-State LatencyContol4 + Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl4Irtl; + +/** Offset 0x0142 - Interrupt Response Time Limit of C-State LatencyContol5. 0 is Auto. + Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. + 0 is Auto. +**/ + UINT16 CstateLatencyControl5Irtl; + +/** Offset 0x0144 - P-state ratios for max 16 version of custom P-state table + P-state ratios for max 16 version of custom P-state table. This table is used for + OS versions limited to a max of 16 P-States. If the first entry of this table is + 0, or if Number of Entries is 16 or less, then this table will be ignored, and + up to the top 16 values of the StateRatio table will be used instead. Valid Range + of each entry is 0 to 0x7F +**/ + UINT8 StateRatioMax16[16]; + +/** Offset 0x0154 - CpuBistData + Pointer CPU BIST Data +**/ + UINT32 CpuBistData; + +/** Offset 0x0158 - CpuMpPpi + Pointer for CpuMpPpi +**/ + UINT32 CpuMpPpi; + +/** Offset 0x015C - CpuMpHob + Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. +**/ + UINT32 CpuMpHob; + +/** Offset 0x0160 +**/ + UINT8 CpuPostMemRsvd[16]; + +/** Offset 0x0170 - BgpdtHash[4] + BgpdtHash values +**/ + UINT64 BgpdtHash[4]; + +/** Offset 0x0190 - BiosGuardAttr + BiosGuardAttr default values +**/ + UINT32 BiosGuardAttr; + +/** Offset 0x0194 +**/ + UINT8 UnusedUpdSpace7[4]; + +/** Offset 0x0198 - BiosGuardModulePtr + BiosGuardModulePtr default values +**/ + UINT64 BiosGuardModulePtr; + +/** Offset 0x01A0 - SendEcCmd + SendEcCmd function pointer. \n + @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE + EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode +**/ + UINT64 SendEcCmd; + +/** Offset 0x01A8 - EcCmdProvisionEav + Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC +**/ + UINT8 EcCmdProvisionEav; + +/** Offset 0x01A9 - EcCmdLock + EcCmdLock default values. Locks Ephemeral Authorization Value sent previously +**/ + UINT8 EcCmdLock; + +/** Offset 0x01AA +**/ + UINT8 UnusedUpdSpace8[6]; + +/** Offset 0x01B0 - SgxEpoch0 + SgxEpoch0 default values +**/ + UINT64 SgxEpoch0; + +/** Offset 0x01B8 - SgxEpoch1 + SgxEpoch1 default values +**/ + UINT64 SgxEpoch1; + +/** Offset 0x01C0 - SgxSinitNvsData + SgxSinitNvsData default values +**/ + UINT8 SgxSinitNvsData; + +/** Offset 0x01C1 - SgxSinitDataFromTpm + SgxSinitDataFromTpm default values +**/ + UINT8 SgxSinitDataFromTpm; + +/** Offset 0x01C2 +**/ + UINT8 SecurityPostMemRsvd[16]; + +/** Offset 0x01D2 - Enable Device 4 + Enable/disable Device 4 + $EN_DIS +**/ + UINT8 Device4Enable; + +/** Offset 0x01D3 - DEPRECATED SA CRID + Deprecated, use FSPM_UPD.FspmConfig.CridEnable instead + $EN_DIS +**/ + UINT8 CridEnableDeprecated; + +/** Offset 0x01D4 - Skip PAM register lock + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + $EN_DIS +**/ + UINT8 SkipPamLock; + +/** Offset 0x01D5 - EDRAM Test Mode + Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): + PAM registers will be locked by RC + 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode +**/ + UINT8 EdramTestMode; + +/** Offset 0x01D6 - DMI ASPM + 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 + 0:Disable, 1:L0s, 2:L1, 3:L0sL1 +**/ + UINT8 DmiAspm; + +/** Offset 0x01D7 - PchDmiCwbEnable + Central Write Buffer feature configurable and disabled by default + $EN_DIS +**/ + UINT8 PchDmiCwbEnable; + +/** Offset 0x01D8 - DMI Extended Sync Control + Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended + Sync Control + $EN_DIS +**/ + UINT8 DmiExtSync; + +/** Offset 0x01D9 - DMI IOT Control + Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control + $EN_DIS +**/ + UINT8 DmiIot; + +/** Offset 0x01DA - PCIe DeEmphasis control per root port + 0: -6dB, 1(Default): -3.5dB + 0:-6dB, 1:-3.5dB +**/ + UINT8 PegDeEmphasis[4]; + +/** Offset 0x01DE - PCIe Slot Power Limit value per root port + Slot power limit value per root port +**/ + UINT8 PegSlotPowerLimitValue[4]; + +/** Offset 0x01E2 - PCIe Slot Power Limit scale per root port + Slot power limit scale per root port + 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x +**/ + UINT8 PegSlotPowerLimitScale[4]; + +/** Offset 0x01E6 - PCIe Physical Slot Number per root port + Physical Slot Number per root port +**/ + UINT16 PegPhysicalSlotNumber[4]; + +/** Offset 0x01EE - PEG Max Payload size per root port + 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B + 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B +**/ + UINT8 PegMaxPayload[4]; + +/** Offset 0x01F2 +**/ + UINT8 UnusedUpdSpace9[2]; + +/** Offset 0x01F4 - Graphics Configuration Ptr + Points to VBT +**/ + UINT32 GraphicsConfigPtr; + +/** Offset 0x01F8 - Logo Pointer + Points to PEI Display Logo Image +**/ + UINT32 LogoPtr; + +/** Offset 0x01FC - Logo Size + Size of PEI Display Logo Image +**/ + UINT32 LogoSize; + +/** Offset 0x0200 - Blt Buffer Address + Address of Blt buffer +**/ + UINT32 BltBufferAddress; + +/** Offset 0x0204 - Blt Buffer Size + Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of + EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +**/ + UINT32 BltBufferSize; + +/** Offset 0x0208 - Enable/Disable PavpEnable + Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable + $EN_DIS +**/ + UINT8 PavpEnable; + +/** Offset 0x0209 - CdClock Frequency selection + 0: (Default) Auto (Max based on reference clock frequency), 1: 307.2, 2: 312 Mhz, + 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz + 0: Auto (Max based on reference clock frequency), 1: 307.2, 2: 312 Mhz, 3: 552 Mhz, + 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz +**/ + UINT8 CdClock; + +/** Offset 0x020A - Enable/Disable PeiGraphicsPeimInit + Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit + $EN_DIS +**/ + UINT8 PeiGraphicsPeimInit; + +/** Offset 0x020B - Enable/Disable IGFX RenderStandby + Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby + $EN_DIS +**/ + UINT8 RenderStandby; + +/** Offset 0x020C - Enable/Disable IGFX PmSupport + Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport + $EN_DIS +**/ + UINT8 PmSupport; + +/** Offset 0x020D - Enable/Disable CdynmaxClamp + Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp + $EN_DIS +**/ + UINT8 CdynmaxClampEnable; + +/** Offset 0x020E - GT Frequency Limit + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz + 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, + 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: + 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, + 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, + 0x18: 1200 Mhz +**/ + UINT8 GtFreqMax; + +/** Offset 0x020F - Disable Turbo GT + 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency + $EN_DIS +**/ + UINT8 DisableTurboGt; + +/** Offset 0x0210 - Enable/Disable CdClock Init + Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full + CD clock if not initialized by Gfx PEIM + $EN_DIS +**/ + UINT8 SkipCdClockInit; + +/** Offset 0x0211 - Enable or disable HPD of DDI port-A device + 0=Disabled,1(Default)=eDP, 2=MIPI DSI + 0:Disabled, 1:eDP, 2:MIPI DSI +**/ + UINT8 DdiPortAConfig; + +/** Offset 0x0212 - Enable or disable HPD of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBHpd; + +/** Offset 0x0213 - Enable or disable HPD of DDI port C + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortCHpd; + +/** Offset 0x0214 - Enable or disable HPD of DDI port 1 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort1Hpd; + +/** Offset 0x0215 - Enable or disable HPD of DDI port 2 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort2Hpd; + +/** Offset 0x0216 - Enable or disable HPD of DDI port 3 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort3Hpd; + +/** Offset 0x0217 - Enable or disable HPD of DDI port 4 + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPort4Hpd; + +/** Offset 0x0218 - Enable or disable DDC of DDI port B + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortBDdc; + +/** Offset 0x0219 - Enable or disable DDC of DDI port C + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 DdiPortCDdc; + +/** Offset 0x021A - Enable DDC setting of DDI Port 1 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort1Ddc; + +/** Offset 0x021B - Enable DDC setting of DDI Port 2 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort2Ddc; + +/** Offset 0x021C - Enable DDC setting of DDI Port 3 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort3Ddc; + +/** Offset 0x021D - Enable DDC setting of DDI Port 4 + 0=Disable, 1=DDC(Default) + 0: Disable, 1: DDC +**/ + UINT8 DdiPort4Ddc; + +/** Offset 0x021E - Enable or disable GNA device + 0=Disable, 1(Default)=Enable + $EN_DIS +**/ + UINT8 GnaEnable; + +/** Offset 0x021F - USB override in IOM + This policy will enable/disable USB Connect override in IOM + $EN_DIS +**/ + UINT8 UsbOverride; + +/** Offset 0x0220 - VCCST request for IOM + This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 + $EN_DIS +**/ + UINT8 VccSt; + +/** Offset 0x0221 - Enable D3 Hot in TCSS + This policy will enable/disable D3 hot support in IOM + $EN_DIS +**/ + UINT8 D3HotEnable; + +/** Offset 0x0222 - Enable D3 Cold in TCSS + This policy will enable/disable D3 cold support in IOM + $EN_DIS +**/ + UINT8 D3ColdEnable; + +/** Offset 0x0223 - Enable/Disable PMC-PD Solution + This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution + $EN_DIS +**/ + UINT8 PmcPdEnable; + +/** Offset 0x0224 - Enable/Disable PTM + This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports + $EN_DIS +**/ + UINT8 PtmEnabled[4]; + +/** Offset 0x0228 - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 SaPcieItbtRpLtrEnable[4]; + +/** Offset 0x022C - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; + +/** Offset 0x0230 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0234 - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; + +/** Offset 0x023C - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; + +/** Offset 0x0240 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; + +/** Offset 0x0244 - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; + +/** Offset 0x024C - Force LTR Override + Force LTR Override. +**/ + UINT8 SaPcieItbtRpForceLtrOverride[4]; + +/** Offset 0x0250 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 SaPcieItbtRpLtrConfigLock[4]; + +/** Offset 0x0254 - Enable VMD controller + Enable/disable to VMD controller. + $EN_DIS +**/ + UINT8 VmdEnable; + +/** Offset 0x0255 - Enable VMD portA Support + Enable/disable to VMD portA Support. + $EN_DIS +**/ + UINT8 VmdPortA; + +/** Offset 0x0256 - Enable VMD portB Support + Enable/disable to VMD portB Support. + $EN_DIS +**/ + UINT8 VmdPortB; + +/** Offset 0x0257 - Enable VMD portC Support + Enable/disable to VMD portC Support. + $EN_DIS +**/ + UINT8 VmdPortC; + +/** Offset 0x0258 - Enable VMD portD Support + Enable/disable to VMD portD Support. + $EN_DIS +**/ + UINT8 VmdPortD; + +/** Offset 0x0259 - VMD Config Bar size + Set The VMD Config Bar Size. +**/ + UINT8 VmdCfgBarSz; + +/** Offset 0x025A - VMD Config Bar Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdCfgBarAttr; + +/** Offset 0x025B - VMD Mem Bar1 size + Set The VMD Mem Bar1 Size. +**/ + UINT8 VmdMemBarSz1; + +/** Offset 0x025C - VMD Mem Bar1 Attributes + 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar1Attr; + +/** Offset 0x025D - VMD Mem Bar2 size + Set The VMD Mem Bar2 Size. +**/ + UINT8 VmdMemBarSz2; + +/** Offset 0x025E - VMD Mem Bar2 Attributes + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH + 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH +**/ + UINT8 VmdMemBar2Attr; + +/** Offset 0x025F +**/ + UINT8 UnusedUpdSpace10[1]; + +/** Offset 0x0260 - TypeC port GPIO setting + GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined + in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Icl + = IceLake) +**/ + UINT32 IomTypeCPortPadCfg[8]; + +/** Offset 0x0280 - TCSS Aux Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssAuxOri; + +/** Offset 0x0282 - TCSS HSL Orientation Override Enable + Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides +**/ + UINT16 TcssHslOri; + +/** Offset 0x0284 - PCH USB OverCurrent mapping enable + 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin + mapping allow for NOA usage of OC pins + $EN_DIS +**/ + UINT8 PchUsbOverCurrentEnable; + +/** Offset 0x0285 - CPU USB3 Port Over Current Pin + Describe the specific over current pin number of USBC Port N. +**/ + UINT8 CpuUsb3OverCurrentPin[8]; + +/** Offset 0x028D - TCSS USB Port Enable + Bits 0, 1, ... max Type C port control enables +**/ + UINT8 UsbTcPortEn; + +/** Offset 0x028E +**/ + UINT8 UnusedUpdSpace11[2]; + +/** Offset 0x0290 - ITBT DMA UUID + TCSS DMA1, DMA2 UUID Number +**/ + UINT32 IclAxITbtDmaUuid[2]; + +/** Offset 0x0298 - ITBT Root Port Enable + ITBT Root Port Enable, 0:Disable, 1:Enable + 0:Disable, 1:Enable +**/ + UINT8 ITbtPcieRootPortEn[4]; + +/** Offset 0x029C - ITBTForcePowerOn Timeout value + ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. + 100 = 100 ms. +**/ + UINT16 ITbtForcePowerOnTimeoutInMs; + +/** Offset 0x029E - ITbtConnectTopology Timeout value + ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range + is 0-10000. 100 = 100 ms. +**/ + UINT16 ITbtConnectTopologyTimeoutInMs; + +/** Offset 0x02A0 - TcssXhciEnableComplianceMode + Set Compliance Mode. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssXhciEnableComplianceMode; + +/** Offset 0x02A1 - Enable/Disable PEG GEN3 Static EQ Phase1 programming + Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 SaPcieGen3ProgramStaticEq; + +/** Offset 0x02A2 - Enable/Disable GEN4 Static EQ Phase1 programming + Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets + Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming + $EN_DIS +**/ + UINT8 SaPcieGen4ProgramStaticEq; + +/** Offset 0x02A3 - TcssLoopbackModeBitMap + Set Loopback Mode Bit Map. 0:Disabled 1:Enabled + $EN_DIS +**/ + UINT8 TcssLoopbackModeBitMap; + +/** Offset 0x02A4 - ITBT DMA UUID + TCSS DMA1, DMA2 LTR value +**/ + UINT16 ITbtDmaLtr[2]; + +/** Offset 0x02A8 +**/ + UINT8 SaPostMemRsvd[3]; + +/** Offset 0x02AB - HECI3 state + The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. + 0: disable, 1: enable + $EN_DIS +**/ + UINT8 Heci3Enabled; + +/** Offset 0x02AC - ME Unconfig on RTC clear + 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. + 2: Cmos is clear, status unkonwn. 3: Reserved + 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos + is clear, 3: Reserved +**/ + UINT8 MeUnconfigOnRtcClear; + +/** Offset 0x02AD - End of Post message + Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): + EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE + 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved +**/ + UINT8 EndOfPostMessage; + +/** Offset 0x02AE - D0I3 Setting for HECI Disable + Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all + HECI devices + $EN_DIS +**/ + UINT8 DisableD0I3SettingForHeci; + +/** Offset 0x02AF - Mctp Broadcast Cycle + Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 MctpBroadcastCycle; + +/** Offset 0x02B0 +**/ + UINT8 MePostMemRsvd[10]; + +/** Offset 0x02BA - AMT Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. + $EN_DIS +**/ + UINT8 AmtEnabled; + +/** Offset 0x02BB - WatchDog Timer Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. + $EN_DIS +**/ + UINT8 WatchDog; + +/** Offset 0x02BC - ASF Switch + Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. + $EN_DIS +**/ + UINT8 AsfEnabled; + +/** Offset 0x02BD - PET Progress + Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive + PET Events. + $EN_DIS +**/ + UINT8 FwProgress; + +/** Offset 0x02BE - OS Timer + 16 bits Value, Set OS watchdog timer. + $EN_DIS +**/ + UINT16 WatchDogTimerOs; + +/** Offset 0x02C0 - BIOS Timer + 16 bits Value, Set BIOS watchdog timer. + $EN_DIS +**/ + UINT16 WatchDogTimerBios; + +/** Offset 0x02C2 - Manageability Mode set by Mebx + Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. + $EN_DIS +**/ + UINT8 ManageabilityMode; + +/** Offset 0x02C3 - SOL Switch + Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx + $EN_DIS +**/ + UINT8 AmtSolEnabled; + +/** Offset 0x02C4 - Remote Assistance Trigger Availablilty + Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx + $EN_DIS +**/ + UINT8 RemoteAssistance; + +/** Offset 0x02C5 - KVM Switch + Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx + $EN_DIS +**/ + UINT8 AmtKvmEnabled; + +/** Offset 0x02C6 - MEBX execution + Enable/Disable. 0: Disable, 1: enable, Force MEBX execution + $EN_DIS +**/ + UINT8 ForcMebxSyncUp; + +/** Offset 0x02C7 +**/ + UINT8 AmtPostMemRsvd[10]; + +/** Offset 0x02D1 - SPI0 Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, + 1:PchSerialIoCsActiveHigh +**/ + UINT8 SerialIoSpi0CsPolarity[2]; + +/** Offset 0x02D3 - SPI1 Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, + 1:PchSerialIoCsActiveHigh +**/ + UINT8 SerialIoSpi1CsPolarity[2]; + +/** Offset 0x02D5 - SPI2 Chip Select Polarity + Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, + 1:PchSerialIoCsActiveHigh +**/ + UINT8 SerialIoSpi2CsPolarity[2]; + +/** Offset 0x02D7 - SPI0 Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpi0CsEnable[2]; + +/** Offset 0x02D9 - SPI1 Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpi1CsEnable[2]; + +/** Offset 0x02DB - SPI2 Chip Select Enable + 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled +**/ + UINT8 SerialIoSpi2CsEnable[2]; + +/** Offset 0x02DD - SPIn Device Mode + Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available + modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden +**/ + UINT8 SerialIoSpiMode[3]; + +/** Offset 0x02E0 - SPIn Default Chip Select Output + Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available + options: 0:CS0, 1:CS1 +**/ + UINT8 SerialIoSpiDefaultCsOutput[3]; + +/** Offset 0x02E3 - SPIn Default Chip Select Mode HW/SW + Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, + SPI1, ... Available options: 0:HW, 1:SW +**/ + UINT8 SerialIoSpiCsMode[3]; + +/** Offset 0x02E6 - SPIn Default Chip Select State Low/High + Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... + Available options: 0:Low, 1:High +**/ + UINT8 SerialIoSpiCsState[3]; + +/** Offset 0x02E9 - PCH SerialIo I2C Pads Termination + 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, + 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 + pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 + for I2C1, and so on. +**/ + UINT8 PchSerialIoI2cPadsTermination[6]; + +/** Offset 0x02EF - I2Cn Device Mode + Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available + modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden +**/ + UINT8 SerialIoI2cMode[6]; + +/** Offset 0x02F5 - UARTn Device Mode + Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available + modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, + 4:SerialIoUartSkipInit +**/ + UINT8 SerialIoUartMode[3]; + +/** Offset 0x02F8 - Default BaudRate for each Serial IO UART + Set default BaudRate Supported from 0 - default to 6000000 +**/ + UINT32 SerialIoUartBaudRate[3]; + +/** Offset 0x0304 - Default ParityType for each Serial IO UART + Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity +**/ + UINT8 SerialIoUartParity[3]; + +/** Offset 0x0307 - Default DataBits for each Serial IO UART + Set default word length. 0: Default, 5,6,7,8 +**/ + UINT8 SerialIoUartDataBits[3]; + +/** Offset 0x030A - Default StopBits for each Serial IO UART + Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: + TwoStopBits +**/ + UINT8 SerialIoUartStopBits[3]; + +/** Offset 0x030D - Power Gating mode for each Serial IO UART that works in COM mode + Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto +**/ + UINT8 SerialIoUartPowerGating[3]; + +/** Offset 0x0310 - Enable Dma for each Serial IO UART that supports it + Set DMA/PIO mode. 0: Disabled, 1: Enabled +**/ + UINT8 SerialIoUartDmaEnable[3]; + +/** Offset 0x0313 - Enables UART hardware flow control, CTS and RTS lines + Enables UART hardware flow control, CTS and RTS lines. +**/ + UINT8 SerialIoUartAutoFlow[3]; + +/** Offset 0x0316 +**/ + UINT8 UnusedUpdSpace12[2]; + +/** Offset 0x0318 - SerialIoUartRxPinMux + Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for + possible values. +**/ + UINT32 SerialIoUartRxPinMux[3]; + +/** Offset 0x0324 - SerialIoUartTxPinMux + Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for + possible values. +**/ + UINT32 SerialIoUartTxPinMux[3]; + +/** Offset 0x0330 - SerialIoUartRtsPinMux + Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* + for possible values. +**/ + UINT32 SerialIoUartRtsPinMux[3]; + +/** Offset 0x033C - SerialIoUartCtsPinMux + Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* + for possible values. +**/ + UINT32 SerialIoUartCtsPinMux[3]; + +/** Offset 0x0348 - UART Number For Debug Purpose + UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected + as CNVi BT Core interface, it cannot be used for debug purpose. + 0:UART0, 1:UART1, 2:UART2 +**/ + UINT8 SerialIoDebugUartNumber; + +/** Offset 0x0349 - Enable LAN + Enable/disable LAN controller. + $EN_DIS +**/ + UINT8 PchLanEnable; + +/** Offset 0x034A - Enable PCH Lan LTR capabilty of PCH internal LAN + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchLanLtrEnable; + +/** Offset 0x034B - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x034C - Enable Pme + Enable Azalia wake-on-ring. + $EN_DIS +**/ + UINT8 PchHdaPme; + +/** Offset 0x034D - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x034E - HD Audio Link Frequency + HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. + 0: 6MHz, 1: 12MHz, 2: 24MHz +**/ + UINT8 PchHdaLinkFrequency; + +/** Offset 0x034F - iDisp-Link Frequency + iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. + 4: 96MHz, 3: 48MHz +**/ + UINT8 PchHdaIDispLinkFrequency; + +/** Offset 0x0350 - iDisp-Link T-mode + iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T + 0: 2T, 2: 4T, 3: 8T, 4: 16T +**/ + UINT8 PchHdaIDispLinkTmode; + +/** Offset 0x0351 - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x0352 - iDisplay Audio Codec disconnection + 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. + $EN_DIS +**/ + UINT8 PchHdaIDispCodecDisconnect; + +/** Offset 0x0353 - PCH HDA Codec Sx Wake Capability + Capability to detect wake initiated by a codec in Sx +**/ + UINT8 PchHdaCodecSxWakeCapability; + +/** Offset 0x0354 - HD Audio Reset Wait Timer + The delay timer after Azalia reset, the value is number of microseconds. Default is 600. +**/ + UINT16 PchHdaResetWaitTimer; + +/** Offset 0x0356 - PCH HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + UINT8 PchHdaVerbTableEntryNum; + +/** Offset 0x0357 +**/ + UINT8 UnusedUpdSpace13; + +/** Offset 0x0358 - PCH HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + UINT32 PchHdaVerbTablePtr; + +/** Offset 0x035C - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHda; + +/** Offset 0x035D - Enable HD Audio DMIC0 Link + Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic0; + +/** Offset 0x035E - Enable HD Audio DMIC1 Link + Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic1; + +/** Offset 0x035F - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp0; + +/** Offset 0x0360 - Enable HD Audio SSP1 Link + Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp1; + +/** Offset 0x0361 - Enable HD Audio SSP2 Link + Enable/disable HD Audio SSP2/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp2; + +/** Offset 0x0362 - Enable HD Audio SSP3 Link + Enable/disable HD Audio SSP3/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp3; + +/** Offset 0x0363 - Enable HD Audio SSP4 Link + Enable/disable HD Audio SSP4/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp4; + +/** Offset 0x0364 - Enable HD Audio SSP5 Link + Enable/disable HD Audio SSP5/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp5; + +/** Offset 0x0365 - Enable HD Audio SoundWire#1 Link + Enable/disable HD Audio SNDW1 link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw1; + +/** Offset 0x0366 - Enable HD Audio SoundWire#2 Link + Enable/disable HD Audio SNDW2 link. Muxed with SSP1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw2; + +/** Offset 0x0367 - Enable HD Audio SoundWire#3 Link + Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw3; + +/** Offset 0x0368 - Enable HD Audio SoundWire#4 Link + Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw4; + +/** Offset 0x0369 - CNVi Configuration + This option allows for automatic detection of Connectivity Solution. [Auto Detection] + assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. + 0:Disable, 1:Auto +**/ + UINT8 CnviMode; + +/** Offset 0x036A - CNVi BT Core + Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtCore; + +/** Offset 0x036B - CNVi BT Audio Offload + Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE + $EN_DIS +**/ + UINT8 CnviBtAudioOffload; + +/** Offset 0x036C - CNVi RF_RESET pin muxing + Select CNVi RF_RESET# pin depending on board routing. ICP-LP: GPP_A8 = 0x2640E408(default) + or GPP_F4 = 0x1645E404. ICP-H: 0. ICP-N: GPP_H12 = 0x2746E40C(default) or GPP_H1 + = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. +**/ + UINT32 CnviRfResetPinMux; + +/** Offset 0x0370 - CNVi CLKREQ pin muxing + Select CNVi CLKREQ pin depending on board routing. ICP-LP: GPP_A9 = 0x2640E609(default) + or GPP_F5 = 0x2645E605. ICP-H: 0. ICP-N: GPP_H13 = 0x2746E60D(default) or GPP_H2 + = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h. +**/ + UINT32 CnviClkreqPinMux; + +/** Offset 0x0374 - Espi Lgmr Memory Range decode + This option enables or disables espi lgmr + $EN_DIS +**/ + UINT8 PchEspiLgmrEnable; + +/** Offset 0x0375 - PCH eSPI Master and Slave BME enabled + PCH eSPI Master and Slave BME enabled + $EN_DIS +**/ + UINT8 PchEspiBmeMasterSlaveEnabled; + +/** Offset 0x0376 - Enable Host C10 reporting through eSPI + Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire. + $EN_DIS +**/ + UINT8 PchEspiHostC10ReportEnable; + +/** Offset 0x0377 - Enable SdCard Controller + Enable/disable SD Card Controller. + $EN_DIS +**/ + UINT8 ScsSdCardEnabled; + +/** Offset 0x0378 - SdCard power enable polarity + Choose SD_PWREN# polarity + 0: Active low, 1: Active high +**/ + UINT8 SdCardPowerEnableActiveHigh; + +/** Offset 0x0379 - Use tuned DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 SdCardUseCustomDlls; + +/** Offset 0x037A +**/ + UINT8 UnusedUpdSpace14[2]; + +/** Offset 0x037C - SdCard Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 SdCardTxCmdDelayRegValue; + +/** Offset 0x0380 - SdCard Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 SdCardTxDataDelay1RegValue; + +/** Offset 0x0384 - SdCard Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 SdCardTxDataDelay2RegValue; + +/** Offset 0x0388 - SdCard Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay1RegValue; + +/** Offset 0x038C - SdCard Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay2RegValue; + +/** Offset 0x0390 - Enable eMMC Controller + Enable/disable eMMC Controller. + $EN_DIS +**/ + UINT8 ScsEmmcEnabled; + +/** Offset 0x0391 - Enable eMMC HS400 Mode + Enable eMMC HS400 Mode. + $EN_DIS +**/ + UINT8 ScsEmmcHs400Enabled; + +/** Offset 0x0392 - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 EmmcUseCustomDlls; + +/** Offset 0x0393 +**/ + UINT8 UnusedUpdSpace15; + +/** Offset 0x0394 - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x0398 - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x039C - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x03A0 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x03A4 - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x03A8 - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x03AC - UFS enable/disable + Please see Rx Strobe Delay control register definition for help + $EN_DIS +**/ + UINT8 UfsEnable[2]; + +/** Offset 0x03AE - Enable PCH ISH SPI GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshSpiGpioAssign; + +/** Offset 0x03AF - Enable PCH ISH UART0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshUart0GpioAssign; + +/** Offset 0x03B0 - Enable PCH ISH UART1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshUart1GpioAssign; + +/** Offset 0x03B1 - Enable PCH ISH I2C0 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c0GpioAssign; + +/** Offset 0x03B2 - Enable PCH ISH I2C1 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c1GpioAssign; + +/** Offset 0x03B3 - Enable PCH ISH I2C2 GPIO pins assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshI2c2GpioAssign; + +/** Offset 0x03B4 - Enable PCH ISH GP_0 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp0GpioAssign; + +/** Offset 0x03B5 - Enable PCH ISH GP_1 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp1GpioAssign; + +/** Offset 0x03B6 - Enable PCH ISH GP_2 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp2GpioAssign; + +/** Offset 0x03B7 - Enable PCH ISH GP_3 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp3GpioAssign; + +/** Offset 0x03B8 - Enable PCH ISH GP_4 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp4GpioAssign; + +/** Offset 0x03B9 - Enable PCH ISH GP_5 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp5GpioAssign; + +/** Offset 0x03BA - Enable PCH ISH GP_6 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp6GpioAssign; + +/** Offset 0x03BB - Enable PCH ISH GP_7 GPIO pin assigned + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIshGp7GpioAssign; + +/** Offset 0x03BC - PCH ISH PDT Unlock Msg + 0: False; 1: True. + $EN_DIS +**/ + UINT8 PchIshPdtUnlock; + +/** Offset 0x03BD - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + UINT8 SataEnable; + +/** Offset 0x03BE - PCH Sata Test Mode + Allow entrance to the PCH SATA test modes. + $EN_DIS +**/ + UINT8 SataTestMode; + +/** Offset 0x03BF - Enable SATA SALP Support + Enable/disable SATA Aggressive Link Power Management. + $EN_DIS +**/ + UINT8 SataSalpSupport; + +/** Offset 0x03C0 - PCH Sata Pwr Opt Enable + SATA Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 SataPwrOptEnable; + +/** Offset 0x03C1 - PCH Sata eSATA Speed Limit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. + $EN_DIS +**/ + UINT8 EsataSpeedLimit; + +/** Offset 0x03C2 - SATA LED + SATA LED indicating SATA controller activity. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 SataLedEnable; + +/** Offset 0x03C3 - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + UINT8 SataMode; + +/** Offset 0x03C4 - PCH Sata Speed Limit + Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. +**/ + UINT8 SataSpeedLimit; + +/** Offset 0x03C5 - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, + and so on. +**/ + UINT8 SataPortsEnable[8]; + +/** Offset 0x03CD - Enable SATA Port HotPlug + Enable SATA Port HotPlug. +**/ + UINT8 SataPortsHotPlug[8]; + +/** Offset 0x03D5 - Enable SATA Port Interlock Sw + Enable SATA Port Interlock Sw. +**/ + UINT8 SataPortsInterlockSw[8]; + +/** Offset 0x03DD - Enable SATA Port External + Enable SATA Port External. +**/ + UINT8 SataPortsExternal[8]; + +/** Offset 0x03E5 - Enable SATA Port SpinUp + Enable the COMRESET initialization Sequence to the device. +**/ + UINT8 SataPortsSpinUp[8]; + +/** Offset 0x03ED - Enable SATA Port Solid State Drive + 0: HDD; 1: SSD. +**/ + UINT8 SataPortsSolidStateDrive[8]; + +/** Offset 0x03F5 - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each + port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlp[8]; + +/** Offset 0x03FD - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; + +/** Offset 0x0405 - Enable SATA Port DmVal + DITO multiplier. Default is 15. +**/ + UINT8 SataPortsDmVal[8]; + +/** Offset 0x040D +**/ + UINT8 UnusedUpdSpace16[1]; + +/** Offset 0x040E - Enable SATA Port DmVal + DEVSLP Idle Timeout (DITO), Default is 625. +**/ + UINT16 SataPortsDitoVal[8]; + +/** Offset 0x041E - Enable SATA Port ZpOdd + Support zero power ODD. +**/ + UINT8 SataPortsZpOdd[8]; + +/** Offset 0x0426 - PCH Sata Rst Raid Alternate Id + Enable RAID Alternate ID. + $EN_DIS +**/ + UINT8 SataRstRaidDeviceId; + +/** Offset 0x0427 - PCH Sata Rst Raid0 + RAID0. + $EN_DIS +**/ + UINT8 SataRstRaid0; + +/** Offset 0x0428 - PCH Sata Rst Raid1 + RAID1. + $EN_DIS +**/ + UINT8 SataRstRaid1; + +/** Offset 0x0429 - PCH Sata Rst Raid10 + RAID10. + $EN_DIS +**/ + UINT8 SataRstRaid10; + +/** Offset 0x042A - PCH Sata Rst Raid5 + RAID5. + $EN_DIS +**/ + UINT8 SataRstRaid5; + +/** Offset 0x042B - PCH Sata Rst Irrt + Intel Rapid Recovery Technology. + $EN_DIS +**/ + UINT8 SataRstIrrt; + +/** Offset 0x042C - PCH Sata Rst Orom Ui Banner + OROM UI and BANNER. + $EN_DIS +**/ + UINT8 SataRstOromUiBanner; + +/** Offset 0x042D - PCH Sata Rst Orom Ui Delay + 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). +**/ + UINT8 SataRstOromUiDelay; + +/** Offset 0x042E - PCH Sata Rst Hdd Unlock + Indicates that the HDD password unlock in the OS is enabled. + $EN_DIS +**/ + UINT8 SataRstHddUnlock; + +/** Offset 0x042F - PCH Sata Rst Led Locate + Indicates that the LED/SGPIO hardware is attached and ping to locate feature is + enabled on the OS. + $EN_DIS +**/ + UINT8 SataRstLedLocate; + +/** Offset 0x0430 - PCH Sata Rst Irrt Only + Allow only IRRT drives to span internal and external ports. + $EN_DIS +**/ + UINT8 SataRstIrrtOnly; + +/** Offset 0x0431 - PCH Sata Rst Smart Storage + RST Smart Storage caching Bit. + $EN_DIS +**/ + UINT8 SataRstSmartStorage; + +/** Offset 0x0432 - SATA RST Interrupt Mode + Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. + 0:Msix, 1:Msi, 2:Legacy +**/ + UINT8 SataRstInterrupt; + +/** Offset 0x0433 - PCH Sata Rst Optane Memory + Optane Memory + $EN_DIS +**/ + UINT8 SataRstOptaneMemory; + +/** Offset 0x0434 - PCH SATA use RST Legacy OROM + Use PCH SATA RST Legacy OROM when CSM is Enabled + $EN_DIS +**/ + UINT8 SataRstLegacyOrom; + +/** Offset 0x0435 - PCH Sata Rst CPU Attached Storage + CPU Attached Storage + $EN_DIS +**/ + UINT8 SataRstCpuAttachedStorage; + +/** Offset 0x0436 - PCH Sata Rst Pcie Storage Remap enable + Enable Intel RST for PCIe Storage remapping. +**/ + UINT8 SataRstPcieEnable[3]; + +/** Offset 0x0439 - PCH Sata Rst Pcie Storage Port + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). +**/ + UINT8 SataRstPcieStoragePort[3]; + +/** Offset 0x043C - PCH Sata Rst Pcie Device Reset Delay + PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms +**/ + UINT8 SataRstPcieDeviceResetDelay[3]; + +/** Offset 0x043F - Port 0 T1 Multipler + Port 0 T1 Multipler. +**/ + UINT8 SataP0T1M; + +/** Offset 0x0440 - Port 0 T2 Multipler + Port 0 T2 Multipler. +**/ + UINT8 SataP0T2M; + +/** Offset 0x0441 - Port 0 T3 Multipler + Port 0 T3 Multipler. +**/ + UINT8 SataP0T3M; + +/** Offset 0x0442 - Port 0 Tdispatch + Port 0 Tdispatch. +**/ + UINT8 SataP0TDisp; + +/** Offset 0x0443 - Port 1 T1 Multipler + Port 1 T1 Multipler. +**/ + UINT8 SataP1T1M; + +/** Offset 0x0444 - Port 1 T2 Multipler + Port 1 T2 Multipler. +**/ + UINT8 SataP1T2M; + +/** Offset 0x0445 - Port 1 T3 Multipler + Port 1 T3 Multipler. +**/ + UINT8 SataP1T3M; + +/** Offset 0x0446 - Port 1 Tdispatch + Port 1 Tdispatch. +**/ + UINT8 SataP1TDisp; + +/** Offset 0x0447 - Port 0 Tinactive + Port 0 Tinactive. +**/ + UINT8 SataP0Tinact; + +/** Offset 0x0448 - Port 0 Alternate Fast Init Tdispatch + Port 0 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP0TDispFinit; + +/** Offset 0x0449 - Port 1 Tinactive + Port 1 Tinactive. +**/ + UINT8 SataP1Tinact; + +/** Offset 0x044A - Port 1 Alternate Fast Init Tdispatch + Port 1 Alternate Fast Init Tdispatch. + $EN_DIS +**/ + UINT8 SataP1TDispFinit; + +/** Offset 0x044B - Sata Thermal Throttling Suggested Setting + Sata Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 SataThermalSuggestedSetting; + +/** Offset 0x044C - Enable xHCI Compliance Mode + Compliance Mode can be enabled for testing through this option but this is disabled + by default. + $EN_DIS +**/ + UINT8 PchEnableComplianceMode; + +/** Offset 0x044D - USB PDO Programming + Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming + during later phase. 1: enable, 0: disable + $EN_DIS +**/ + UINT8 UsbPdoProgramming; + +/** Offset 0x044E - USB Overcurrent Override for DbC + This option overrides USB Over Current enablement state that USB OC will be disabled + after enabling this option. Enable when DbC is used to avoid signaling conflicts. + $EN_DIS +**/ + UINT8 PchEnableDbcObs; + +/** Offset 0x044F - PCH USB OverCurrent mapping lock enable + If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning + that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. + $EN_DIS +**/ + UINT8 PchXhciOcLock; + +/** Offset 0x0450 - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb20Enable[16]; + +/** Offset 0x0460 - USB2 Port Over Current Pin + Describe the specific over current pin number of USB 2.0 Port N. +**/ + UINT8 Usb2OverCurrentPin[16]; + +/** Offset 0x0470 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for + port1, and so on. +**/ + UINT8 PortUsb30Enable[10]; + +/** Offset 0x047A - USB3 Port Over Current Pin + Describe the specific over current pin number of USB 3.0 Port N. +**/ + UINT8 Usb3OverCurrentPin[10]; + +/** Offset 0x0484 - Enable xDCI controller + Enable/disable to xDCI controller. + $EN_DIS +**/ + UINT8 XdciEnable; + +/** Offset 0x0485 - USB Per Port HS Preemphasis Bias + USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. +**/ + UINT8 Usb2PhyPetxiset[16]; + +/** Offset 0x0495 - USB Per Port HS Transmitter Bias + USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, + 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. +**/ + UINT8 Usb2PhyTxiset[16]; + +/** Offset 0x04A5 - USB Per Port HS Transmitter Emphasis + USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, + 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. +**/ + UINT8 Usb2PhyPredeemp[16]; + +/** Offset 0x04B5 - USB Per Port Half Bit Pre-emphasis + USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. + One byte for each port. +**/ + UINT8 Usb2PhyPehalfbit[16]; + +/** Offset 0x04C5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment + Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmphEnable[10]; + +/** Offset 0x04CF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], + Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. +**/ + UINT8 Usb3HsioTxDeEmph[10]; + +/** Offset 0x04D9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment + Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value + in arrary can be between 0-1. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmpEnable[10]; + +/** Offset 0x04E3 - USB 3.0 TX Output Downscale Amplitude Adjustment + USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default + = 00h. One byte for each port. +**/ + UINT8 Usb3HsioTxDownscaleAmp[10]; + +/** Offset 0x04ED +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; + +/** Offset 0x04F7 +**/ + UINT8 PchUsb3HsioFilterSelNEnable[10]; + +/** Offset 0x0501 +**/ + UINT8 PchUsb3HsioFilterSelPEnable[10]; + +/** Offset 0x050B +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; + +/** Offset 0x0515 +**/ + UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; + +/** Offset 0x051F +**/ + UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; + +/** Offset 0x0529 +**/ + UINT8 PchUsb3HsioFilterSelN[10]; + +/** Offset 0x0533 +**/ + UINT8 PchUsb3HsioFilterSelP[10]; + +/** Offset 0x053D - Enable PCIE RP HotPlug + Indicate whether the root port is hot plug available. +**/ + UINT8 PcieRpHotPlug[24]; + +/** Offset 0x0555 - Enable PCIE RP Pm Sci + Indicate whether the root port power manager SCI is enabled. +**/ + UINT8 PcieRpPmSci[24]; + +/** Offset 0x056D - Enable PCIE RP Transmitter Half Swing + Indicate whether the Transmitter Half Swing is enabled. +**/ + UINT8 PcieRpTransmitterHalfSwing[24]; + +/** Offset 0x0585 - Enable PCIE RP Clk Req Detect + Probe CLKREQ# signal before enabling CLKREQ# based power management. +**/ + UINT8 PcieRpClkReqDetect[24]; + +/** Offset 0x059D - PCIE RP Advanced Error Report + Indicate whether the Advanced Error Reporting is enabled. +**/ + UINT8 PcieRpAdvancedErrorReporting[24]; + +/** Offset 0x05B5 - PCIE RP Unsupported Request Report + Indicate whether the Unsupported Request Report is enabled. +**/ + UINT8 PcieRpUnsupportedRequestReport[24]; + +/** Offset 0x05CD - PCIE RP Fatal Error Report + Indicate whether the Fatal Error Report is enabled. +**/ + UINT8 PcieRpFatalErrorReport[24]; + +/** Offset 0x05E5 - PCIE RP No Fatal Error Report + Indicate whether the No Fatal Error Report is enabled. +**/ + UINT8 PcieRpNoFatalErrorReport[24]; + +/** Offset 0x05FD - PCIE RP Correctable Error Report + Indicate whether the Correctable Error Report is enabled. +**/ + UINT8 PcieRpCorrectableErrorReport[24]; + +/** Offset 0x0615 - PCIE RP System Error On Fatal Error + Indicate whether the System Error on Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnFatalError[24]; + +/** Offset 0x062D - PCIE RP System Error On Non Fatal Error + Indicate whether the System Error on Non Fatal Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnNonFatalError[24]; + +/** Offset 0x0645 - PCIE RP System Error On Correctable Error + Indicate whether the System Error on Correctable Error is enabled. +**/ + UINT8 PcieRpSystemErrorOnCorrectableError[24]; + +/** Offset 0x065D - PCIE RP Max Payload + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. +**/ + UINT8 PcieRpMaxPayload[24]; + +/** Offset 0x0675 +**/ + UINT8 UnusedUpdSpace17[3]; + +/** Offset 0x0678 - DPC for PCIE RP Mask + Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpDpcMask; + +/** Offset 0x067C - DPC Extensions PCIE RP Mask + Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit + for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpDpcExtensionsMask; + +/** Offset 0x0680 - PTM for PCIE RP Mask + Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. + One bit for each port, bit0 for port1, bit1 for port2, and so on. +**/ + UINT32 PcieRpPtmMask; + +/** Offset 0x0684 - PCIE RP Pcie Speed + Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: + PCH_PCIE_SPEED). +**/ + UINT8 PcieRpPcieSpeed[24]; + +/** Offset 0x069C - PCIE RP Gen3 Equalization Phase Method + PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; + 1: hardware equalization; 4: Fixed Coeficients. +**/ + UINT8 PcieRpGen3EqPh3Method[24]; + +/** Offset 0x06B4 - PCIE RP Physical Slot Number + Indicates the slot number for the root port. Default is the value as root port index. +**/ + UINT8 PcieRpPhysicalSlotNumber[24]; + +/** Offset 0x06CC - PCH PCIe root port connection type + 0: built-in device, 1:slot +**/ + UINT8 PcieRpSlotImplemented[24]; + +/** Offset 0x06E4 - PCIE RP Completion Timeout + The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. +**/ + UINT8 PcieRpCompletionTimeout[24]; + +/** Offset 0x06FC - PCIE RP Aspm + The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + PchPcieAspmAutoConfig. +**/ + UINT8 PcieRpAspm[24]; + +/** Offset 0x0714 - PCIE RP L1 Substates + The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). + Default is PchPcieL1SubstatesL1_1_2. +**/ + UINT8 PcieRpL1Substates[24]; + +/** Offset 0x072C - PCIE RP Ltr Enable + Latency Tolerance Reporting Mechanism. +**/ + UINT8 PcieRpLtrEnable[24]; + +/** Offset 0x0744 - PCIE RP Ltr Config Lock + 0: Disable; 1: Enable. +**/ + UINT8 PcieRpLtrConfigLock[24]; + +/** Offset 0x075C - PCIE RP Access Control Services Extended Capability + Enable/Disable PCIE RP Access Control Services Extended Capability +**/ + UINT8 PcieRpAcsEnabled[24]; + +/** Offset 0x0774 - PCIE RP Clock Power Management + Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal + can still be controlled by L1 PM substates mechanism +**/ + UINT8 PcieRpEnableCpm[24]; + +/** Offset 0x078C - PCIE RP Detect Timeout Ms + The number of milliseconds within 0~65535 in reference code will wait for link to + exit Detect state for enabled ports before assuming there is no device and potentially + disabling the port. +**/ + UINT16 PcieRpDetectTimeoutMs[24]; + +/** Offset 0x07BC - PCIE RP Ltr Max Snoop Latency + Latency Tolerance Reporting, Max Snoop Latency. +**/ + UINT16 PcieRpLtrMaxSnoopLatency[24]; + +/** Offset 0x07EC - PCIE RP Ltr Max No Snoop Latency + Latency Tolerance Reporting, Max Non-Snoop Latency. +**/ + UINT16 PcieRpLtrMaxNoSnoopLatency[24]; + +/** Offset 0x081C - PCIE RP Snoop Latency Override Mode + Latency Tolerance Reporting, Snoop Latency Override Mode. +**/ + UINT8 PcieRpSnoopLatencyOverrideMode[24]; + +/** Offset 0x0834 - PCIE RP Snoop Latency Override Multiplier + Latency Tolerance Reporting, Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x084C - PCIE RP Snoop Latency Override Value + Latency Tolerance Reporting, Snoop Latency Override Value. +**/ + UINT16 PcieRpSnoopLatencyOverrideValue[24]; + +/** Offset 0x087C - PCIE RP Non Snoop Latency Override Mode + Latency Tolerance Reporting, Non-Snoop Latency Override Mode. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; + +/** Offset 0x0894 - PCIE RP Non Snoop Latency Override Multiplier + Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. +**/ + UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; + +/** Offset 0x08AC - PCIE RP Non Snoop Latency Override Value + Latency Tolerance Reporting, Non-Snoop Latency Override Value. +**/ + UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; + +/** Offset 0x08DC - PCIE RP Slot Power Limit Scale + Specifies scale used for slot power limit value. Leave as 0 to set to default. +**/ + UINT8 PcieRpSlotPowerLimitScale[24]; + +/** Offset 0x08F4 - PCIE RP Slot Power Limit Value + Specifies upper limit on power supplie by slot. Leave as 0 to set to default. +**/ + UINT16 PcieRpSlotPowerLimitValue[24]; + +/** Offset 0x0924 - PCIE RP Upstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 5. +**/ + UINT8 PcieRpUptp[24]; + +/** Offset 0x093C - PCIE RP Downstream Port Transmiter Preset + Used during Gen3 Link Equalization. Used for all lanes. Default is 7. +**/ + UINT8 PcieRpDptp[24]; + +/** Offset 0x0954 - Usage type for ClkSrc + 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PcieClkSrcUsage[16]; + +/** Offset 0x0964 - ClkReq-to-ClkSrc mapping + Number of ClkReq signal assigned to ClkSrc +**/ + UINT8 PcieClkSrcClkReq[16]; + +/** Offset 0x0974 - PCIE Eq Ph3 Lane Param Cm + PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. +**/ + UINT8 PcieEqPh3LaneParamCm[24]; + +/** Offset 0x098C - PCIE Eq Ph3 Lane Param Cp + PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. +**/ + UINT8 PcieEqPh3LaneParamCp[24]; + +/** Offset 0x09A4 - PCIE Sw Eq CoeffList Cm + PCH_PCIE_EQ_PARAM. Coefficient C-1. +**/ + UINT8 PcieSwEqCoeffListCm[5]; + +/** Offset 0x09A9 - PCIE Sw Eq CoeffList Cp + PCH_PCIE_EQ_PARAM. Coefficient C+1. +**/ + UINT8 PcieSwEqCoeffListCp[5]; + +/** Offset 0x09AE - PCIE RP Enable Port8xh Decode + This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; + 1: Enable. + $EN_DIS +**/ + UINT8 PcieEnablePort8xhDecode; + +/** Offset 0x09AF - PCIE Port8xh Decode Port Index + The Index of PCIe Port that is selected for Port8xh Decode (0 Based). +**/ + UINT8 PchPciePort8xhDecodePortIndex; + +/** Offset 0x09B0 - PCIE Enable Peer Memory Write + This member describes whether Peer Memory Writes are enabled on the platform. + $EN_DIS +**/ + UINT8 PcieEnablePeerMemoryWrite; + +/** Offset 0x09B1 - PCIE Compliance Test Mode + Compliance Test Mode shall be enabled when using Compliance Load Board. + $EN_DIS +**/ + UINT8 PcieComplianceTestMode; + +/** Offset 0x09B2 - PCIE Rp Function Swap + Allows BIOS to use root port function number swapping when root port of function + 0 is disabled. + $EN_DIS +**/ + UINT8 PcieRpFunctionSwap; + +/** Offset 0x09B3 - Number of DevIntConfig Entry + Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr + must not be NULL. +**/ + UINT8 NumOfDevIntConfig; + +/** Offset 0x09B4 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. + The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. +**/ + UINT32 DevIntConfigPtr; + +/** Offset 0x09B8 - PIRQx to IRQx Map Config + PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for + PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy + 8259 PCI mode. +**/ + UINT8 PxRcConfig[8]; + +/** Offset 0x09C0 - Select GPIO IRQ Route + GPIO IRQ Select. The valid value is 14 or 15. +**/ + UINT8 GpioIrqRoute; + +/** Offset 0x09C1 - Select SciIrqSelect + SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. +**/ + UINT8 SciIrqSelect; + +/** Offset 0x09C2 - Select TcoIrqSelect + TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. +**/ + UINT8 TcoIrqSelect; + +/** Offset 0x09C3 - Enable/Disable Tco IRQ + Enable/disable TCO IRQ + $EN_DIS +**/ + UINT8 TcoIrqEnable; + +/** Offset 0x09C4 - Enable LOCKDOWN SMI + Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. + $EN_DIS +**/ + UINT8 PchLockDownGlobalSmi; + +/** Offset 0x09C5 - Enable LOCKDOWN BIOS Interface + Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. + $EN_DIS +**/ + UINT8 PchLockDownBiosInterface; + +/** Offset 0x09C6 - Enable LOCKDOWN BIOS LOCK + Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region + protection. + $EN_DIS +**/ + UINT8 PchLockDownBiosLock; + +/** Offset 0x09C7 - RTC CMOS MEMORY LOCK + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper + and and lower 128-byte bank of RTC RAM. + $EN_DIS +**/ + UINT8 PchLockDownRtcMemoryLock; + +/** Offset 0x09C8 - Unlock all GPIO pads + Force all GPIO pads to be unlocked for debug purpose. + $EN_DIS +**/ + UINT8 PchUnlockGpioPads; + +/** Offset 0x09C9 - Enable Power Optimizer + Enable DMI Power Optimizer on PCH side. + $EN_DIS +**/ + UINT8 PchPwrOptEnable; + +/** Offset 0x09CA - Pch Dmi Aspm Ctrl + ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto +**/ + UINT8 PchDmiAspmCtrl; + +/** Offset 0x09CB - PCH Flash Protection Ranges Write Enble + Write or erase is blocked by hardware. +**/ + UINT8 PchWriteProtectionEnable[5]; + +/** Offset 0x09D0 - PCH Flash Protection Ranges Read Enble + Read is blocked by hardware. +**/ + UINT8 PchReadProtectionEnable[5]; + +/** Offset 0x09D5 +**/ + UINT8 UnusedUpdSpace18[1]; + +/** Offset 0x09D6 - PCH Protect Range Limit + Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for + limit comparison. +**/ + UINT16 PchProtectedRangeLimit[5]; + +/** Offset 0x09E0 - PCH Protect Range Base + Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. +**/ + UINT16 PchProtectedRangeBase[5]; + +/** Offset 0x09EA - Enable PCH Io Apic Entry 24-119 + 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PchIoApicEntry24_119; + +/** Offset 0x09EB - Enable 8254 Static Clock Gating + Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time + might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support + legacy OS using 8254 timer. Also enable this while S0ix is enabled. + $EN_DIS +**/ + UINT8 Enable8254ClockGating; + +/** Offset 0x09EC - Enable 8254 Static Clock Gating On S3 + This is only applicable when Enable8254ClockGating is disabled. FSP will do the + 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This + avoids the SMI requirement for the programming. + $EN_DIS +**/ + UINT8 Enable8254ClockGatingOnS3; + +/** Offset 0x09ED - PCH Io Apic ID + This member determines IOAPIC ID. Default is 0x02. +**/ + UINT8 PchIoApicId; + +/** Offset 0x09EE - PCH Unlock SideBand access + The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before + 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. + $EN_DIS +**/ + UINT8 PchSbAccessUnlock; + +/** Offset 0x09EF - PCH Compatibility Revision ID + This member describes whether or not the CRID feature of PCH should be enabled. + $EN_DIS +**/ + UINT8 PchCrid; + +/** Offset 0x09F0 - PCH Pm PME_B0_S5_DIS + When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. + $EN_DIS +**/ + UINT8 PchPmPmeB0S5Dis; + +/** Offset 0x09F1 - PCH Pm Wol Enable Override + Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. + $EN_DIS +**/ + UINT8 PchPmWolEnableOverride; + +/** Offset 0x09F2 - PCH Pm Pcie Wake From DeepSx + Determine if enable PCIe to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmPcieWakeFromDeepSx; + +/** Offset 0x09F3 - PCH Pm WoW lan Enable + Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanEnable; + +/** Offset 0x09F4 - PCH Pm WoW lan DeepSx Enable + Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the + PWRM_CFG3 register. + $EN_DIS +**/ + UINT8 PchPmWoWlanDeepSxEnable; + +/** Offset 0x09F5 - PCH Pm Lan Wake From DeepSx + Determine if enable LAN to wake from deep Sx. + $EN_DIS +**/ + UINT8 PchPmLanWakeFromDeepSx; + +/** Offset 0x09F6 - PCH Pm Deep Sx Pol + Deep Sx Policy. + $EN_DIS +**/ + UINT8 PchPmDeepSxPol; + +/** Offset 0x09F7 - PCH Pm Slp S3 Min Assert + SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. +**/ + UINT8 PchPmSlpS3MinAssert; + +/** Offset 0x09F8 - PCH Pm Slp S4 Min Assert + SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. +**/ + UINT8 PchPmSlpS4MinAssert; + +/** Offset 0x09F9 - PCH Pm Slp Sus Min Assert + SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. +**/ + UINT8 PchPmSlpSusMinAssert; + +/** Offset 0x09FA - PCH Pm Slp A Min Assert + SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. +**/ + UINT8 PchPmSlpAMinAssert; + +/** Offset 0x09FB - PCH Pm Slp Strch Sus Up + Enable SLP_X Stretching After SUS Well Power Up. + $EN_DIS +**/ + UINT8 PchPmSlpStrchSusUp; + +/** Offset 0x09FC - PCH Pm Slp Lan Low Dc + Enable/Disable SLP_LAN# Low on DC Power. + $EN_DIS +**/ + UINT8 PchPmSlpLanLowDc; + +/** Offset 0x09FD - PCH Pm Pwr Btn Override Period + PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. +**/ + UINT8 PchPmPwrBtnOverridePeriod; + +/** Offset 0x09FE - PCH Energy Reporting + Disable/Enable PCH to CPU energy report feature. + $EN_DIS +**/ + UINT8 PchPmDisableEnergyReport; + +/** Offset 0x09FF - PCH Pm Disable Dsx Ac Present Pulldown + When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. + $EN_DIS +**/ + UINT8 PchPmDisableDsxAcPresentPulldown; + +/** Offset 0x0A00 - PCH Pm Disable Native Power Button + Power button native mode disable. + $EN_DIS +**/ + UINT8 PchPmDisableNativePowerButton; + +/** Offset 0x0A01 +**/ + UINT8 UnusedUpdSpace19[3]; + +/** Offset 0x0A04 - Power button debounce configuration + Debounce time for PWRBTN in microseconds. For values not supported by HW, they will + be rounded down to closest supported on. 0: disable, 250-1024000us: supported range +**/ + UINT32 PmcPowerButtonDebounceTime; + +/** Offset 0x0A08 - Disable Power Button debounce in PMC module + Disable Power Button debounce for PWRBTN in PMC module. '0': The 16ms debounce period + applies to all usages of the PWRBTN# pin (legacy behavior). '1': When a falling + edge occurs on the PWRBTN# pin, an interrupt is generated and the 16ms debounce + timer starts. Subsequent interrupts are masked while the debounce timer is running. +**/ + UINT8 PmcDisablePowerButtonDebounce; + +/** Offset 0x0A09 - PCH Pm Slp S0 Enable + Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. + $EN_DIS +**/ + UINT8 PchPmSlpS0Enable; + +/** Offset 0x0A0A - PCH Pm ME_WAKE_STS + Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmMeWakeSts; + +/** Offset 0x0A0B - PCH Pm WOL_OVR_WK_STS + Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. + $EN_DIS +**/ + UINT8 PchPmWolOvrWkSts; + +/** Offset 0x0A0C - Enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have + huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer + emulation must be enabled, and WDAT table must not be exposed to the OS. + $EN_DIS +**/ + UINT8 EnableTcoTimer; + +/** Offset 0x0A0D - VRAlert# Pin + When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling + to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchPmVrAlert; + +/** Offset 0x0A0E - PCH Pm Reset Power Cycle Duration + Could be customized in the unit of second. Please refer to EDS for all support settings. + 0 is default, 1 is 1 second, 2 is 2 seconds, ... +**/ + UINT8 PchPmPwrCycDur; + +/** Offset 0x0A0F - PCH Pm Pcie Pll Ssc + Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No + BIOS override. +**/ + UINT8 PchPmPciePllSsc; + +/** Offset 0x0A10 - S0i3 support + S0i3 platform support. When enabled ASL code is used to determine if platform can + go to S0i2 or S0i3 state. 0:Disable(S0i2 only), 1:Enable (Runtime in ASL) + $EN_DIS +**/ + UINT8 PchPmS0i3Support; + +/** Offset 0x0A11 - SLP_S0# Override + DEPRECATED + 0:Disabled, 1:Enabled +**/ + UINT8 SlpS0Override; + +/** Offset 0x0A12 - S0ix Override Settings + DEPRECATED + 0:No Change, 1:DCI OOB, 2:USB2 DbC +**/ + UINT8 SlpS0DisQForDebug; + +/** Offset 0x0A13 - PMC Debug Message Enable + When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW + will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix + $EN_DIS +**/ + UINT8 PmcDbgMsgEn; + +/** Offset 0x0A14 - Pointer of ChipsetInit format v2 Binary + ChipsetInit Binary format v2 Pointer. +**/ + UINT32 ChipsetInitBinPtr; + +/** Offset 0x0A18 - Length of ChipsetInit format v2 Binary + ChipsetInit Binary format v2 Length. +**/ + UINT32 ChipsetInitBinLen; + +/** Offset 0x0A1C - Enable PS_ON. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power + target that will be required by the California Energy Commission (CEC). When FALSE, + PS_ON is to be disabled. + $EN_DIS +**/ + UINT8 PsOnEnable; + +/** Offset 0x0A1D - Pmc Cpu C10 Gate Pin Enable + Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO + and VccSTG rails instead of SLP_S0# pin. + $EN_DIS +**/ + UINT8 PmcCpuC10GatePinEnable; + +/** Offset 0x0A1E - ModPHY SUS Power Domain Dynamic Gating + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on + PCH-H. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PmcModPhySusPgEnable; + +/** Offset 0x0A1F - PCH USB2 PHY Power Gating enable + 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY + Sus Well PG + $EN_DIS +**/ + UINT8 PmcUsb2PhySusPgEnable; + +/** Offset 0x0A20 - OS IDLE Mode Enable + Enable/Disable OS Idle Mode (PCH-N and PCH-H only) + $EN_DIS +**/ + UINT8 PmcOsIdleEnable; + +/** Offset 0x0A21 - Enable PMC CrashLog + Enable or Disable PMC CrashLog; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 PmcCrashLogEnable; + +/** Offset 0x0A22 - Enable CPPM Forced Alignment + Enable or Disable CPPM Forced Alignment; 0: Disable; 1: Enable. + $EN_DIS +**/ + UINT8 ForcedAlignmentEnable; + +/** Offset 0x0A23 - PCHHOT# pin + Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable + $EN_DIS +**/ + UINT8 PchHotEnable; + +/** Offset 0x0A24 - Thermal Throttling Custimized T0Level Value + Custimized T0Level value. +**/ + UINT16 PchT0Level; + +/** Offset 0x0A26 - Thermal Throttling Custimized T1Level Value + Custimized T1Level value. +**/ + UINT16 PchT1Level; + +/** Offset 0x0A28 - Thermal Throttling Custimized T2Level Value + Custimized T2Level value. +**/ + UINT16 PchT2Level; + +/** Offset 0x0A2A - Enable The Thermal Throttle + Enable the thermal throttle function. + $EN_DIS +**/ + UINT8 PchTTEnable; + +/** Offset 0x0A2B - PMSync State 13 + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force + at least T2 state. + $EN_DIS +**/ + UINT8 PchTTState13Enable; + +/** Offset 0x0A2C - Thermal Throttle Lock + Thermal Throttle Lock. + $EN_DIS +**/ + UINT8 PchTTLock; + +/** Offset 0x0A2D - Thermal Throttling Suggested Setting + Thermal Throttling Suggested Setting. + $EN_DIS +**/ + UINT8 TTSuggestedSetting; + +/** Offset 0x0A2E - Enable PCH Cross Throttling + Enable/Disable PCH Cross Throttling + $EN_DIS +**/ + UINT8 TTCrossThrottling; + +/** Offset 0x0A2F - DMI Thermal Sensor Autonomous Width Enable + DMI Thermal Sensor Autonomous Width Enable. + $EN_DIS +**/ + UINT8 PchDmiTsawEn; + +/** Offset 0x0A30 - DMI Thermal Sensor Suggested Setting + DMT thermal sensor suggested representative values. + $EN_DIS +**/ + UINT8 DmiSuggestedSetting; + +/** Offset 0x0A31 - Thermal Sensor 0 Target Width + Thermal Sensor 0 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS0TW; + +/** Offset 0x0A32 - Thermal Sensor 1 Target Width + Thermal Sensor 1 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS1TW; + +/** Offset 0x0A33 - Thermal Sensor 2 Target Width + Thermal Sensor 2 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS2TW; + +/** Offset 0x0A34 - Thermal Sensor 3 Target Width + Thermal Sensor 3 Target Width. + 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 +**/ + UINT8 DmiTS3TW; + +/** Offset 0x0A35 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. + $EN_DIS +**/ + UINT8 PchMemoryThrottlingEnable; + +/** Offset 0x0A36 - Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPmsyncEnable[2]; + +/** Offset 0x0A38 - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryC0TransmitEnable[2]; + +/** Offset 0x0A3A - Enable Memory Thermal Throttling + Enable Memory Thermal Throttling. +**/ + UINT8 PchMemoryPinSelection[2]; + +/** Offset 0x0A3C - Thermal Device Temperature + Decides the temperature. +**/ + UINT16 PchTemperatureHotLevel; + +/** Offset 0x0A3E - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states + Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtV1p05RailEnabledStates; + +/** Offset 0x0A3F +**/ + UINT8 UnusedUpdSpace20; + +/** Offset 0x0A40 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtV1p05RailVoltage; + +/** Offset 0x0A42 - External V1P05 Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtV1p05RailIccMax; + +/** Offset 0x0A43 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states + Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailEnabledStates; + +/** Offset 0x0A44 - External Vnn Voltage Value that will be used in S0ix/Sx states + Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailVoltage; + +/** Offset 0x0A46 - External Vnn Icc Max Value that will be used in S0ix/Sx states + Granularity of this setting is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailIccMax; + +/** Offset 0x0A47 - Mask to enable the usage of external Vnn VR rail in Sx states + Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in + Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 +**/ + UINT8 PchFivrExtVnnRailSxEnabledStates; + +/** Offset 0x0A48 - External Vnn Voltage Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments + (0=0mV, 1=2.5mV, 2=5mV...) +**/ + UINT16 PchFivrExtVnnRailSxVoltage; + +/** Offset 0x0A4A - External Vnn Icc Max Value that will be used in Sx states + Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting + is 1mA and maximal possible value is 200mA +**/ + UINT8 PchFivrExtVnnRailSxIccMax; + +/** Offset 0x0A4B - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to low current mode voltage,for PCH-LP ICL U/Y board with D0 stepping need to program + it to 12us +**/ + UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; + +/** Offset 0x0A4C - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; + +/** Offset 0x0A4D - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage + This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX + to retention mode voltage. +**/ + UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; + +/** Offset 0x0A4E - Transition time in microseconds from Off (0V) to High Current Mode Voltage + This field has 1us resolution. When value is 0 Transition to 0V is disabled,for + PCH-LP ICL U/Y board with D0 stepping need to program it to 120us +**/ + UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; + +/** Offset 0x0A50 - FIVR Dynamic Power Management + Enable/Disable FIVR Dynamic Power Management. + $EN_DIS +**/ + UINT8 PchFivrDynPm; + +/** Offset 0x0A51 - Serial IO UART DBG2 table + Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; + 1: Enable. +**/ + UINT8 SerialIoUartDbg2[3]; + +/** Offset 0x0A54 - Trace Hub Memory Base + If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate + trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub + memory is configured properly. +**/ + UINT32 TraceHubMemBase; + +/** Offset 0x0A58 - ITSS IRQ Polarity. + Configuration for ITSS IPC[0-3] registers. +**/ + UINT32 ItssIrqPolarity[4]; + +/** Offset 0x0A68 - PCH PMC Energy Report Debug mode + Disable/Enable Energy Reporting Debug Mode. + $EN_DIS +**/ + UINT8 PchPmEnergyReportDebugMode; + +/** Offset 0x0A69 +**/ + UINT8 UnusedUpdSpace21[4]; + +/** Offset 0x0A6D +**/ + UINT8 ReservedFspsUpd[11]; +} FSP_S_CONFIG; /** Fsp S UPD Configuration **/ @@ -59,11 +3596,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x07AD +/** Offset 0x0A78 **/ - FSP_S_TEST_CONFIG FspsTestConfig; + UINT8 UnusedUpdSpace22[6]; -/** Offset 0x0A80 +/** Offset 0x0A7E **/ UINT16 UpdTerminator; } FSPS_UPD; diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 4a13b29c53..ac9ee48888 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -77,12 +77,19 @@ #define MIN_ROM_KB 256 #define ALIGN(val, by) (((val) + (by) - 1) & ~((by) - 1)) +#define _MAX(A, B) (((A) > (B)) ? (A) : (B)) +#define ERASE_ALIGNMENT 0x1000U #define TABLE_ALIGNMENT 0x1000U #define BLOB_ALIGNMENT 0x100U +#define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) +#define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) + +#define DEFAULT_SOFT_FUSE_CHAIN "0x1" #define EMBEDDED_FW_SIGNATURE 0x55aa55aa -#define PSP_COOKIE 0x50535024 /* 'PSP$' */ -#define PSP2_COOKIE 0x50535032 /* 'PSP2' */ +#define PSP_COOKIE 0x50535024 /* 'PSP$' */ +#define PSPL2_COOKIE 0x324c5024 /* '2LP$' */ +#define PSP2_COOKIE 0x50535032 /* 'PSP2' */ /* * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP @@ -171,6 +178,7 @@ static void usage(void) printf("\nPSP options:\n"); printf("-A | --combo-capable Place PSP directory pointer at Embedded Firmware\n"); printf(" offset able to support combo directory\n"); + printf("-M | --multilevel Generate primary and secondary tables\n"); printf("-p | --pubkey Add pubkey\n"); printf("-b | --bootloader Add bootloader\n"); printf("-S | --subprogram Sets subprogram field for the next firmware\n"); @@ -184,6 +192,7 @@ static void usage(void) printf("-u | --trustletkey Add trustletkey\n"); printf("-w | --smufirmware2 Add smufirmware2\n"); printf("-m | --smuscs Add smuscs\n"); + printf("-T | --soft-fuse Override default soft fuse values\n"); printf("\n-o | --output output filename\n"); printf("-f | --flashsize ROM size in bytes\n"); printf(" size must be larger than %dKB\n", @@ -207,35 +216,44 @@ typedef enum _amd_fw_type { AMD_FW_PSP_SMU_FIRMWARE2 = 18, AMD_PSP_FUSE_CHAIN = 11, AMD_FW_PSP_SMUSCS = 95, - + AMD_FW_L2_PTR = 0x40, AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, AMD_FW_INVALID, } amd_fw_type; +#define PSP_LVL1 0x1 +#define PSP_LVL2 0x2 +#define PSP_BOTH (PSP_LVL1 | PSP_LVL2) typedef struct _amd_fw_entry { amd_fw_type type; uint8_t subprog; char *filename; + int level; + uint64_t other; } amd_fw_entry; static amd_fw_entry amd_psp_fw_table[] = { - { .type = AMD_FW_PSP_PUBKEY }, - { .type = AMD_FW_PSP_BOOTLOADER }, - { .type = AMD_FW_PSP_SMU_FIRMWARE }, - { .type = AMD_FW_PSP_RECOVERY }, - { .type = AMD_FW_PSP_RTM_PUBKEY }, - { .type = AMD_FW_PSP_SECURED_OS }, - { .type = AMD_FW_PSP_NVRAM }, - { .type = AMD_FW_PSP_SECURED_DEBUG }, - { .type = AMD_FW_PSP_TRUSTLETS }, - { .type = AMD_FW_PSP_TRUSTLETKEY }, - { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1 }, - { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, - { .type = AMD_FW_PSP_SMUSCS }, - { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, + { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SECURED_OS, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_NVRAM, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 2, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SECURED_DEBUG, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_TRUSTLETS, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_TRUSTLETKEY, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, + { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH }, { .type = AMD_FW_INVALID }, }; @@ -312,11 +330,20 @@ typedef struct _context { #define BUFF_TO_RUN(ctx, ptr) RUN_OFFSET((ctx), ((char *)(ptr) - (ctx).rom)) #define BUFF_ROOM(ctx) ((ctx).rom_size - (ctx).current) -static void *new_psp_dir(context *ctx) +static void *new_psp_dir(context *ctx, int multi) { void *ptr; - ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); + /* + * Force both onto boundary when multi. Primary table is after + * updatable table, so alignment ensures primary can stay intact + * if secondary is reprogrammed. + */ + if (multi) + ctx->current = ALIGN(ctx->current, TABLE_ERASE_ALIGNMENT); + else + ctx->current = ALIGN(ctx->current, TABLE_ALIGNMENT); + ptr = BUFF_CURRENT(*ctx); ctx->current += sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry); @@ -336,9 +363,15 @@ static void *new_combo_dir(context *ctx) static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) { - if (cookie == PSP2_COOKIE) { + psp_combo_directory *cdir = directory; + psp_directory_table *dir = directory; + + if (!count) + return; + + switch (cookie) { + case PSP2_COOKIE: /* caller is responsible for lookup mode */ - psp_combo_directory *cdir = directory; cdir->header.cookie = cookie; cdir->header.num_entries = count; cdir->header.reserved[0] = 0; @@ -349,8 +382,9 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) + sizeof(cdir->header.num_entries) + sizeof(cdir->header.lookup) + 2 * sizeof(cdir->header.reserved[0])); - } else { - psp_directory_table *dir = directory; + break; + case PSP_COOKIE: + case PSPL2_COOKIE: dir->header.cookie = cookie; dir->header.num_entries = count; dir->header.reserved = 0; @@ -359,6 +393,7 @@ static void fill_dir_header(void *directory, uint32_t count, uint32_t cookie) count * sizeof(psp_directory_entry) + sizeof(dir->header.num_entries) + sizeof(dir->header.reserved)); + break; } } @@ -437,20 +472,65 @@ static void integrate_firmwares(context *ctx, static void integrate_psp_firmwares(context *ctx, psp_directory_table *pspdir, - amd_fw_entry *fw_table) + psp_directory_table *pspdir2, + amd_fw_entry *fw_table, + uint32_t cookie) { ssize_t bytes; unsigned int i, count; + int level; + + /* This function can create a primary table, a secondary table, or a + * flattened table which contains all applicable types. These if-else + * statements infer what the caller intended. If a 2nd-level cookie + * is passed, clearly a 2nd-level table is intended. However, a + * 1st-level cookie may indicate level 1 or flattened. If the caller + * passes a pointer to a 2nd-level table, then assume not flat. + */ + if (cookie == PSPL2_COOKIE) + level = PSP_LVL2; + else if (pspdir2) + level = PSP_LVL1; + else + level = PSP_BOTH; ctx->current = ALIGN(ctx->current, BLOB_ALIGNMENT); for (i = 0, count = 0; fw_table[i].type != AMD_FW_INVALID; i++) { + if (!(fw_table[i].level & level)) + continue; + if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { pspdir->entries[count].type = fw_table[i].type; pspdir->entries[count].subprog = fw_table[i].subprog; pspdir->entries[count].rsvd = 0; pspdir->entries[count].size = 0xFFFFFFFF; - pspdir->entries[count].addr = 1; + pspdir->entries[count].addr = fw_table[i].other; + count++; + } else if (fw_table[i].type == AMD_FW_PSP_NVRAM) { + if (fw_table[i].filename == NULL) + continue; + /* TODO: Add a way to reserve for NVRAM without + * requiring a filename. This isn't a feature used + * by coreboot systems, so priority is very low. + */ + ctx->current = ALIGN(ctx->current, ERASE_ALIGNMENT); + bytes = copy_blob(BUFF_CURRENT(*ctx), + fw_table[i].filename, BUFF_ROOM(*ctx)); + if (bytes <= 0) { + free(ctx->rom); + exit(1); + } + + pspdir->entries[count].type = fw_table[i].type; + pspdir->entries[count].subprog = fw_table[i].subprog; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = ALIGN(bytes, + ERASE_ALIGNMENT); + pspdir->entries[count].addr = RUN_CURRENT(*ctx); + + ctx->current = ALIGN(ctx->current + bytes, + BLOB_ERASE_ALIGNMENT); count++; } else if (fw_table[i].filename != NULL) { bytes = copy_blob(BUFF_CURRENT(*ctx), @@ -474,16 +554,28 @@ static void integrate_psp_firmwares(context *ctx, } } + if (pspdir2) { + pspdir->entries[count].type = AMD_FW_L2_PTR; + pspdir->entries[count].subprog = 0; + pspdir->entries[count].rsvd = 0; + pspdir->entries[count].size = sizeof(pspdir2->header) + + pspdir2->header.num_entries + * sizeof(psp_directory_entry); + + pspdir->entries[count].addr = BUFF_TO_RUN(*ctx, pspdir2); + count++; + } + if (count > MAX_PSP_ENTRIES) { printf("Error: PSP entries exceed max allowed items\n"); free(ctx->rom); exit(1); } - fill_dir_header(pspdir, count, PSP_COOKIE); + fill_dir_header(pspdir, count, cookie); } -static const char *optstring = "x:i:g:AS:p:b:s:r:k:c:n:d:t:u:w:m:o:f:l:h"; +static const char *optstring = "x:i:g:AMS:p:b:s:r:k:c:n:d:t:u:w:m:T:o:f:l:h"; static struct option long_options[] = { {"xhci", required_argument, 0, 'x' }, @@ -491,6 +583,7 @@ static struct option long_options[] = { {"gec", required_argument, 0, 'g' }, /* PSP */ {"combo-capable", no_argument, 0, 'A' }, + {"multilevel", no_argument, 0, 'M' }, {"subprogram", required_argument, 0, 'S' }, {"pubkey", required_argument, 0, 'p' }, {"bootloader", required_argument, 0, 'b' }, @@ -504,6 +597,7 @@ static struct option long_options[] = { {"trustletkey", required_argument, 0, 'u' }, {"smufirmware2", required_argument, 0, 'w' }, {"smuscs", required_argument, 0, 'm' }, + {"soft-fuse", required_argument, 0, 'T' }, {"output", required_argument, 0, 'o' }, {"flashsize", required_argument, 0, 'f' }, {"location", required_argument, 0, 'l' }, @@ -512,6 +606,19 @@ static struct option long_options[] = { {NULL, 0, 0, 0 } }; +static void register_fw_fuse(char *str) +{ + int i; + + for (i = 0; i < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type != AMD_PSP_FUSE_CHAIN) + continue; + + amd_psp_fw_table[i].other = strtoull(str, NULL, 16); + return; + } +} + static void register_fw_filename(amd_fw_type type, uint8_t sub, char filename[]) { unsigned int i; @@ -543,6 +650,7 @@ int main(int argc, char **argv) embedded_firmware *amd_romsig; psp_directory_table *pspdir; int comboable = 0; + int fuse_defined = 0; int targetfd; char *output = NULL; context ctx = { @@ -552,6 +660,7 @@ int main(int argc, char **argv) uint32_t romsig_offset; uint32_t rom_base_address; uint8_t sub = 0; + int multi = 0; while (1) { int optindex = 0; @@ -564,19 +673,22 @@ int main(int argc, char **argv) switch (c) { case 'x': register_fw_filename(AMD_FW_XHCI, sub, optarg); - sub = 0; /* subprogram is N/A but clear anyway */ + sub = 0; break; case 'i': register_fw_filename(AMD_FW_IMC, sub, optarg); - sub = 0; /* subprogram is N/A but clear anyway */ + sub = 0; break; case 'g': register_fw_filename(AMD_FW_GEC, sub, optarg); - sub = 0; /* subprogram is N/A but clear anyway */ + sub = 0; break; case 'A': comboable = 1; break; + case 'M': + multi = 1; + break; case 'S': sub = (uint8_t)strtoul(optarg, &tmp, 16); break; @@ -635,6 +747,11 @@ int main(int argc, char **argv) register_fw_filename(AMD_FW_PSP_SMUSCS, sub, optarg); sub = 0; break; + case 'T': + register_fw_fuse(optarg); + fuse_defined = 1; + sub = 0; + break; case 'o': output = optarg; break; @@ -663,6 +780,9 @@ int main(int argc, char **argv) } } + if (!fuse_defined) + register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); + if (!output) { printf("Error: Output value is not specified.\n\n"); retval = 1; @@ -733,8 +853,21 @@ int main(int argc, char **argv) ctx.current = ALIGN(ctx.current, 0x10000U); /* todo: is necessary? */ - pspdir = new_psp_dir(&ctx); - integrate_psp_firmwares(&ctx, pspdir, amd_psp_fw_table); + if (multi) { + /* Do 2nd PSP directory followed by 1st */ + psp_directory_table *pspdir2 = new_psp_dir(&ctx, multi); + integrate_psp_firmwares(&ctx, pspdir2, 0, + amd_psp_fw_table, PSPL2_COOKIE); + + pspdir = new_psp_dir(&ctx, multi); + integrate_psp_firmwares(&ctx, pspdir, pspdir2, + amd_psp_fw_table, PSP_COOKIE); + } else { + /* flat: PSP 1 cookie and no pointer to 2nd table */ + pspdir = new_psp_dir(&ctx, multi); + integrate_psp_firmwares(&ctx, pspdir, 0, + amd_psp_fw_table, PSP_COOKIE); + } if (comboable) amd_romsig->comboable = BUFF_TO_RUN(ctx, pspdir); diff --git a/util/autoport/main.go b/util/autoport/main.go index dc02a8d1fd..ab49a14a9d 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -517,6 +517,8 @@ func (g GenericPCI) Scan(ctx Context, addr PCIDevData) { PutPCIDevParent(addr, g.Comment, g.MissingParent) } +var IGDEnabled bool = false + func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { KconfigString["VGA_BIOS_ID"] = fmt.Sprintf("%04x,%04x", addr.PCIVenID, @@ -525,6 +527,7 @@ func (g GenericVGA) Scan(ctx Context, addr PCIDevData) { addr.PCIVenID, addr.PCIDevID) PutPCIDevParent(addr, g.Comment, g.MissingParent) + IGDEnabled = true } func makeKconfigName(ctx Context) { @@ -748,6 +751,12 @@ func main() { ScanRoot(ctx) + if IGDEnabled { + KconfigBool["MAINBOARD_HAS_LIBGFXINIT"] = true + KconfigComment["MAINBOARD_HAS_LIBGFXINIT"] = "FIXME: check this" + AddRAMStageFile("gma-mainboard.ads", "CONFIG_MAINBOARD_USE_LIBGFXINIT") + } + if len(ROMStageFiles) > 0 || len(RAMStageFiles) > 0 || len(SMMFiles) > 0 { mf := Create(ctx, "Makefile.inc") defer mf.Close() @@ -881,4 +890,45 @@ DefinitionBlock( } `) + if IGDEnabled { + gma := Create(ctx, "gma-mainboard.ads") + defer gma.Close() + + gma.WriteString(`-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; +`) + } } diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 6c5e784569..a1a327f6ed 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -925,15 +925,24 @@ static void set_chipdensity(const char *filename, char *image, int size, write_image(filename, image, size); } +static int check_region(const frba_t *frba, unsigned int region_type) +{ + region_t region; + + if (!frba) + return 0; + + region = get_region(frba, region_type); + return !!((region.base < region.limit) && (region.size > 0)); +} + static void lock_descriptor(const char *filename, char *image, int size) { int wr_shift, rd_shift; fmba_t *fmba = find_fmba(image, size); + const frba_t *frba = find_frba(image, size); if (!fmba) exit(EXIT_FAILURE); - /* TODO: Dynamically take Platform Data Region and GbE Region - * into regard. - */ if (ifd_version >= IFD_VERSION_2) { wr_shift = FLMSTR_WR_SHIFT_V2; @@ -969,36 +978,66 @@ static void lock_descriptor(const char *filename, char *image, int size) case PLATFORM_CNL: case PLATFORM_ICL: case PLATFORM_SKLKBL: - /* CPU/BIOS can read descriptor, BIOS, EC and GbE. */ - fmba->flmstr1 |= 0x10b << rd_shift; - /* CPU/BIOS can write BIOS and Gbe. */ - fmba->flmstr1 |= 0xa << wr_shift; - /* ME can read descriptor, ME and GbE. */ - fmba->flmstr2 |= 0xd << rd_shift; + /* CPU/BIOS can read descriptor and BIOS. */ + fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; + /* CPU/BIOS can write BIOS. */ + fmba->flmstr1 |= (1 << REGION_BIOS) << wr_shift; + /* ME can read descriptor and ME. */ + fmba->flmstr2 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr2 |= (1 << REGION_ME) << rd_shift; /* ME can write ME. */ - fmba->flmstr2 |= 0x4 << wr_shift; - /* GbE can read GbE and descriptor. */ - fmba->flmstr3 |= 0x9 << rd_shift; - /* GbE can write GbE. */ - fmba->flmstr3 |= 0x8 << wr_shift; - /* EC can read EC and descriptor. */ - fmba->flmstr5 |= 0x101 << rd_shift; - /* EC can write EC region. */ - fmba->flmstr5 |= 0x100 << wr_shift; + fmba->flmstr2 |= (1 << REGION_ME) << wr_shift; + if (check_region(frba, REGION_GBE)) { + /* BIOS can read/write GbE. */ + fmba->flmstr1 |= (1 << REGION_GBE) << rd_shift; + fmba->flmstr1 |= (1 << REGION_GBE) << wr_shift; + /* ME can read GbE. */ + fmba->flmstr2 |= (1 << REGION_GBE) << rd_shift; + /* GbE can read descriptor and read/write GbE.. */ + fmba->flmstr3 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr3 |= (1 << REGION_GBE) << rd_shift; + fmba->flmstr3 |= (1 << REGION_GBE) << wr_shift; + } + if (check_region(frba, REGION_PDR)) { + /* BIOS can read/write PDR. */ + fmba->flmstr1 |= (1 << REGION_PDR) << rd_shift; + fmba->flmstr1 |= (1 << REGION_PDR) << wr_shift; + } + if (check_region(frba, REGION_EC)) { + /* BIOS can read EC. */ + fmba->flmstr1 |= (1 << REGION_EC) << rd_shift; + /* EC can read descriptor and read/write EC. */ + fmba->flmstr5 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr5 |= (1 << REGION_EC) << rd_shift; + fmba->flmstr5 |= (1 << REGION_EC) << wr_shift; + } break; default: - /* CPU/BIOS can read descriptor, BIOS, and GbE. */ - fmba->flmstr1 |= 0xb << rd_shift; - /* CPU/BIOS can write BIOS and GbE. */ - fmba->flmstr1 |= 0xa << wr_shift; - /* ME can read descriptor, ME, and GbE. */ - fmba->flmstr2 |= 0xd << rd_shift; - /* ME can write ME and GbE. */ - fmba->flmstr2 |= 0xc << wr_shift; - /* GbE can write only GbE. */ - fmba->flmstr3 |= 0x8 << rd_shift; - /* GbE can read only GbE. */ - fmba->flmstr3 |= 0x8 << wr_shift; + /* CPU/BIOS can read descriptor and BIOS. */ + fmba->flmstr1 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr1 |= (1 << REGION_BIOS) << rd_shift; + /* CPU/BIOS can write BIOS. */ + fmba->flmstr1 |= (1 << REGION_BIOS) << wr_shift; + /* ME can read descriptor and ME. */ + fmba->flmstr2 |= (1 << REGION_DESC) << rd_shift; + fmba->flmstr2 |= (1 << REGION_ME) << rd_shift; + /* ME can write ME. */ + fmba->flmstr2 |= (1 << REGION_ME) << wr_shift; + if (check_region(frba, REGION_GBE)) { + /* BIOS can read GbE. */ + fmba->flmstr1 |= (1 << REGION_GBE) << rd_shift; + /* BIOS can write GbE. */ + fmba->flmstr1 |= (1 << REGION_GBE) << wr_shift; + /* ME can read GbE. */ + fmba->flmstr2 |= (1 << REGION_GBE) << rd_shift; + /* ME can write GbE. */ + fmba->flmstr2 |= (1 << REGION_GBE) << wr_shift; + /* GbE can write GbE. */ + fmba->flmstr3 |= (1 << REGION_GBE) << rd_shift; + /* GbE can read GbE. */ + fmba->flmstr3 |= (1 << REGION_GBE) << wr_shift; + } break; } diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h index 49463b91bf..f3b9a53e06 100644 --- a/util/ifdtool/ifdtool.h +++ b/util/ifdtool/ifdtool.h @@ -94,6 +94,15 @@ typedef struct { #define MAX_REGIONS 9 #define MAX_REGIONS_OLD 5 +enum flash_regions { + REGION_DESC, + REGION_BIOS, + REGION_ME, + REGION_GBE, + REGION_PDR, + REGION_EC = 8, +}; + typedef struct { uint32_t flreg[MAX_REGIONS]; } __attribute__((packed)) frba_t; diff --git a/util/superiotool/superiotool.h b/util/superiotool/superiotool.h index 1a10fb63ab..6e59933792 100644 --- a/util/superiotool/superiotool.h +++ b/util/superiotool/superiotool.h @@ -127,9 +127,15 @@ and print its vendor, name, ID, revision, and config port.\n" #define EOT -1 /* End Of Table */ #define NOLDN -2 /* NO LDN needed */ -#define NANA -3 /* Not Available */ +#define NANA -3 /* Not Available: + Used for registers having externally controlled + values that can change during runtime like + GPIO input value registers. */ #define RSVD -4 /* Reserved */ -#define MISC -5 /* Needs special comment in output */ +#define MISC -5 /* Needs special comment in output: + Used for registers depending on external pin straps + configuring static, but board-specific settings like + SIO base address or AMD/Intel power seqencing type. */ #define MAXLDN 0x14 /* Biggest LDN */ #define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */ #define MAXNUMIDX 170 /* Maximum number of indices */