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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-60

Browse Source 
Creator:  Li-Ta Lo <ollie@lanl.gov>

More Via EPIA 

more via epia stuff, including the trival but fatal bug in auto.c


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1978 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical)
2005-07-06 18:17:33 +00:00
parent f642a4795a
commit 80e3d96d0a
15 changed files with 758 additions and 732 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/mainboard/via/epia/Config.lb
View File

@@ -126,20 +126,18 @@ config chip.h
chip northbridge/via/vt8601 chip northbridge/via/vt8601
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on device pci 0.0 on end # Northbridge
device pci 0.1 on # AGP bridge
# chip drivers/pci/onboard # Integrated VGA
# device pci 0.0 on end
# register "rom_adress" = "0xfff80000"
# end
end
chip southbridge/via/vt8231 chip southbridge/via/vt8231
register "enable_usb" = "0"
register "enable_native_ide" = "0" register "enable_native_ide" = "0"
register "enable_com_ports" = "1" register "enable_com_ports" = "1"
register "enable_keyboard" = "0" register "enable_keyboard" = "0"
register "enable_nvram" = "1" device pci 11.0 on # Southbrdge
device pci 11.0 on # Southbridge
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb
device pci 11.3 off end # Usb
device pci 11.4 off end # ACPI
device pci 11.5 off end # Audio
device pci 11.6 on # Com
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
@@ -164,6 +162,8 @@ chip northbridge/via/vt8601
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
register "com1" = "{1}"
end
device pnp 2e.6 off end # CIR device pnp 2e.6 off end # CIR
device pnp 2e.7 off end # GAME_MIDI_GIPO1 device pnp 2e.7 off end # GAME_MIDI_GIPO1
device pnp 2e.8 off end # GPIO2 device pnp 2e.8 off end # GPIO2
@@ -172,14 +172,17 @@ chip northbridge/via/vt8601
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
end end
register "com1" = "{1}"
end
end end
device pci 11.1 on end # Ide
device pci 11.2 off end # Usb port 0-1
device pci 11.3 off end # Usb port 2-3
device pci 11.4 off end # ACPI
device pci 11.5 off end # AC97 Audio
device pci 11.6 on end # AC97 Modem
device pci 12.0 on end # Ethernet device pci 12.0 on end # Ethernet
end end
end end
end
end
chip cpu/via/model_centaur chip cpu/via/model_centaur
end end
end end

19
src/mainboard/via/epia/Options.lb
View File

@@ -1,3 +1,10 @@
uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses TTYS0_BAUD
uses TTYS0_BASE
uses TTYS0_LCS
uses CONFIG_CHIP_NAME
uses HAVE_MP_TABLE uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE uses USE_FALLBACK_IMAGE
@@ -40,6 +47,18 @@ uses MAXIMUM_CONSOLE_LOGLEVEL
uses DEFAULT_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVEL
uses MAXIMUM_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
default TTYS0_BAUD=19200
# Select the serial console base port
default TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
default TTYS0_LCS=0x3
default CONFIG_CHIP_NAME=1
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024 default ROM_SIZE = 256*1024

22
src/mainboard/via/epia/auto.c
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@@ -2,9 +2,6 @@
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#if 0
#include <cpu/x86/lapic.h>
#endif
#include <arch/io.h> #include <arch/io.h>
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <arch/romcc_io.h> #include <arch/romcc_io.h>
@@ -30,18 +27,8 @@ void udelay(int usecs)
#include "debug.c" #include "debug.c"
#include "southbridge/via/vt8231/vt8231_early_smbus.c" #include "southbridge/via/vt8231/vt8231_early_smbus.c"
#include "southbridge/via/vt8231/vt8231_early_serial.c" #include "southbridge/via/vt8231/vt8231_early_serial.c"
static void memreset_setup(void)
{
}
/*
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
*/
static inline int spd_read_byte(unsigned device, unsigned address) static inline int spd_read_byte(unsigned device, unsigned address)
{ {
unsigned char c; unsigned char c;
@@ -49,8 +36,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return c; return c;
} }
#include "northbridge/via/vt8601/raminit.c" #include "northbridge/via/vt8601/raminit.c"
/* /*
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
@@ -66,6 +51,7 @@ static void enable_mainboard_devices(void)
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n"); die("Southbridge not found!!!\n");
} }
pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff); pci_write_config8(dev, 0x51, 0xff);
#if 0 #if 0
@@ -87,9 +73,9 @@ static void enable_mainboard_devices(void)
static void enable_shadow_ram(void) static void enable_shadow_ram(void)
{ {
device_t dev = 0; /* no need to look up 0:0.0 */ device_t dev = 0;
unsigned char shadowreg; unsigned char shadowreg;
/* dev 0 for southbridge */
shadowreg = pci_read_config8(dev, 0x63); shadowreg = pci_read_config8(dev, 0x63);
/* 0xf0000-0xfffff */ /* 0xf0000-0xfffff */
shadowreg |= 0x30; shadowreg |= 0x30;
@@ -113,8 +99,8 @@ static void main(unsigned long bist)
enable_mainboard_devices(); enable_mainboard_devices();
enable_smbus(); enable_smbus();
enable_shadow_ram(); enable_shadow_ram();
/* /*
memreset_setup();
this is way more generic than we need. this is way more generic than we need.
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
*/ */

4
src/northbridge/via/vt8601/northbridge.c
View File

@@ -29,8 +29,6 @@ static void northbridge_init(device_t dev)
pci_write_config8(dev, 0x76, 0x52); pci_write_config8(dev, 0x76, 0x52);
} }
static struct device_operations northbridge_operations = { static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
@@ -46,8 +44,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
.device = 0x0601, /* 0x8601 is the AGP bridge? */ .device = 0x0601, /* 0x8601 is the AGP bridge? */
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev) static void pci_domain_read_resources(device_t dev)

31
src/northbridge/via/vt8601/raminit.c
View File

@@ -69,8 +69,6 @@ void dimms_write(int x)
} }
} }
#ifdef DEBUG_SETNORTHB #ifdef DEBUG_SETNORTHB
void setnorthb(device_t north, uint8_t reg, uint8_t val) void setnorthb(device_t north, uint8_t reg, uint8_t val)
{ {
@@ -85,8 +83,7 @@ void setnorthb(device_t north, uint8_t reg, uint8_t val)
#define setnorthb pci_write_config8 #define setnorthb pci_write_config8
#endif #endif
void void dumpnorth(device_t north)
dumpnorth(device_t north)
{ {
unsigned int r, c; unsigned int r, c;
for (r = 0;; r += 16) { for (r = 0;; r += 16) {
@@ -104,12 +101,10 @@ dumpnorth(device_t north)
static void sdram_set_registers(const struct mem_controller *ctrl) static void sdram_set_registers(const struct mem_controller *ctrl)
{ {
device_t north = (device_t) 0; device_t north = (device_t) PCI_DEV(0, 0, 0);
uint8_t c, r; uint8_t c, r;
print_err("vt8601 init starting\r\n"); print_err("vt8601 init starting\r\n");
north = pci_locate_device(PCI_ID(0x1106, 0x8601), 0);
north = 0;
print_debug_hex32(north); print_debug_hex32(north);
print_debug(" is the north\n"); print_debug(" is the north\n");
print_debug_hex16(pci_read_config16(north, 0)); print_debug_hex16(pci_read_config16(north, 0));
@@ -120,17 +115,21 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
/* All we are doing now is setting initial known-good values that will /* All we are doing now is setting initial known-good values that will
* be revised later as we read SPD * be revised later as we read SPD
*/ */
// memory clk enable. We are not using ECC // memory clk enable. We are not using ECC
pci_write_config8(north, 0x78, 0x01); pci_write_config8(north, 0x78, 0x01);
print_debug_hex8(pci_read_config8(north, 0x78)); print_debug_hex8(pci_read_config8(north, 0x78));
// dram control, see the book. // dram control, see the book.
#if DIMM_PC133 #if DIMM_PC133
pci_write_config8(north, 0x68, 0x52); pci_write_config8(north, 0x68, 0x52);
#else #else
pci_write_config8(north, 0x68, 0x42); pci_write_config8(north, 0x68, 0x42);
#endif #endif
// dram control, see the book. // dram control, see the book.
pci_write_config8(north, 0x6B, 0x0c); pci_write_config8(north, 0x6B, 0x0c);
// Initial setting, 256MB in each bank, will be rewritten later. // Initial setting, 256MB in each bank, will be rewritten later.
pci_write_config8(north, 0x5A, 0x20); pci_write_config8(north, 0x5A, 0x20);
print_debug_hex8(pci_read_config8(north, 0x5a)); print_debug_hex8(pci_read_config8(north, 0x5a));
@@ -146,6 +145,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
// SDRAM in all banks // SDRAM in all banks
pci_write_config8(north, 0x60, 0x3F); pci_write_config8(north, 0x60, 0x3F);
// DRAM timing. I'm suspicious of this // DRAM timing. I'm suspicious of this
// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5. // This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
// ras precharge 4T, RAS pulse 5T // ras precharge 4T, RAS pulse 5T
@@ -173,7 +173,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
// refresh counter, disabled. // refresh counter, disabled.
pci_write_config8(north, 0x6A, 0x00); pci_write_config8(north, 0x6A, 0x00);
// clkenable configuration. kevinh FIXME - add precharge // clkenable configuration. kevinh FIXME - add precharge
pci_write_config8(north, 0x6C, 0x00); pci_write_config8(north, 0x6C, 0x00);
// dram read latch delay of 1 ns, MD drive 8 mA, // dram read latch delay of 1 ns, MD drive 8 mA,
@@ -184,8 +183,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
/* slot is the dram slot. Return size of side0 in lower 16-bit, /* slot is the dram slot. Return size of side0 in lower 16-bit,
* side1 in upper 16-bit, in units of 8MB */ * side1 in upper 16-bit, in units of 8MB */
static unsigned long static unsigned long spd_module_size(unsigned char slot)
spd_module_size(unsigned char slot)
{ {
/* for all the DRAMS, see if they are there and get the size of each /* for all the DRAMS, see if they are there and get the size of each
* module. This is just a very early first cut at sizing. * module. This is just a very early first cut at sizing.
@@ -195,6 +193,7 @@ spd_module_size(unsigned char slot)
unsigned int value = 0; unsigned int value = 0;
/* unsigned int module = ((0x50 + slot) << 1) + 1; */ /* unsigned int module = ((0x50 + slot) << 1) + 1; */
unsigned int module = 0x50 + slot; unsigned int module = 0x50 + slot;
/* is the module there? if byte 2 is not 4, then we'll assume it /* is the module there? if byte 2 is not 4, then we'll assume it
* is useless. * is useless.
*/ */
@@ -207,9 +206,11 @@ spd_module_size(unsigned char slot)
print_info(" is SDRAM "); print_info(" is SDRAM ");
banks = smbus_read_byte(module, 17); banks = smbus_read_byte(module, 17);
/* we're going to assume symmetric banks. Sorry. */ /* we're going to assume symmetric banks. Sorry. */
cols = smbus_read_byte(module, 4) & 0xf; cols = smbus_read_byte(module, 4) & 0xf;
rows = smbus_read_byte(module, 3) & 0xf; rows = smbus_read_byte(module, 3) & 0xf;
/* grand total. You have rows+cols addressing, * times of banks, times /* grand total. You have rows+cols addressing, * times of banks, times
* width of data in bytes */ * width of data in bytes */
/* Width is assumed to be 64 bits == 8 bytes */ /* Width is assumed to be 64 bits == 8 bytes */
@@ -229,10 +230,8 @@ spd_module_size(unsigned char slot)
} }
static int static int spd_num_chips(unsigned char slot)
spd_num_chips(unsigned char slot)
{ {
/* unsigned int module = ((0x50 + slot) << 1) + 1; */
unsigned int module = 0x50 + slot; unsigned int module = 0x50 + slot;
unsigned int width; unsigned int width;
@@ -262,7 +261,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4; val = (Trp << 7) | (Tras << 6) | (casl << 4) | 4;
print_debug_hex8(val); print_debug(" is the computed timing\n"); print_debug_hex8(val);
print_debug(" is the computed timing\n");
/* don't set it. Experience shows that this screwy chipset should just /* don't set it. Experience shows that this screwy chipset should just
* be run with the most conservative timing. * be run with the most conservative timing.
* pci_write_config8(0, 0x64, val); * pci_write_config8(0, 0x64, val);
@@ -296,6 +296,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
device_t north = 0; device_t north = 0;
uint32_t size, base, slot, ma; uint32_t size, base, slot, ma;
/* begin to initialize */ /* begin to initialize */
// I forget why we need this, but we do // I forget why we need this, but we do
dimms_write(0xa55a5aa5); dimms_write(0xa55a5aa5);
@@ -385,7 +386,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
print_debug(" is the chip size\r\n"); print_debug(" is the chip size\r\n");
if (size < 64) if (size < 64)
ma = 0; ma = 0;
if (size < 256) else if (size < 256)
ma = 8; ma = 8;
else else
ma = 0xe; ma = 0xe;

8
src/southbridge/via/vt8231/Config.lb
View File

@@ -1,2 +1,8 @@
config chip.h config chip.h
object vt8231.o driver vt8231.o
driver vt8231_lpc.o
driver vt8231_acpi.o
driver vt8231_ide.o
driver vt8231_nic.o
#driver vt8231_usb.o

10
src/southbridge/via/vt8231/chip.h
View File

@@ -4,18 +4,10 @@
extern struct chip_operations southbridge_via_vt8231_ops; extern struct chip_operations southbridge_via_vt8231_ops;
struct southbridge_via_vt8231_config { struct southbridge_via_vt8231_config {
/* PCI function enables */ /* enables of Non-PCI devices */
/* i.e. so that pci scan bus will find them. */
/* I am putting in IDE as an example but obviously this needs
* to be more complete!
*/
int enable_ide;
/* enables of functions of devices */
int enable_usb;
int enable_native_ide; int enable_native_ide;
int enable_com_ports; int enable_com_ports;
int enable_keyboard; int enable_keyboard;
int enable_nvram;
}; };
#endif /* _SOUTHBRIDGE_VIA_VT8231 */ #endif /* _SOUTHBRIDGE_VIA_VT8231 */

428
src/southbridge/via/vt8231/vt8231.c
View File

@@ -1,281 +1,45 @@
#include <console/console.h>
#include <arch/io.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <pc80/keyboard.h>
#include "vt8231.h" #include "vt8231.h"
#include "chip.h" #include "chip.h"
void pc_keyboard_init(void); /* Base 8231 controller */
static device_t lpc_dev;
void hard_reset(void) void hard_reset(void)
{ {
printk_err("NO HARD RESET ON VT8231! FIX ME!\n"); printk_err("NO HARD RESET ON VT8231! FIX ME!\n");
} }
static void usb_on(int enable)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* USB controller 1 */
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
/* enable USB1 */
if(dev2) {
if (enable) {
pci_write_config8(dev2, 0x3c, 0x05);
pci_write_config8(dev2, 0x04, 0x07);
} else {
pci_write_config8(dev2, 0x3c, 0x00);
pci_write_config8(dev2, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x10);
else
regval |= 0x10;
pci_write_config8(dev0, 0x50, regval);
}
/* enable USB2 */
if(dev3) {
if (enable) {
pci_write_config8(dev3, 0x3c, 0x05);
pci_write_config8(dev3, 0x04, 0x07);
} else {
pci_write_config8(dev3, 0x3c, 0x00);
pci_write_config8(dev3, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x20);
else
regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}
static void keyboard_on(void) static void keyboard_on(void)
{ {
unsigned char regval; unsigned char regval;
/* Base 8231 controller */ if (lpc_dev) {
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0); regval = pci_read_config8(lpc_dev, 0x51);
/* kevinh/Ispiri - update entire function to use
new pci_write_config8 */
if (dev0) {
regval = pci_read_config8(dev0, 0x51);
regval |= 0x0f; regval |= 0x0f;
pci_write_config8(dev0, 0x51, regval); pci_write_config8(lpc_dev, 0x51, regval);
} }
init_pc_keyboard(0x60, 0x64, 0); init_pc_keyboard(0x60, 0x64, 0);
} }
static void nvram_on(void) static void com_port_on(void)
{ {
/* #if 0
* the VIA 8231 South has a very different nvram setup than the
* piix4e ...
* turn on ProMedia nvram.
* TO DO: use the PciWriteByte function here.
*/
/*
* kevinh/Ispiri - I don't think this is the correct address/value
* intel_conf_writeb(0x80008841, 0xFF);
*/
}
/*
* Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void ethernet_fixup()
{
device_t edev;
uint8_t byte;
printk_info("Ethernet fixup\n");
edev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7, 0);
if (edev) {
printk_debug("Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(edev, PCI_COMMAND);
byte &= ~PCI_COMMAND_WAIT;
pci_write_config8(edev, PCI_COMMAND, byte);
} else {
printk_debug("VIA LAN not found\n");
}
}
/* we need to do things in this function so that PCI scan will find
* them. One problem here is that we can't use ANY of the new device
* stuff. This work here precedes all that.
* Fundamental problem with linuxbios V2 architecture.
* You can't do pci control in the C code without having done a PCI scan.
* But in some cases you need to to pci control in the c code before doing
* a PCI scan. But you can't use arch/romcc_io.h (the code you need) because
* that has functions with the same name but different type signatures
* (e.g. device_t). This needs to get fixed. We need low-level pci scans
* in the C code.
*/
static void vt8231_pci_enable(struct southbridge_via_vt8231_config *conf)
{
/*
unsigned long busdevfn = 0x8000;
if (conf->enable_ide) {
printk_debug("%s: enabling IDE function\n", __FUNCTION__);
}
*/
}
/* PIRQ init
*/
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
/*
Our IDSEL mappings are as follows
PCI slot is AD31 (device 15) (00:14.0)
Southbridge is AD28 (device 12) (00:11.0)
*/
static void pci_routing_fixup(struct device *dev)
{
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ12
*/
pci_write_config8(dev, 0x55, 0xb0);
pci_write_config8(dev, 0x56, 0xa5);
pci_write_config8(dev, 0x57, 0xc0);
}
// Standard southbridge components
printk_info("setting southbridge\n");
pci_assign_irqs(0, 0x11, southbridgeIrqs);
// Ethernet built into southbridge
printk_info("setting ethernet\n");
pci_assign_irqs(0, 0x12, enetIrqs);
// PCI slot
printk_info("setting pci slot\n");
pci_assign_irqs(0, 0x14, slotIrqs);
printk_info("%s: DONE\n", __FUNCTION__);
}
void
dump_south(void)
{
device_t dev0;
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
int i,j;
for(i = 0; i < 256; i += 16) {
printk_debug("0x%x: ", i);
for(j = 0; j < 16; j++) {
printk_debug("%02x ", pci_read_config8(dev0, i+j));
}
printk_debug("\n");
}
}
static void vt8231_init(struct southbridge_via_vt8231_config *conf)
{
unsigned char enables;
device_t dev0;
device_t dev1;
device_t devpwr;
// to do: use the pcibios_find function here, instead of
// hard coding the devfn.
// done - kevinh/Ispiri
printk_debug("vt8231 init\n");
/* Base 8231 controller */
dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* IDE controller */
dev1 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, 0);
/* Power management controller */
devpwr = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4, 0);
// enable the internal I/O decode
enables = pci_read_config8(dev0, 0x6C);
enables |= 0x80;
pci_write_config8(dev0, 0x6C, enables);
// Map 4MB of FLASH into the address space
pci_write_config8(dev0, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev0, 0x40);
pci_write_config8(dev0, 0x40, enables);
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev0, 0x42);
enables |= 0xf0;
pci_write_config8(dev0, 0x42, enables);
// Set bit 3 of 0x4a, to match award (dummy pci request)
enables = pci_read_config8(dev0, 0x4a);
enables |= 0x08;
pci_write_config8(dev0, 0x4a, enables);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev0, 0x4f);
enables |= 0x08;
pci_write_config8(dev0, 0x4f, enables);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev0, 0x58, 0x03);
// enable the ethernet/RTC
if(dev0) {
enables = pci_read_config8(dev0, 0x51);
enables |= 0x18;
pci_write_config8(dev0, 0x51, enables);
}
// enable com1 and com2. // enable com1 and com2.
if (conf->enable_com_ports) { enables = pci_read_config8(dev, 0x6e);
enables = pci_read_config8(dev0, 0x6e);
/* 0x80 is enable com port b, 0x10 is to make it com2, 0x8 /* 0x80 is enable com port b, 0x10 is to make it com2, 0x8
* is enable com port a as com1 kevinh/Ispiri - Old code * is enable com port a as com1 kevinh/Ispiri - Old code
* thought 0x01 would make it com1, that was wrong enables = * thought 0x01 would make it com1, that was wrong enables =
* 0x80 | 0x10 | 0x8 ; pci_write_config8(dev0, 0x6e, * 0x80 | 0x10 | 0x8 ; pci_write_config8(dev, 0x6e,
* enables); // note: this is also a redo of some port of * enables); // note: this is also a redo of some port of
* assembly, but we want everything up. * assembly, but we want everything up.
*/ */
@@ -283,159 +47,27 @@ static void vt8231_init(struct southbridge_via_vt8231_config *conf)
/* set com1 to 115 kbaud not clear how to do this yet. /* set com1 to 115 kbaud not clear how to do this yet.
* forget it; done in assembly. * forget it; done in assembly.
*/ */
#endif
}
// enable IDE, since Linux won't do it.
// First do some more things to devfn (17,0)
// note: this should already be cleared, according to the book.
enables = pci_read_config8(dev0, 0x50);
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev0, 0x50, enables);
// set default interrupt values (IDE)
enables = pci_read_config8(dev0, 0x4c);
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk_debug("setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev0, 0x4c, enables);
// set up the serial port interrupts.
// com2 to 3, com1 to 4
pci_write_config8(dev0, 0x46, 0x04);
pci_write_config8(dev0, 0x47, 0x03);
pci_write_config8(dev0, 0x6e, 0x98);
//
// Power management setup
//
// Set ACPI base address to IO 0x4000
pci_write_config32(devpwr, 0x48, 0x4001);
// Enable ACPI access (and setup like award)
pci_write_config8(devpwr, 0x41, 0x84);
// Set hardware monitor base address to IO 0x6000
pci_write_config32(devpwr, 0x70, 0x6001);
// Enable hardware monitor (and setup like award)
pci_write_config8(devpwr, 0x74, 0x01);
// set IO base address to 0x5000
pci_write_config32(devpwr, 0x90, 0x5001);
// Enable SMBus
pci_write_config8(devpwr, 0xd2, 0x01);
//
// IDE setup
//
if (! conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
enables = pci_read_config8(dev1, 0x42);
printk_debug("enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
pci_write_config8(dev1, 0x42, enables);
enables = pci_read_config8(dev1, 0x42);
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
} }
enables = pci_read_config8(dev1, 0x40); /* FixME: to be removed ? */
printk_debug("enables in reg 0x40 0x%x\n", enables); static void vt8231_enable(struct device *dev)
enables |= 3;
pci_write_config8(dev1, 0x40, enables);
enables = pci_read_config8(dev1, 0x40);
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev1, 0x41);
enables |= 0xf0;
pci_write_config8(dev1, 0x41, enables);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev1, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev1, 0x43, enables);
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev1, 0x44, 0x18);
// Use memory read multiple
pci_write_config8(dev1, 0x45, 0x1c);
// address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev1, 0x9);
printk_debug("enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
pci_write_config8(dev1, 0x9, enables);
enables = pci_read_config8(dev1, 0x9);
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev1, 0x4);
printk_debug("command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
pci_write_config8(dev1, 0x4, enables);
enables = pci_read_config8(dev1, 0x4);
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
if (! conf->enable_native_ide) {
// Use compatability mode - per award bios
pci_write_config32(dev1, 0x10, 0x0);
pci_write_config32(dev1, 0x14, 0x0);
pci_write_config32(dev1, 0x18, 0x0);
pci_write_config32(dev1, 0x1c, 0x0);
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev1, 0x3d, 00);
pci_write_config8(dev1, 0x3c, 0xff);
}
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev0, 0x40, 0x54);
ethernet_fixup();
// Start the rtc
rtc_init(0);
}
static void southbridge_init(struct device *dev) {
vt8231_init(dev->chip_info);
pci_routing_fixup(dev);
}
struct device_operations vt8231_dev_ops = {
.init = &southbridge_init,
};
static void southbridge_enable(struct device *dev)
{ {
dev->ops = &vt8231_dev_ops; struct southbridge_via_vt8231_config *conf = dev->chip_info;
if (!lpc_dev) {
/* the first time called, enable devices not on PCI bus
* FIXME: is that device struct there yet? */
lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8231, 0);
if (conf->enable_keyboard)
keyboard_on();
if (conf->enable_com_ports)
com_port_on();
}
} }
struct chip_operations southbridge_via_vt8231_ops = { struct chip_operations southbridge_via_vt8231_ops = {
CHIP_NAME("VIA vt8231") CHIP_NAME("VIA vt8231")
.enable_dev = southbridge_enable, .enable_dev = vt8231_enable,
}; };

44
src/southbridge/via/vt8231/vt8231_acpi.c Normal file
View File

@@ -0,0 +1,44 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "vt8231.h"
static void acpi_init(struct device *dev)
{
printk_debug("Configuring VIA ACPI\n");
// Set ACPI base address to IO 0x4000
pci_write_config32(dev, 0x48, 0x4001);
// Enable ACPI access (and setup like award)
pci_write_config8(dev, 0x41, 0x84);
// Set hardware monitor base address to IO 0x6000
pci_write_config32(dev, 0x70, 0x6001);
// Enable hardware monitor (and setup like award)
pci_write_config8(dev, 0x74, 0x01);
// set IO base address to 0x5000
pci_write_config32(dev, 0x90, 0x5001);
// Enable SMBus
pci_write_config8(dev, 0xd2, 0x01);
}
static struct device_operations acpi_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = acpi_init,
.enable = 0,
.ops_pci = 0,
};
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &acpi_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8231_4,
};

14
src/southbridge/via/vt8231/vt8231_early_smbus.c
View File

@@ -32,7 +32,6 @@ static void enable_smbus(void)
if (dev == PCI_DEV_INVALID) { if (dev == PCI_DEV_INVALID) {
die("SMBUS controller not found\r\n"); die("SMBUS controller not found\r\n");
} }
// set IO base address to SMBUS_IO_BASE // set IO base address to SMBUS_IO_BASE
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
@@ -86,8 +85,7 @@ static int smbus_wait_until_ready(void)
break; break;
} }
if (loops == (SMBUS_TIMEOUT / 2)) { if (loops == (SMBUS_TIMEOUT / 2)) {
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
SMBUS_IO_BASE + SMBHSTSTAT);
} }
} while (--loops); } while (--loops);
return loops ? 0 : -2; return loops ? 0 : -2;
@@ -206,8 +204,7 @@ static int smbus_read_byte(unsigned device, unsigned address)
#if 0 #if 0
/* SMBus routines borrowed from VIA's Trident Driver */ /* SMBus routines borrowed from VIA's Trident Driver */
/* this works, so I am not going to touch it for now -- rgm */ /* this works, so I am not going to touch it for now -- rgm */
static unsigned char smbus_read_byte(unsigned char devAdr, static unsigned char smbus_read_byte(unsigned char devAdr, unsigned char bIndex)
unsigned char bIndex)
{ {
unsigned int i; unsigned int i;
unsigned char bData; unsigned char bData;
@@ -265,8 +262,7 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
/* set the command/address... */ /* set the command/address... */
outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD); outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
/* set up for a byte data read */ /* set up for a byte data read */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
SMBUS_IO_BASE + SMBHSTCTL);
/* clear any lingering errors, so the transaction will run */ /* clear any lingering errors, so the transaction will run */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
@@ -275,8 +271,7 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
outb(0, SMBUS_IO_BASE + SMBHSTDAT0); outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
/* start the command */ /* start the command */
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
SMBUS_IO_BASE + SMBHSTCTL);
/* poll for transaction completion */ /* poll for transaction completion */
smbus_wait_until_done(); smbus_wait_until_done();
@@ -296,4 +291,3 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
#endif #endif

108
src/southbridge/via/vt8231/vt8231_ide.c Normal file
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@@ -0,0 +1,108 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "vt8231.h"
#include "chip.h"
static void ide_init(struct device *dev)
{
struct southbridge_via_vt8231_config *conf;
unsigned char enables;
if (!conf->enable_native_ide) {
// Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
printk_info("%s: enabling compatibility IDE addresses\n", __FUNCTION__);
enables = pci_read_config8(dev, 0x42);
printk_debug("enables in reg 0x42 0x%x\n", enables);
enables &= ~0xc0; // compatability mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk_debug("enables in reg 0x42 read back as 0x%x\n", enables);
}
enables = pci_read_config8(dev, 0x40);
printk_debug("enables in reg 0x40 0x%x\n", enables);
enables |= 3;
pci_write_config8(dev, 0x40, enables);
enables = pci_read_config8(dev, 0x40);
printk_debug("enables in reg 0x40 read back as 0x%x\n", enables);
// Enable prefetch buffers
enables = pci_read_config8(dev, 0x41);
enables |= 0xf0;
pci_write_config8(dev, 0x41, enables);
// Lower thresholds (cause award does it)
enables = pci_read_config8(dev, 0x43);
enables &= ~0x0f;
enables |= 0x05;
pci_write_config8(dev, 0x43, enables);
// PIO read prefetch counter (cause award does it)
pci_write_config8(dev, 0x44, 0x18);
// Use memory read multiple
pci_write_config8(dev, 0x45, 0x1c);
// address decoding.
// we want "flexible", i.e. 1f0-1f7 etc. or native PCI
// kevinh@ispiri.com - the standard linux drivers seem ass slow when
// used in native mode - I've changed back to classic
enables = pci_read_config8(dev, 0x9);
printk_debug("enables in reg 0x9 0x%x\n", enables);
// by the book, set the low-order nibble to 0xa.
if (conf->enable_native_ide) {
enables &= ~0xf;
// cf/cg silicon needs an 'f' here.
enables |= 0xf;
} else {
enables &= ~0x5;
}
pci_write_config8(dev, 0x9, enables);
enables = pci_read_config8(dev, 0x9);
printk_debug("enables in reg 0x9 read back as 0x%x\n", enables);
// standard bios sets master bit.
enables = pci_read_config8(dev, 0x4);
printk_debug("command in reg 0x4 0x%x\n", enables);
enables |= 7;
// No need for stepping - kevinh@ispiri.com
enables &= ~0x80;
pci_write_config8(dev, 0x4, enables);
enables = pci_read_config8(dev, 0x4);
printk_debug("command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
// Use compatability mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
pci_write_config32(dev, 0x1c, 0x0);
// Force interrupts to use compat mode - just like Award bios
pci_write_config8(dev, 0x3d, 00);
pci_write_config8(dev, 0x3c, 0xff);
}
}
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.enable = 0,
.ops_pci = 0,
};
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_82C586_1,
};

154
src/southbridge/via/vt8231/vt8231_lpc.c Normal file
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@@ -0,0 +1,154 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
#include "vt8231.h"
#include "chip.h"
/* PIRQ init
*/
void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);
static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 };
static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 };
/*
Our IDSEL mappings are as follows
PCI slot is AD31 (device 15) (00:14.0)
Southbridge is AD28 (device 12) (00:11.0)
*/
static void pci_routing_fixup(struct device *dev)
{
printk_info("%s: dev is %p\n", __FUNCTION__, dev);
if (dev) {
/* initialize PCI interupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11
PINTB = IRQ5
PINTC = IRQ10
PINTD = IRQ12
*/
pci_write_config8(dev, 0x55, 0xb0);
pci_write_config8(dev, 0x56, 0xa5);
pci_write_config8(dev, 0x57, 0xc0);
}
// Standard southbridge components
printk_info("setting southbridge\n");
pci_assign_irqs(0, 0x11, southbridgeIrqs);
// Ethernet built into southbridge
printk_info("setting ethernet\n");
pci_assign_irqs(0, 0x12, enetIrqs);
// PCI slot
printk_info("setting pci slot\n");
pci_assign_irqs(0, 0x14, slotIrqs);
printk_info("%s: DONE\n", __FUNCTION__);
}
static void vt8231_init(struct device *dev)
{
unsigned char enables;
struct southbridge_via_vt8231_config *conf = dev->chip_info;
printk_debug("vt8231 init\n");
// enable the internal I/O decode
enables = pci_read_config8(dev, 0x6C);
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
// Map 4MB of FLASH into the address space
pci_write_config8(dev, 0x41, 0x7f);
// Set bit 6 of 0x40, because Award does it (IO recovery time)
// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
// interrupts can be properly marked as level triggered.
enables = pci_read_config8(dev, 0x40);
pci_write_config8(dev, 0x40, enables);
// Set 0x42 to 0xf0 to match Award bios
enables = pci_read_config8(dev, 0x42);
enables |= 0xf0;
pci_write_config8(dev, 0x42, enables);
// Set bit 3 of 0x4a, to match award (dummy pci request)
enables = pci_read_config8(dev, 0x4a);
enables |= 0x08;
pci_write_config8(dev, 0x4a, enables);
// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
enables = pci_read_config8(dev, 0x4f);
enables |= 0x08;
pci_write_config8(dev, 0x4f, enables);
// Set 0x58 to 0x03 to match Award
pci_write_config8(dev, 0x58, 0x03);
// enable the ethernet/RTC
if (dev) {
enables = pci_read_config8(dev, 0x51);
enables |= 0x18;
pci_write_config8(dev, 0x51, enables);
}
// enable IDE, since Linux won't do it.
// First do some more things to devfn (17,0)
// note: this should already be cleared, according to the book.
enables = pci_read_config8(dev, 0x50);
printk_debug("IDE enable in reg. 50 is 0x%x\n", enables);
enables &= ~8; // need manifest constant here!
printk_debug("set IDE reg. 50 to 0x%x\n", enables);
pci_write_config8(dev, 0x50, enables);
// set default interrupt values (IDE)
enables = pci_read_config8(dev, 0x4c);
printk_debug("IRQs in reg. 4c are 0x%x\n", enables & 0xf);
// clear out whatever was there.
enables &= ~0xf;
enables |= 4;
printk_debug("setting reg. 4c to 0x%x\n", enables);
pci_write_config8(dev, 0x4c, enables);
// set up the serial port interrupts.
// com2 to 3, com1 to 4
pci_write_config8(dev, 0x46, 0x04);
pci_write_config8(dev, 0x47, 0x03);
pci_write_config8(dev, 0x6e, 0x98);
/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
pci_write_config8(dev, 0x40, 0x54);
//ethernet_fixup();
// Start the rtc
rtc_init(0);
}
static void southbridge_init(struct device *dev)
{
vt8231_init(dev);
pci_routing_fixup(dev);
}
static struct device_operations vt8231_lpc_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = &southbridge_init,
.scan_bus = scan_static_bus,
.enable = 0,
.ops_pci = 0,
};
static struct pci_driver lpc_driver __pci_driver = {
.ops = &vt8231_lpc_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8231,
};

37
src/southbridge/via/vt8231/vt8231_nic.c Normal file
View File

@@ -0,0 +1,37 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "vt8231.h"
/*
* Enable the ethernet device and turn off stepping (because it is integrated
* inside the southbridge)
*/
static void nic_init(struct device *dev)
{
uint8_t byte;
printk_debug("Configuring VIA LAN\n");
/* We don't need stepping - though the device supports it */
byte = pci_read_config8(dev, PCI_COMMAND);
byte &= ~PCI_COMMAND_WAIT;
pci_write_config8(dev, PCI_COMMAND, byte);
}
static struct device_operations nic_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = nic_init,
.enable = 0,
.ops_pci = 0,
};
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_VIA,
.device = PCI_DEVICE_ID_VIA_8233_7,
};

52
src/southbridge/via/vt8231/vt8231_usb.c Normal file
View File

@@ -0,0 +1,52 @@
static void usb_on(int enable)
{
unsigned char regval;
/* Base 8231 controller */
device_t dev0 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, 0);
/* USB controller 1 */
device_t dev2 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, 0);
/* USB controller 2 */
device_t dev3 = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, dev2);
/* enable USB1 */
if(dev2) {
if (enable) {
pci_write_config8(dev2, 0x3c, 0x05);
pci_write_config8(dev2, 0x04, 0x07);
} else {
pci_write_config8(dev2, 0x3c, 0x00);
pci_write_config8(dev2, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x10);
else
regval |= 0x10;
pci_write_config8(dev0, 0x50, regval);
}
/* enable USB2 */
if(dev3) {
if (enable) {
pci_write_config8(dev3, 0x3c, 0x05);
pci_write_config8(dev3, 0x04, 0x07);
} else {
pci_write_config8(dev3, 0x3c, 0x00);
pci_write_config8(dev3, 0x04, 0x00);
}
}
if(dev0) {
regval = pci_read_config8(dev0, 0x50);
if (enable)
regval &= ~(0x20);
else
regval |= 0x20;
pci_write_config8(dev0, 0x50, regval);
}
}

6
targets/via/epia/Config.lb
View File

@@ -13,7 +13,8 @@ romimage "normal"
option LINUXBIOS_EXTRA_VERSION=".0Normal" option LINUXBIOS_EXTRA_VERSION=".0Normal"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi # payload ../../../../../lnxieepro100.ebi
payload /etc/hosts
end end
romimage "fallback" romimage "fallback"
@@ -22,7 +23,8 @@ romimage "fallback"
option LINUXBIOS_EXTRA_VERSION=".0Fallback" option LINUXBIOS_EXTRA_VERSION=".0Fallback"
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf # payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
# payload ../../../../tg3--ide_disk.zelf # payload ../../../../tg3--ide_disk.zelf
payload ../../../../../lnxieepro100.ebi # payload ../../../../../lnxieepro100.ebi
payload /etc/hosts
end end
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"