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usbdebug: Support choice of EHCI controller

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Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.

Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kyösti Mälkki
2013-08-15 16:27:06 +03:00
parent 2410010018
commit 8101aa6bb0
11 changed files with 132 additions and 62 deletions
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26
src/southbridge/amd/sb700/enable_usbdebug.c
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@@ -27,12 +27,21 @@
#include <device/pci_def.h>
#include "sb700.h"
#define EHCI_EOR 0x20
#define DEBUGPORT_MISC_CONTROL 0x80
void set_debug_port(unsigned int port)
/*
* Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
* This code currently only supports the first one, i.e., USB Debug devices
* attached to physical USB ports belonging to the first EHCI device.
*/
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
u32 base_regs = CONFIG_EHCI_BAR + EHCI_EOR;
return PCI_DEV(0, 0x12, 2);
}
void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
{
u32 base_regs = pci_ehci_base_regs(dev);
u32 reg32;
/* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */
@@ -43,17 +52,10 @@ void set_debug_port(unsigned int port)
write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32);
}
/*
* Note: The SB700 has two EHCI devices, D18:F2 and D19:F2.
* This code currently only supports the first one, i.e., USB Debug devices
* attached to physical USB ports belonging to the first EHCI device.
*/
void enable_usbdebug(unsigned int port)
void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)
{
pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */
/* Set the EHCI BAR address. */
pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
pci_write_config32(dev, EHCI_BAR_INDEX, base);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);