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mainboard/intel/tglrvp: Remove unused PrmrrSize chip config

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Refer to commit 7736bfc

TEST=Able to build and boot TGLRVP.

Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2020-07-05 19:13:15 +05:30
parent 96dec04207
commit 8104effa0d
4 changed files with 2 additions and 15 deletions
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2
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@@ -38,8 +38,6 @@ chip soc/intel/tigerlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PrmrrSize" = "0x10000000"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"

2
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@@ -38,8 +38,6 @@ chip soc/intel/tigerlake
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
register "PrmrrSize" = "0x10000000"
register "PcieRpEnable[2]" = "1"
register "PcieRpEnable[3]" = "1"
register "PcieRpEnable[8]" = "1"