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soc/intel: Move fill_postcar_frame to memmap.c

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Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-16 10:37:15 +03:00
parent 4007d7f8c7
commit 81100bf7ff
14 changed files with 166 additions and 154 deletions
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27
src/soc/intel/quark/memmap.c
View File

@@ -13,6 +13,8 @@
* GNU General Public License for more details.
*/
#include <arch/cpu.h>
#include <arch/romstage.h>
#include <cbmem.h>
#include <soc/reg_access.h>
@@ -32,3 +34,28 @@ void *cbmem_top(void)
/* Return the top of memory */
return (void *)top_of_memory;
}
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t top_of_low_usable_memory;
/* Locate the top of RAM */
top_of_low_usable_memory = (uintptr_t) cbmem_top();
top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
/* Cache postcar and ramstage */
postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
MTRR_TYPE_WRBACK);
/* Cache RMU area */
postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
0x10000, MTRR_TYPE_WRTHROUGH);
/* Cache ESRAM */
postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
pcf->skip_common_mtrr = 1;
/* Cache SPI flash - Write protect not supported */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
}

25
src/soc/intel/quark/romstage/fsp2_0.c
View File

@@ -66,31 +66,6 @@ asmlinkage void car_stage_c_entry(void)
/* We do not return here. */
}
void fill_postcar_frame(struct postcar_frame *pcf)
{
uintptr_t top_of_ram;
uintptr_t top_of_low_usable_memory;
/* Locate the top of RAM */
top_of_low_usable_memory = (uintptr_t) cbmem_top();
top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
/* Cache postcar and ramstage */
postcar_frame_add_mtrr(pcf, top_of_ram - (16 * MiB), 16 * MiB,
MTRR_TYPE_WRBACK);
/* Cache RMU area */
postcar_frame_add_mtrr(pcf, (uintptr_t) top_of_low_usable_memory,
0x10000, MTRR_TYPE_WRTHROUGH);
/* Cache ESRAM */
postcar_frame_add_mtrr(pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
pcf->skip_common_mtrr = 1;
/* Cache SPI flash - Write protect not supported */
postcar_frame_add_romcache(pcf, MTRR_TYPE_WRTHROUGH);
}
static struct chipset_power_state power_state;
struct chipset_power_state *get_power_state(void)