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mb/google/brox: Sending End of Post (EOP) asynchronously

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Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.

BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.

Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian
2024-05-08 13:18:36 -06:00
committed by Subrata Banik
parent 7e3cabec51
commit 817c58c2ae
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/brox/Kconfig
View File

@@ -29,7 +29,7 @@ config BOARD_GOOGLE_BROX_COMMON
select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_TPM2
select PMC_IPC_ACPI_INTERFACE select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_LITE_SKU
# select SOC_INTEL_CSE_SEND_EOP_ASYNC select SOC_INTEL_CSE_SEND_EOP_ASYNC
select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES

2
src/soc/intel/alderlake/Kconfig
View File

@@ -82,7 +82,7 @@ config SOC_INTEL_ALDERLAKE
select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON
select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_CSE_SET_EOP
select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION